08 Jan, 2021
1 commit
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VDD SOC normal run changed to 0.85V
LPDDR4 freq0 change from 4000MTS to 2400MTSChange-Id: I69676ea5b582a817fb3c367bd861db96ba647540
(cherry picked from commit 1205f1edfaed1383181d4d52344cc55e5e92a351)
09 Nov, 2020
2 commits
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Since iMX8MP LPDDR4 EVK uses OD for VDD_SOC, so we can set GIC clock
to 500Mhz to align with kernel. For DDR4 EVK, uses default 400Mhz for
ND VDD_SOC.
Move the codes from SOC codes to board level to match with voltage
setting.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit ba50b01b74873cbddaeba61f69e7763a8ba63227) -
Because DDR4 runs at 3200MTS, this speed does not require to use overdrive
voltage for VDD_SOC, so set VDD_SOC to nominal 0.85v on DDR4 EVK.
The VDD_ARM was set to 0.95v to avoid timing risk from SOC to ARM when
VDD_SOC is 0.95v, set it back to 0.85v as well.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 5d556b8e214739deb5c3c71efa2ea8fc28f2a643)
19 Oct, 2020
1 commit
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This board uses 4GB DDR4 and replace emmc and flexspi to a raw NAND
socket. Add the support for this board, including SD boot, NAND boot,
and inline ECC (top 1/8 DDR used for ecc).Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 9b47aaef967bb7655312895c133e64e32e8f5b87)
16 Jun, 2020
1 commit
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Add mmc board level implementation for imx8mp, so we can support
boot from mmc besides ROMAPI.Test: eMMC/SD boot.
Change-Id: Ie3c28e5622dd819583e2146557ac75f89dbe19ef
Signed-off-by: Ji Luo
06 May, 2020
3 commits
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Change the SPL to non-DM and enable USB/tcpc, TMU, flexspi, FEC
and eQOS.Signed-off-by: Ye Li
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There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq,
then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM.Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus
clocks to OD frequency before it increases ARM voltage. So to conform to the
limitation, we'd better increases VDD_ARM to OD voltage in SPL.Signed-off-by: Ye Li
Reviewed-by: Anson Huang
(cherry picked from commit f9fdb7a6134d8929c2291303c006f7380d97faa8) -
Since rng_init is used arch_cpu_init, we have to clean up BSS section
before it.
Also remove the unnecessary memset to global data, because
board_init_f_init_reserve already memset it. If we memset it in board_init_f,
the gd->malloc_base is reset to 0 and will cause early malloc problem
when CONFIG_MALLOC_F_ADDR is not set.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit c36ae6a623b075192b20d93f9e3fe966961d86f4)
(cherry picked from commit f7e11efcb4689cd7e1068677454b2bd4480708f3)
18 Jan, 2020
2 commits
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At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.Signed-off-by: Simon Glass
[trini: Migrate a few more files]
Signed-off-by: Tom Rini -
Move this function out of common.h and into a relevant header file.
Signed-off-by: Simon Glass
08 Jan, 2020
1 commit
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Add basic i.MX8MP EVK board support
U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
power_pca9450b_init
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Failed to find clock node. Check device tree
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
CPU: Freescale i.MX8MP rev1.0 at 1000 MHz
Reset cause: POR
Model: NXP i.MX8MPlus EVK board
DRAM: 6 GiB
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0
u-boot=> mmc list
FSL_SDHC: 1 (SD)
FSL_SDHC: 2Signed-off-by: Peng Fan
