26 Jan, 2019
11 commits
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We have converted mmc to driver model on Poplar. So let's clean up
board level mmc initialization code.Signed-off-by: Shawn Guo
Acked-by: Manivannan Sadhasivam -
It adds compatible "hisilicon,hi3798cv200-dw-mshc" for Poplar SoC
Hi3798CV200 to probe this mmc driver.Signed-off-by: Shawn Guo
Acked-by: Manivannan Sadhasivam -
It adds missing pinctrl headers, updates clock header and sync up Poplar
device tree with kernel 4.20 release.Signed-off-by: Shawn Guo
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* Add pinctrl node for TLMM and add mux request for uart node.
* Rename uart to the actual board uart port.
* Fix indentendation of sdhc2 node.Signed-off-by: Ramon Fried
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The TLMM_GPIO_ENABLE bit is actually use to disable
the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer.Signed-off-by: Ramon Fried
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Signed-off-by: Ramon Fried
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Add pinctrl driver for Dragonboard820c, currently with only
one mux func to initialize pins for serial console.Signed-off-by: Ramon Fried
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The PLL for the UART was not set, and relied on previous
initializtion made by LK. add the appropriate initialization.Signed-off-by: Ramon Fried
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The imgextract command runs a number of checks of
the specified fit. Where it checks for a load address
for compressed images the logic in the expression
is inverted as fit_image_check_comp returns 1 on
success and not 0. -
Deploy u-boot-spl.stm32 binary in u-boot root folder like
the rest of the boards.
This makes it more streamlined when building in Yocto, Buildroot etc..Signed-off-by: Sean Nyekjaer
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A few platforms recently added in CONFIG_DFU_MMC under include/configs
rather than via the defconfig, update them.Signed-off-by: Tom Rini
25 Jan, 2019
20 commits
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mpc85xx config.mk: Add support for -msingle-pic-base
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Print information about Aquantia system interface and firmware loaded
on the phy.Signed-off-by: Valentin Catalin Neacsu
Acked-by: Joe Hershberger -
If System Interface protocol is USXGMII then enable USXGMII autoneg
Signed-off-by: Valentin Catalin Neacsu
Acked-by: Joe Hershberger -
No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.Cc: Simon Goldschmidt
Signed-off-by: Chris Packham
Acked-by: Joe Hershberger -
ether_crc was added to the core net code in commit 53a5c424bf86
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.Signed-off-by: Chris Packham
Acked-by: Joe Hershberger -
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
Standard Registers)Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.Signed-off-by: Carlo Caione
Acked-by: Joe Hershberger -
Some architectures (MIPS) needs mapping to access IOMEM.
Fix that.Fixes: f1dcc19b213d ("net: macb: Convert to driver model")
Signed-off-by: Ramon Fried
Acked-by: Joe Hershberger -
This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]Signed-off-by: Aditya Prayoga
Tested-by: Dennis Gilmore
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.Fix the check by using the bit width instead of hardcoded value(s).
Signed-off-by: Andreas Pretzsch
Acked-by: Joe Hershberger -
With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10
interfaces (0..9) as the number can only have one digit.On boards with more than 10 interfaces, this leads to the protection
and format checks being absent for eth10addr and above.Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow
more than one digit.Signed-off-by: Simon Goldschmidt
Acked-by: Joe Hershberger -
ETHADDR_WILDCARD is defined as the same value in both env_flags.h
and env_callback.hAs env_callback.h includes env_flags.h, remove the duplicate definition
from env_callback.hSigned-off-by: Simon Goldschmidt
Acked-by: Joe Hershberger -
When dealing with two ethernet ports and having "netretry" set
to "once", it could occur that the connection (e.g. an ARP
request) failed, hence the status of the netloop was
"NETLOOP_FAIL". Due to the setting of "netretry", the network
logic would then switch to the other network interface,
assigning "ret" with the return value of "net_start_again()".
If this call succeeded we would return 0 (i.e. success) to
the caller when in reality the network action failed.Signed-off-by: Thomas RIENOESSL
Reviewed-by: Christian Gmeiner
Acked-by: Joe Hershberger -
Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.Cc: Ken Ma
Cc: Stefan Chulski
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.Cc: Ken Ma
Cc: Stefan Chulski
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.Fix the padding code to zero out the padded bytes at the end.
Tested on socfpga gen5.
Signed-off-by: Simon Goldschmidt
Acked-by: Joe Hershberger -
The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.Fix this by correctly clearing the size mask before setting the new
length.Tested on socfpga gen5.
Signed-off-by: Simon Goldschmidt
Acked-by: Joe Hershberger
Reviewed-by: Philipp Tomsich -
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger
24 Jan, 2019
9 commits
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Xilinx changes for v2019.04
tools:
- Fix zynqmpimage generationzynq:
- Some configs/Kconfig/DT updates
- Enable REMAKE_ELF and OF_SEPARATE
- Topic boards update
- i2c cleanups and conversion to DM_I2Czynqmp:
- Some configs/Kconfig/DT updates
- Board config cleanup
- Move arch folder to mach-zynqmpversal:
- Enable DM_I2C, CMD_DMzynq-gem:
- Fix driver cache handlingi2c:
- Live tree simple updatephy:
- Fixed phy cleanuptravis:
- Wire Versal SoC -
Both boards have only controllers enabled that's why move to DM_I2C is
easy.Signed-off-by: Michal Simek
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There is no i2c connected in base DT that's why disable I2C commands.
Also remove zynq_zybo which is not needed now.Signed-off-by: Michal Simek
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With DM in place there is no need to have GEM addresses in headers. None
is using them.Signed-off-by: Michal Simek
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With DM in place there is no need to have GEM addresses in headers. None
is using them.Signed-off-by: Michal Simek
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Most of the memory is being consumed by device binding code,
more space needed for other data structures.Z-turn board has already hit the limit, others may follow soon.
Measuring only the memory consumed in device_bind_common, I've got
the following results (in decimal):root_driver: 108
mod_exp_sw: 108
amba: 120
serial@e0000000 aka uart0: 112
serial@e0001000 aka uart1: 88
spi@e000d000 aka qspi: 120
sdhci@e0100000 aka mmc0: 455
sdhci@e0100000.blk: 208
slcr@f8000000: 96
clkc@100: 72
(total) 1487 = 0x5cf of 0x600Signed-off-by: Anton Gerasimov
Signed-off-by: Michal Simek -
The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX
clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so
change it to run at 1000 and adjust the divisors accordingly. Also set the
GEM0 clock source to MIO instead of EMIO.Signed-off-by: Mike Looijmans
Signed-off-by: Michal Simek -
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz.
Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree.Signed-off-by: Mike Looijmans
Signed-off-by: Michal Simek -
Update cadence i2c driver to support livetree
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695afa794ac018a09e79a48120d322b60d)Signed-off-by: Michal Simek
