29 Oct, 2020
3 commits
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Add gpio node for SoC LS1012A
Signed-off-by: Biwen Li
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Add gpio node for SoC LS1021A
Signed-off-by: Biwen Li
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Fix a bug as belows,
=> gpio status -a
"Synchronous Abort" handler, esr 0x96000061
elr: 0000000082047964 lr : 0000000082047960 (reloc)
elr: 00000000fbd72964 lr : 00000000fbd72960
x0 : 00000000ffffffff x1 : 000000000000000a
x2 : 0000000000000020 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 0000000000000030
x6 : 0000000000000020 x7 : 0000000000000002
x8 : 00000000ffffffe0 x9 : 0000000000000008
x10: 0000000000000010 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000000230
x14: 00000000fbc23e9c x15: 00000000ffffffff
...
resetingSigned-off-by: Biwen Li
19 Oct, 2020
8 commits
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Since the HDP will be shared with i.MX. Move the common HDP library
codes to "driver/video/nxp/hdp" directory.
And use platform specified directory "driver/video/nxp/layerscape"
for LS driver codes and configurations.Signed-off-by: Ye Li
Reviewed-by: Alison Wang -
Initialize variable 'i2caddress' in print_vdd() to zero
Signed-off-by: Priyanka Singh
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Add lpuart config to enable lpuart feature.
Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang . -
Rename fsl-ls1028a-qds.dts to fsl-ls1028a-qds.dtsi so that
it can be used as common device tree for lpuart and duart.
Add lpuart device tree and duart device tree respectively
for qds which are used with duart and lpuart console.Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang -
Add lpuart nodes to enable lpuart feature
Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang -
mux changes in board file to enable lpuart1 and macro
define for lpuart1 used for mux changes in board configuation
register 13Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang -
Enable eMMC HS400 mode support on LX2162AQDS.
Signed-off-by: Yangbo Lu
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The register to enable/disable the write-permission of DBI RO
registers should be accessed via the CFG_ADDR/CFG_DATA registers
instead of accessing directly.Signed-off-by: Hou Zhiqiang
09 Oct, 2020
2 commits
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add alias for dspi
Signed-off-by: Zhao Qiang
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.Signed-off-by: Razvan Ionut Cirjan
05 Oct, 2020
1 commit
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Variable 'compat' is never NULL so drop the check.
Signed-off-by: Laurentiu Tudor
01 Oct, 2020
2 commits
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The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang -
make lx2162aqds platform to enable gpio driver.
Signed-off-by: Hui Song
Signed-off-by: Ran Wang
29 Sep, 2020
24 commits
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Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021Signed-off-by: Hou Zhiqiang
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Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang
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The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033Signed-off-by: Hou Zhiqiang
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Enable the DM_ETH and DM_MDIO config.
On P1020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.Signed-off-by: Hou Zhiqiang
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The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.Signed-off-by: Hou Zhiqiang
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Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
Add compatible string "gianfar" support and update the
device-tree-bindings doc.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang -
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang -
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
Use virtual address to access the MII block registers instead
of physical address.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
Reviewed-by: Hou Zhiqiang -
When an eTSEC is configured to use TBI, configuration of the
TBI is done through the MIIM registers for that eTSEC.
For example, if a TBI interface is required on eTSEC2, then
the MIIM registers starting at offset 0x2_5520 are used to
configure it.Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
Tested-by: Vladimir Oltean
Reviewed-by: Priyanka Jain -
The current code accesses eTSEC registers using physical
address directly, it's not correct, though no problem on
current platforms. It won't work on platforms, which does
not support 1:1 virtual-physical address map.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
Tested-by: Vladimir Oltean
Reviewed-by: Priyanka Jain -
Change the compatible string to "fsl,etsec2" for the Ethernet ports,
which is used in the current driver's match table.Fixes: 69a00875e3db ("doc: dt-bindings: Describe Freescale TSEC ethernet controller")
Signed-off-by: Hou Zhiqiang
Acked-by: Vladimir Oltean
Reviewed-by: Priyanka Jain -
Allow the MDIO devices to be probed based on the device tree.
Signed-off-by: Madalin Bucur
Signed-off-by: Priyanka Jain -
Add i2c node of p1010
Signed-off-by: Biwen Li
Reviewed-by: Priyanka Jain
Signed-off-by: Hou Zhiqiang -
Enable the DM PCIe driver in P1010RDB defconfigs.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Priyanka Jain -
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
for P1010RDB board.Signed-off-by: Hou Zhiqiang
Reviewed-by: Priyanka Jain
