27 Apr, 2020
40 commits
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Added default environment for hdp loading.
Added hdp loading as default for iMX8QM ARM2 and MEK boards.Signed-off-by: Oliver Brown
(cherry picked from commit 432e5b4347841095c3b5a8a0d106f35deadd006e)
(cherry picked from commit cb78a32fa8eb8c37932be003ebe4fa1f8c46c1d5) -
Port the HDMI lib frrom imx_v2019.04 u-boot, which is used for
HDP TX/RX firmware loading and HDMI displaySigned-off-by: Ye Li
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Since the freescale entity does not exist, remove it from CPU info print.
Signed-off-by: Ye Li
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This reverts commit bbe3d4a6c14e17d251029e4dde07f184244e9a4a.
If we set to periperal at exiting, will get a windows USB warning since
it detect a new connection on device mode. Remove this patch to fix
the problemSigned-off-by: Ye Li
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Add assigned clocks rate to USB3 node, so gadget driver can set
the clocks before probing the driver.Signed-off-by: Ye Li
Reviewe-by: Peng Fan
(cherry picked from commit bf02de76bd2b25a4f99d63c4ecc2cf3758095cbe) -
Current codes depend on default clock setting on SCFW, but on QXP c0, the
USB3 BUS clock requires a lower clock at 250Mhz. Found USB TRB error on
8DX (QXP c0), if we use default 500Mhz bus clock.Per SCFW suggestion, SW should be responsible for setting up these clocks
not depending on SCFW. So adding the clock set rate for all USB3 clocksSigned-off-by: Ye Li
Reviewe-by: Peng Fan
(cherry picked from commit 601da3c130fc6b0a864645009cf50c2d4a884d39) -
parameter 'end address' must be inclusive of address range.
And include cpu_func.h header fileSigned-off-by: Seb Fagard
Reviewed-by: Ye Li
(cherry picked from commit d17ae0d28de88bb637f6c1df5ba5c6d4f0779055) -
parameter 'end address' must be inclusive of address range.
Signed-off-by: Seb Fagard
Reviewed-by: Ye Li -
add the new imx8dxl into nandbcb support list.
Signed-off-by: Han Xu
Reviewed-by: Ye Li
(cherry picked from commit 3f791ca3cfb6e1e24e2c96223935f242d84c7818) -
add nand pad settings and init code in imx8dxl board file.
Signed-off-by: Han Xu
Reviewed-by: Ye Li
(cherry picked from commit fdb39fffc55c2ff02fe00a94b3f0208fae75d6df) -
add the nand related env settings for imx8dxl ddr3 evk
Signed-off-by: Han Xu
Reviewed-by: Ye Li
(cherry picked from commit 871df306ff98a93c70d7babe515acd8b680cf99b) -
add nand node and iomux configs for imx8dxl nand support in dts
Signed-off-by: Han Xu
Reviewed-by: Ye Li
(cherry picked from commit 58f2e4885b3e73e7fd071796a3d52ff900e1df9a) -
add new nand config for imx8dxl nand boot
Signed-off-by: Han Xu
Reviewed-by: Ye Li
(cherry picked from commit b71acb264d115300ad04f797e4758a2d2adc3f3f) -
Change the buffer to use the real buffer, not vring space.
Because we are going to let M4 publish the resource table into vring
space for kernel usage. uboot will overwrite it, so use the real shared
buffer space 0x90400000Script:
sed -i "s/CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000/CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000/" configs/*Signed-off-by: Peng Fan
Reviewed-by: Ye Li
(cherry picked from commit a996d907282746a4feca5a5c03f7e5326d9c1bda) -
Enable print to show the DRAM rate of current setting and training
result.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8fa319ae929c37f119fbfadfbb2881cba337b249) -
Since patch MLK-23656 will re-initialize the connectivty subsystem,
we don't need to reset ENET1 explicitely now. And this reset actually
has some limitations:
1. It needs power on the ENET1 resource firstly.
2. It will configure PER clock to 24M OSC. So previous clock setting
is lost.Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
(cherry picked from commit 861b3c324626b56e2c815bc04c342af53e957334) -
When boot from usb, scfw won't re-initialize the connectivity subsystem.
This special behavior is for uuu virtual console feature.
However, it causes entire connectivity SS using settings from ROM. We found
the bus clocks are from AVPLL not DPLL and lower than ADD required. It causes
OTG performance drop about 20% during fastboot because more NYET handshake
added into each transfer.To workaround the issue, we need to power off all usb resources to let connectivity
SS power down at early uboot phase. Then power on any resource in conn SS will
re-initialize the subsystem.Regard to auto USB port check, we only has this workaround in u-boot not in SPL.
SPL uses SDP to download other images, the sizes are very small and not impacted.Signed-off-by: Ye Li
Tested-by: Peter Chen
Acked-by: Peng Fan
(cherry picked from commit 625b061107928377f51859ee9c0558dc7d56c137) -
USB0 and USB1 work.
fastboot work
eqos Network work
Only 512MB in DDR3 evk boards.Signed-off-by: Frank Li
(cherry picked from commit 824d85bb9862264317c43ab10af80e3d946111ee) -
The previous NAND boot looking the rootfs by the mtd index, which is
easy get impacted by other mtd devices, such as SPI NOR. Changed it to
the unique nand rootfs partition name can avoid this issue.Signed-off-by: Han Xu
(cherry picked from commit a69e5febae6c1f98b2f2304501ca8fed085299b8) -
Old documentation styling mentioned all iMX8M devices variants (iMX8M,
iMX8MM, iMX8MN) for every SoC reference.As the secure/encrypted boot procedure is similar for all the variants
(including iMX8MP), make this information common for the whole iMX8M
family to keep the documentation clean instead of adding iMX8MP on every
reference.
Specific information for single variants is described when needed.Signed-off-by: Vanessa Maegima
Reviewed-by: Ye Li
(cherry picked from commit 24c72869a608ffbcce908770953a6d87514f2253) -
iMX8MP has shifted market segment fuse one bit from 0x440 [7:6] to [6:5],
correct it in imx common codes.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 798c09499190ed0fc66e3f0207bdc6343af6027f) -
Enable FDT overlay for all the i.MX 8 series.
Instead of modifying the FDT like done currently,
allow u-boot to apply an overlay instead.
Fallback to previous imlementation if overlay fails.Signed-off-by: Silvano di Ninno
Reviewed-by: Ye Li
(cherry picked from commit 13463bf47b27771976f8b824a20224f599a0518a) -
v5.4 kernel has changed the nodes structure in its DTB. u-boot
implements the ft_system_setup to update kernel DTB for imx8m
variant parts (modules fused). Need sync the codes to support
v5.4 DTB.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 3f55fbb3c010389868f218482413f1375661eaeb) -
In uMCTL2 Databook, for LPDDR4, it is recommended to set
this register to 1. This can avoid ddr bandwidth is lower
after booting with running for a while.Signed-off-by: Jian Li
Reviewed-by: Ye Li
(cherry picked from commit 80f2cd3f62f55a75584747d9107446d0802fc90a) -
Add defconfig to support flexspi boot for both SPL and u-boot
Signed-off-by: Ye Li
Tested-by: Han Xu
Acked-by: Peng Fan
(cherry picked from commit dea8a1e5e104310a07d670c86aa416d7292c1564) -
usb boot EQOS TSN doesn't work, because it required to reset
EQOS TSN resource.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
(cherry picked from commit 52462b15e6bceac27759b6fa57552dae0f1cc6b6) -
On CDNS3 usb, the IOC interrupt for IN is triggered when data
move from memory to FIFO, but not for the transfer completion.When running fastboot command "continue" to disconnect USB device.
The last message "OKAY" sent from device setups a callback to IOC
interrupt handler and disconnect with host in this callback.
However, the real transfer hasn't finished due to host doesn't send
IN at that time, it causes the error at host side.This patch will reset all enabled endpoints in pull up before disable
the device mode. The reset checks the EP_STS.BUFFEREMPTY bit to ensure
data has sent to host.Signed-off-by: Ye Li
Signed-off-by: Peter Chen
Reviewed-by: Peter Chen
(cherry picked from commit 9be87bc89c1e75755b524703dc536c93bd3fbe5c) -
USB OH clock is default enabled by SCFW because it shared
between two USB controller.Signed-off-by: Frank Li
(cherry picked from commit 7a8ec829d4410c51550ad7a589645595042ba541) -
fix usb_power_config hard code to first one
Signed-off-by: Frank Li
(cherry picked from commit dbe54e1f3625269f7bc422ccf53693cb9e0f949b) -
Add device trees, configs and board files for
the i.MX8DXL EVK board.Signed-off-by: Ye Li
Signed-off-by: Teo Hall
(cherry picked from commit f0238679d332f1af2148d467804a93de8f868bd5) -
Reset PHY once is enough that can reduce the time cost
to get IP after the first time.Reviewed-by: Frank Li
Signed-off-by: Fugang Duan
(cherry picked from commit 2342d9670a6e349a462e24febdc085aac3bedcee) -
Update dwc qos driver for i.MX8DXL
Signed-off-by: Fugang Duan
(cherry picked from commit d1e718565972495c99345ee8119651ffa14a3238) -
Add soc id in cpu codes and conditionals.
Also add support for v2x container on 8DXL.Signed-off-by: Ye Li
Signed-off-by: Teo Hall
(cherry picked from commit 35691a6b85c3240b0e3b9f9a8da9fc6328bf92d8) -
Add clocks required for new i.MX8DXL SoC. Since most of clocks are
same as iMX8QXP, share the same driver but with iMX8DXL new clocks added.Signed-off-by: Fugang Duan
Signed-off-by: Teo Hall
(cherry picked from commit f9c23b2df504c5db5f8f4567ee4c92f2439308fc)
Signed-off-by: Ye Li -
Add pads for i.MX8DXL SoC
Signed-off-by: Teo Hall
(cherry picked from commit eccdb0d167e10dc8f179c00cbb1ebee72d93225b) -
Current codes assume the OPTEE address is at the end of first DRAM bank.
Adjust the process to allow OPTEE in the middle of first bank.When OPTEE memory is removed from first bank, it may split the first bank
to two banks, so increase the CONFIG_NR_DRAM_BANKS and adjust the MMU
table for the split case.Signed-off-by: Ye Li
Signed-off-by: Silvano di Ninno
Tested-by: Silvano di Ninno
(cherry picked from commit e2a3b770ef847354ebe85c363608f27381d48adc) -
Since inline ECC feature is disabled in default imx8mp_evk_defconfig, in
order to test the new feature, add a new config file based on
imx8mp_evk_defconfig with inline ECC enabled.Signed-off-by: Sherry Sun
Reviewed-by: Ye Li
(cherry picked from commit 8dff0e01bd5411caa757fe4c296fccbb7e1bdd2b) -
If inline ECC is enabled on imx8mp, then the ECC region should be
reserved. Since the limit of the ddr address map when use inline ecc
and 6G memory, ECC region have to be divided into three parts. So these
three parts ECC region should be set as reserved-memory with no-map.Signed-off-by: Sherry Sun
(cherry picked from commit 0ea77fc9364e46e897cfa554d93895595aaf2a20) -
Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which
can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board.Signed-off-by: Sherry Sun
(cherry picked from commit 6f491bb187dffbb3d235681c0858df515f90f504) -
The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.Signed-off-by: Jacky Bai
Reviewed-by: Jian Li
Reviewed-by: Ye Li
(cherry picked from commit 182be50944e9c4c2892d64a4a40ab2dfec5ca7b8)
