10 Jan, 2014
4 commits
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GPIO dummy routines are required for fdt build, may be removed
these dependencies once the u-boot fdt is fully optimized.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch provides a basic fdt support for zynq u-boot.
zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zedEnabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.Signed-off-by: Jagannadha Sutradharudu Teki
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Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.Added this functionality on board_late_init as it's not
needed for normal initializtion part.Signed-off-by: Jagannadha Sutradharudu Teki
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The toolchain sets __aarch64__ for both LE and BE. In the case of
posix_types.h we cannot reliably use config.h as that will lead to
problems. In the case of byteorder.h it's clearer to check the EB flag
being set in either case instead.Cc: David Feng
Signed-off-by: Tom RiniAmended by Albert ARIBAUD to
actually remove the config.h include from the posix_types.h
files, with permission from Tom Rini.
09 Jan, 2014
1 commit
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Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott WoodSigned-off-by: David Feng
06 Jan, 2014
2 commits
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Conflicts:
include/micrel.hThe conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
03 Jan, 2014
9 commits
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Enable fuse supply before fuse programming and disable after.
Signed-off-by: Sergey Alyoshin
Reviewed-by: Benoît Thébaudeau -
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.Signed-off-by: Otavio Salvador
Acked-by: Stefano Babic -
The macro allows easy setting in per-pin, as for example:
,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.
The following quote from the datasheet:
,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.Thanks for Benoît Thébaudeau , Fabio
Estevam and Eric Bénard
for helping to properly trace this down.Signed-off-by: Otavio Salvador
Acked-by: Stefano Babic -
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.Signed-off-by: Anson Huang
Signed-off-by: Jason Liu
Signed-off-by: Fabio Estevam -
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.Signed-off-by: Fabio Estevam
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Introduce set_ldo_voltage() so that all three LDO regulators can be configured.
Signed-off-by: Fabio Estevam
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mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0Signed-off-by: Fabio Estevam
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Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;Signed-off-by: Anson Huang
Signed-off-by: Jason Liu
Signed-off-by: Fabio Estevam -
set_vddsoc() is not used anywhere else, so make it static.
Signed-off-by: Fabio Estevam
30 Dec, 2013
8 commits
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This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Naveen Krishna Chatradhi
Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Add dmc and phy_control register structure for 5420.
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Add structure for power register for Exynos5420
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Adds base addresses of various IPs and controllers required for
Exynos5420.Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang
19 Dec, 2013
16 commits
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Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks
board with SATA support, because sata is not compiled.Signed-off-by: Stefano Babic
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GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG registerSigned-off-by: Lokesh Vutla
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AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.Signed-off-by: Lokesh Vutla
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Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.Signed-off-by: Lokesh Vutla
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini -
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHzTouching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla -
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.Signed-off-by: Lokesh Vutla
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Current Booting devices list is different from that of AM33xx.
Updating the same.Signed-off-by: Lokesh Vutla
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Selecting the Master osc clk as Timer2 clock source.
Signed-off-by: Lokesh Vutla
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Add support for reading onboard EEPROM to enable
board detection.Signed-off-by: Sekhar Nori
Signed-off-by: Lokesh Vutla -
Use ti_armv7_common.h config file to inclde the common
configs.Signed-off-by: Lokesh Vutla
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PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.Signed-off-by: Lokesh Vutla
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The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.Signed-off-by: Alban Bedel
Acked-by: Stephen Warren
Tested-by: Stephen Warren
Signed-off-by: Tom Warren -
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
Signed-off-by: Alban Bedel
Reviewed-by: Julian Scheel
Signed-off-by: Tom Warren -
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.Signed-off-by: Thierry Reding
Signed-off-by: Tom Warren -
The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.Signed-off-by: Jimmy Zhang
Reviewed-by: Tom Warren
Signed-off-by: Thierry Reding
Acked-by: Stephen Warren
Signed-off-by: Tom Warren
