04 Dec, 2017
1 commit
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Signed-off-by: Dmitry Korunov
01 Dec, 2017
5 commits
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The reset circuitry in the RK3399 only resets 'almost all logic' when
a software reset is performed. To make our software maintenance
easier in the future, we want to have the option (controlled by a DTS
property) to force all reset causes other than a power-on reset to
trigger a power-on reset via a GPIO trigger.This adds the necessary support to the rk3399-puma (i.e. RK3399-Q7)
board-support and the documentation for the new property
(sysreset-gpio) within the /config-node.Signed-off-by: Philipp Tomsich
Tested-by: Klaus Goger
Reviewed-by: Simon Glass -
For some versions of the RK3399-Q7 (at least revisions v1.1 and v1.2
are affected), we need to turn on the power for the port connected to
the on-module USB hub only when the device is probed for the first
time to ensure that the hub does not enter a low-power mode (that
U-Boot's USB stack can't deal with).Note that this is needed for U-Boot only, as Linux eventually manages
to attach the hub even when it has entered into its low-power state
(when the hub wakes up the next time) after a few seconds.Signed-off-by: Philipp Tomsich
Tested-by: Jakob Unterwurzacher -
Even if the board-specific directory Makefile doesn't have any
targets, it still needs to exist.This adds a minimal Makefile for the board/rockchip/evb_rk3128
directory and a evk-rk3128.c (as built-in.o needs to be built
for every directory that a Makefile gets run for).Fixes: c7a6866 ("rockchip: rk3128: add evb-rk3128 support")
Signed-off-by: Philipp Tomsich -
evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
- 2 USB2.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;Signed-off-by: Kever Yang
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich -
After commit d962e5dadc2c("rockchip: mkimage: use spl_boot0 for all Rockchip SoCs"),
the mkimage will not pad the Tag memroy, so we shoud
pass a Taged ddr.bin/spl.bin to it.Signed-off-by: Andy Yan
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich
30 Nov, 2017
14 commits
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Rework the ULCB CPLD driver and make it into a sysreset driver,
since that is what the ULCB CPLD driver is mostly for.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
The order of members in struct hws_topology_map is cas_wl, cas_l. The
comments in the original db-88f6820-gp.c had this wrong and have been
copied to other Armada-385 based boards. Practically this hasn't made a
difference since all these boards set both cas_wl and cas_l to 0
(autodetect) but if there were ever a board that did need to set these
explicitly they would run into unexpected issued.Update the comments to reflect the correct order of structure members.
Reported-by: Tobi Wulff
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
This board is based on the Atmel sama5d3 eval boards.
Supporting the following features:
- Boot from NAND Flash
- Ethernet
- FIT
- SPLSigned-off-by: Ben Whitten
Signed-off-by: Dan Kephart -
This board is based on the Atmel 9x5 eval board.
Supporting the following features:
- Boot from NAND Flash
- Ethernet
- FIT
- SPLSigned-off-by: Ben Whitten
Signed-off-by: Dan Kephart -
Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board
which was a prototype.Signed-off-by: Ludovic Desroches
Signed-off-by: Wenyou Yang -
MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family
and used a common MPU's region config.Only one exception for STM32H7 which doesn't have device area
located at 0xA000 0000.For STM32F4, configure_clocks() need to be moved from arch_cpu_init()
to board_early_init_f().Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha -
In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.hSigned-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha -
AG101P/AE3XX enable ftsdc010 dm flow.
Signed-off-by: Rick Chen
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Drop the ad-hoc DRAM configuration with macros and just decode
the DRAM configuration from device tree instead. This makes it
far cleaner and easier.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Since checkboard() is gone, rmobile_sysinfo is also pointless on Gen3.
Furthermore, nuke ad-hoc CONFIG_RCAR_BOARD_STRING which is also dead.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
We can now use rmobile_get_cpu_type() to check the CPU ID rather
than using a macro, make it so.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Since the Gen3 clock driver now has a .remove callback, it is no
longer necessary to shut the clock down before booting Linux in the
arch_preboot_os hook. Stop using it and while doing so, remove all
the ad-hoc config options which this hook used.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
29 Nov, 2017
12 commits
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Xilinx changes for v2018.1
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handlingZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 boardDrivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support -
After some generic cleanup adding ps7_init* to repository
is not big pain now.Signed-off-by: Michal Simek
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Show information about silicon in bootlog.
Signed-off-by: Michal Simek
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Use generic implementation. It will also reduce config data size for
converted boards.Signed-off-by: Michal Simek
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This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.The patch is also marking ps7_config as weak function.
Signed-off-by: Michal Simek
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There is no reason to call separate function.
Signed-off-by: Michal Simek
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SPL is not calling this code that's why it is dead code and can be
removed.Signed-off-by: Michal Simek
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U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs which generates it using the srec_cat tool available from
the SRecord project, and build it by default when srec_cat is present.Signed-off-by: Paul Burton
Cc: Daniel Schwierzeck
Cc: u-boot@lists.denx.de -
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.Signed-off-by: Paul Burton
Cc: Daniel Schwierzeck
Cc: u-boot@lists.denx.de -
The lowlevel_display() function includes a "1:" label which is never
used. Remove it.Signed-off-by: Paul Burton
Cc: Daniel Schwierzeck -
The boston lowlevel_init() function zeroes the return register v0,
despite the function not being expected to return a value & that value
never being used.Remove the redundant assignment to v0.
Signed-off-by: Paul Burton
Cc: Daniel Schwierzeck
28 Nov, 2017
7 commits
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This ID is available on zc1254.
Signed-off-by: Michal Simek
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Version string has unused fields 31:20 which can be used for exporting 9
bits from efuse IPDISABLE regs to recognize eg/cg/ev devices.These efuse bits are setup for certain devices.
Signed-off-by: Michal Simek
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Warning is reported by checkpatch.
Signed-off-by: Michal Simek
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Add configuration files/dtses for mini u-boot configurations which runs
out of OCM.ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE
0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE 0x40000
was hardcoded.Signed-off-by: Michal Simek
Reviewed-by: Simon Glass -
There is no reason not to return return value from above function.
Signed-off-by: Michal Simek
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Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
booting from SD.Signed-off-by: Tom McLeod
Cc: Michal Simek
CC: Albert Aribaud
Signed-off-by: Michal Simek
27 Nov, 2017
1 commit
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Signed-off-by: Tom Rini