13 Feb, 2020
1 commit
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There is no reason to show RAM_ROCKCHIP_DEBUG entry in other .config files
as I see it for Xilinx ZynqMP.\# CONFIG_U_QE is not set
\# CONFIG_RAM is not set
CONFIG_RAM_ROCKCHIP_DEBUG=yAdd missing dependency on RAM_ROCKCHIP driver.
Signed-off-by: Michal Simek
06 Feb, 2020
3 commits
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Most files don't need this header and it pulls in quite of lots of stuff,
malloc() in particular. Drop it.Signed-off-by: Simon Glass
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
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At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin
30 Jan, 2020
3 commits
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No need to do twice data training for rk3328 ddr sdram, we re-use the
setting for both channel. And adjust the sdram_init properly for correct
init flow.Signed-off-by: Kever Yang
Signed-off-by: YouMin Chen -
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.The rest of rockchip cru files will add it in future.
Reviewed-by: Kever Yang
Signed-off-by: Jagan Teki -
In the RK3399 DRAM driver, the function set_ds_odt() supports operating
in two different modes, selected by the ctl_phy_reg argument: when true,
the function reads and writes directly from the DRAM registers, accessed
through "chan->pctl->denali_*"; when false, the function reads and
writes from an array, accessed through "params->pctl_regs.denali_*",
which is written to DRAM registers at a later time.However, phy_config_io(), which is called by set_ds_odt() to do a subset
of its register operations, operates directly on DRAM registers at all
times. This means that it reads incorrect values (and writes new values
prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by
passing in the address of the registers to work with.This prevents an "Invalid DRV value" error in the SPL debug log and
(presumably) results in a more correct end state. See the following logs
from a RK3399 NanoPi M4 board (4GB LPDDR3):Before:
sdram_init() Starting SDRAM initialization...
phy_io_config() Invalid DRV value.
phy_io_config() Invalid DRV value.
sdram_init() sdram_init: data trained for rank 2, ch 0
phy_io_config() Invalid DRV value.
phy_io_config() Invalid DRV value.
sdram_init() sdram_init: data trained for rank 2, ch 1
Channel 0: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
sdram_init() Finish SDRAM initialization...After:
sdram_init() Starting SDRAM initialization...
sdram_init() sdram_init: data trained for rank 2, ch 0
sdram_init() sdram_init: data trained for rank 2, ch 1
Channel 0: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
sdram_init() Finish SDRAM initialization...Signed-off-by: Thomas Hebb
Reviewed-by: Kever Yang
18 Jan, 2020
2 commits
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At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.Signed-off-by: Simon Glass
[trini: Migrate a few more files]
Signed-off-by: Tom Rini -
These functions relate to memory init so move them into the init
header.Signed-off-by: Simon Glass
15 Jan, 2020
1 commit
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Add SDRAM driver for i.MXRT SoCs.
Signed-off-by: Giulio Benetti
17 Nov, 2019
19 commits
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A dm based dram driver for rk3308 u-boot
to get capacity.Signed-off-by: Andy Yan
Reviewed-by: Kever Yang -
There are some code different with rockchip vendor code which may lead
to different bugs, including:
1) Fix setting error about LPDDR3 dram size ODT.
2) Set phy io speed to 0x2.
3) Fix setting error about phy_pad_fdbk_drive.
4) Fix setting error about PI_WDQLVL_VREF_ENSigned-off-by: YouMin Chen
Signed-off-by: Kever Yang -
Update the calculation of the stride to support all the DRAM case.
Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
The io setting are updated after some bugfix in different rk3399 boards,
sync the code from vendor.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip
vendor code;Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
Add capacity detect for rk3399 so that the driver able to detect the
capacity automatically.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
Clean up the sdram_init to keep sync with rockchip source code.
Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
Correct the register to its correct name.
Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
Clean up rk3399 dram driver source code for more readable.
Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
The debug info for dram is main about the capacity related info which is
very important the board init, so set this default enable.Signed-off-by: Kever Yang
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The functions for dram info print are part of common code.
Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang -
The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.Signed-off-by: YouMin Chen
Signed-off-by: Kever Yang
10 Nov, 2019
2 commits
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Fix a typo that caused incorrect values to be loaded into the DRAM
controller's deskew registers.Signed-off-by: Simon South
Reviewed-by: Kever Yang -
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units
for the DDR frequency, causing the DRAM controller to be misconfigured
in most cases.Signed-off-by: Simon South
Reviewed-by: Kever Yang
26 Oct, 2019
3 commits
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The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.Signed-off-by: Kevin Scholz
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Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.Signed-off-by: James Doublesin
Signed-off-by: Lokesh Vutla -
Added training support for LPDDR4 and DDR3L DDRs. Also added/changed
some register configuration to support all 3 DDR typesSigned-off-by: James Doublesin
Signed-off-by: Lokesh Vutla
19 Sep, 2019
1 commit
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Few of the rk3288 boards like tinker, vyasa are using
TPL, SPL bootchain so the dram initialization must needed
during TPL stage. So add proper ifconstruct to satisfy
both TPL, SPL and SPL-only bootchain boards.This eventually fixing TPL to SPL handoff, otherwise missing
dram initilaztion at TPL stage would leads to SPL hang.Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
27 Aug, 2019
5 commits
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Add pattern for infinite test_read and test_write, that
allow to change the pattern to test without recompilation;
default pattern is 0xA5A5AA55.Signed-off-by: Patrick Delaunay
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Avoid watchdog during infinite DDR test.
Signed-off-by: Patrick Delaunay
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Reduce verbosity of the infinite tests to avoid CubeMX issue.
test and display loop by 1024*1024 accesses: read or write.Signed-off-by: Patrick Delaunay
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If user choose to test memory size is 1GByte (0x40000000),
memory address would overflow in test "Random" and
test "FrequencySelectivePattern".
Thus the system would hangs up when running DDR test.Signed-off-by: Patrick Delaunay
Signed-off-by: Bossen WU -
Signed-off-by: Patrick Delaunay
