13 Jun, 2009
12 commits
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When CONFIG_I2C_MUX was defined the output of 'help i2c' was not
correct, eg:=> help i2c
i2c bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes.
speed [speed] - show or set I2C bus speed
i2c dev [dev] - show or set current I2C bus
...It has been changed to:
i2c speed [speed] - show or set I2C bus speed
i2c bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes
i2c dev [dev] - show or set current I2C bus
...Signed-off-by: Peter Tyser
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Signed-off-by: Peter Tyser
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argc and argv should only be modified once instead of once for
every i2c sub-commandSigned-off-by: Peter Tyser
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The individual i2c commands imd, imm, inm, imw, icrc32, iprobe, iloop,
and isdram are no longer available so all references to them have been
updated to the new form of "i2c ".Signed-off-by: Peter Tyser
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The following individual I2C commands have been removed: imd, imm, inm,
imw, icrc32, iprobe, iloop, isdram.The functionality of the individual commands is still available via
the 'i2c' command.This change only has an impact on those boards which did not have
CONFIG_I2C_CMD_TREE defined.Signed-off-by: Peter Tyser
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New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions
replace a number of architecture-specific implementations.Also, providing default functions will allow all boards to enable
CONFIG_I2C_CMD_TREE. This was previously not possible since the
tree-form of the i2c command provides the ability to display and modify
the i2c bus speed which requires i2c_[set|get]_bus_speed() to be
present.Signed-off-by: Peter Tyser
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Add "_test" to cm5200's function test command names to prevent
overlap with common, global function names. Originally, the
"do_i2c" function test command interfered with
common/cmd_i2c.c's "do_i2c" when CONFIG_I2C_CMD_TREE was defined.The functions were also made static as they are not globally accessed.
Signed-off-by: Peter Tyser
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Add the i2c_init() function so that the tsi108_i2c.c driver fits
U-Boot's standard I2C API which is utilized by cmd_i2c.cSigned-off-by: Peter Tyser
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Add standard CONFIG_SYS_I2C_SPEED define for the mpc7448hpc2 so that
it can use the common 'i2c speed' command. Note that the I2C controller
utilized by the mpc7448hpc2 has a fixed speed and cannot be changed
dynamically.Signed-off-by: Peter Tyser
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The following changes were made, primarily to bring the Marvell i2c
driver in line with U-Boot's current I2C API:
- Made i2c_init() globally accessible
- Made i2c_read() and i2c_write() return an integer
- Updated i2c_init() calls to pass in CONFIG_SYS_I2C_SLAVE in the
offhand chance someone adds slave support in the futureSigned-off-by: Peter Tyser
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The following changes were made, primarily to bring the cpci750 i2c
driver in line with U-Boot's current I2C API:
- Made i2c_init() globally accessible
- Made i2c_read() and i2c_write() return an integer
- Updated i2c_init() calls to pass in CONFIG_SYS_I2C_SLAVE in the
offhand chance someone adds slave support in the futureSigned-off-by: Peter Tyser
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Many boards/controllers/drivers don't support an I2C slave interface,
however CONFIG_SYS_I2C_SLAVE is used in common code so provide a
defaultSigned-off-by: Peter Tyser
12 Jun, 2009
8 commits
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The ddr code computes most things as 64-bit quantities and had some places
in the middle that it was using phy_addr_t and phys_size_t.Instead we use unsigned long long through out and only at the last stage of
setting the LAWs and reporting the amount of memory to the board code do we
truncate down to what we can cover via phys_size_t.This has the added benefit that the DDR controller itself is always setup
the same way regardless of how much memory we have. Its only the LAW
setup that limits what is visible to the system.Signed-off-by: Kumar Gala
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Signed-off-by: Kumar Gala
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Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala -
MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
those pins before using UART1.Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala -
Signed-off-by: Haiying Wang
Signed-off-by: Yu Liu
Signed-off-by: Kumar Gala -
- Increase the size of malloc to 512KB because MPC8569MDS needs more memory for
malloc to support up to eight Ethernet interfaces.
- Move Environment address out of uboot thus the saved environment variables
will not be erased after u-boot is re-programmed.Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala -
MPC8569 has 128K bytes MURAM.
Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala
10 Jun, 2009
14 commits
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
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Signed-off-by: Shinya Kuribayashi
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Update CHANGELOG
Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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In do_readpage(), don't free 'dn' if its allocation failed.
Signed-off-by: Daniel Mack
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Signed-off-by: Wolfgang Denk
Tested-by: Mikhail Zaturenskiy -
Remove "saveenv" from "update" definition: the environment is outside
the U-Boot image on TQM85xx and therefor not affected by updates.Also "beautify" code a bit (vertical alignment).
Signed-off-by: Wolfgang Denk
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Old TQM85xx boards had 'M' type Spansion Flashes from the S29GLxxxM
series while new boards have 'N' type Flashes from the S29GLxxxN
series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.We now change the configuration to the new flash types for all
boards; this also works on old boards - we just waste two flash
sectors for the environment which could be smaller there.Signed-off-by: Wolfgang Denk
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The SYS_CLK_IN of MPC8569MDS is 66.66MHz,
The DDR_CLK_IN is same with SYS_CLK_IN in 8569 processor.
so, change the SYS_CLK_IN from 66MHz to 66.66MHz.Signed-off-by: Dave Liu
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The BCSR17[7] = 1 will unlock the write protect of FLASH.
The WP# pin only controls the write protect of top/bottom sector,
That is why we can save env, but we can't write the first sector
before the patch.Signed-off-by: Dave Liu
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The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits.
This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum
(256 MB)
which made u-boot hang in board_init_f() when trying to create a new stack
in RAM.
I have an mpc8540 with one 1GB dimm.Signed-off-by: Fredrik Arnerup
Signed-off-by: Andy Fleming
Acked-by: Kumar Gala -
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.Signed-off-by: Dave Liu
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This patch corrects the missing PLLB initialization in usb_cpu_init()
for AT91SAM9261.
Because of the missing PLLB initialization, the USB support for all
AT91SAM9261 based boards will work only if the PLLB is configured by a
precedent bootloader.Signed-off-by: Ilko Iliev
Acked-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Remy Bohmer
09 Jun, 2009
4 commits
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This patch fixes MDIO clock setup in case when OPB frequency is 100MHz.
Current code assumes that the value of sysinfo.freqOPB is 100000000
when OPB frequency is 100MHz. In reality it is 100000001. As a result
MDIO clock is set to incorrect value, larger than 2.5MHz, thus violating
the standard. This in not a problem on boards equipped with Marvell PHYs
(e.g. Canyonlands), since those PHYs support MDIO clocks up to 8.3MHz,
but can be a problem for other PHYs (e.g. Realtek ones).Signed-off-by: Felix Radensky
Signed-off-by: Ben Warren -
When PCI device use system memory, some PCI host controller should be
set physical memory address.Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Ben Warren -
eth_halt() function in the smc911x drivers used to call the
smc911x_reset() function. eth_halt() used to be called after
tftp transfers. This used to put the ethernet chip in reset
while the linux boots up resulting in the ethernet driver
not coming up. NFS boot used to fail as a result.This patch calls smc911x_shutdown() instead of smc911x_reset().
Some comments received has also been fixed.Signed-off-by: Manikandan Pillai
Signed-off-by: Ben Warren -
Some boards do not have SROM support for the DM9000 network adapter.
Instead of listing these board names in the driver code, make this
option configurable from the board config file.It also removes a build warning for the at91sam9261ek board:
'dm9000x.c:545: warning: 'read_srom_word' defined but not used'And it repaires the trizepsiv board build which was broken around the
same routinesSigned-off-by: Remy Bohmer
Signed-off-by: Ben Warren
08 Jun, 2009
2 commits
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In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer
impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0.
SICRH[TSIOB1] was erroneously being set high.U-Boot always operated this PHY interface in GMII mode. It is assumed this
was missed in the clean up by the original board porters, and copied along
to the TQM and sbc boards.Signed-off-by: Kim Phillips
Acked-by: Ira Snyder
Reviewed-by: David Hawkins
Tested-by: Paul Gortmaker
CC: Dave Liu -
If the MAX address is given by the environment, write it back to the
hardware.Signed-off-by: Daniel Mack
Cc: Sascha Hauer
Signed-off-by: Ben Warren
