Eric Lee / smarc-uboot

21 Feb, 2021

1 commit

  • c48c0a4d7   MLK-25310 imx8m: ddr: Disable CA VREF Training for LPDDR4 ... Browse Code »

    Users reported LPDDR4 MR12 value is set to 0 during PHY training,
    not the value from FSP timing structure, which cause compliance test failed.
    The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
    but not set in 1D. According to PHY training application node,
    to enable the feature both 1D and 2D need set this field to 1,
    otherwise the training result will be incorrect.
    The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
    MR12 value from message block (FSP structure). So update the LPDDR4
    scripts of all mscale to clear CATrainOpt[0].

    Signed-off-by: Ye Li
    Reviewed-by: Jacky Bai
    (cherry picked from commit 2c98fb859258478e0f8bb8df980a96edff19d359)

    Ye Li
     

06 May, 2020

1 commit

08 Oct, 2019

1 commit