Eric Lee / smarc-uboot

08 Mar, 2014

1 commit

  • 96ac18c9c   powerpc/t104xrdb: Update DDR initialization related settings ... Browse Code »

    Update following DDR related settings for T1040RDB, T1042RDB_PI
    -Correct number of chip selects to two as t1040 supports
    two Chip selects.
    -Update board_specific_parameters udimm structure with settings
    derived via calibration.
    -Update ddr_raw_timing sructure corresponding to DIMM.
    -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
    but on T104xRDB, on setting this , DDR instability is observed.
    Board-level debugging is in progress.

    Verified the updated settings to be working fine with dual-ranked
    Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.

    Signed-off-by: Priyanka Jain
    Signed-off-by: York Sun

    Priyanka Jain
     

14 Nov, 2013

1 commit

  • 062ef1a66   powerpc/t104xrdb: Add T1040RDB board support ... Browse Code »

    T1040RDB is Freescale Reference Design Board supporting
    the T1040 QorIQ Power Architecture™ processor.

    T1040RDB board Overview
    -----------------------
    - Four e5500 cores, each with a private 256 KB L2 cache
    - 256 KB shared L3 CoreNet platform cache (CPC)
    - Interconnect CoreNet platform
    - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
    support
    - Data Path Acceleration Architecture (DPAA) incorporating acceleration
    for the following functions:
    - Packet parsing, classification, and distribution
    - Queue management for scheduling, packet sequencing, and congestion
    management
    - Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
    - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
    - SERDES Connections, 8 lanes supporting:
    - PCI
    - SGMII
    - QSGMII
    - SATA 2.0
    - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
    Interleaving
    -IFC/Local Bus
    - NAND flash: 1GB 8-bit NAND flash
    - NOR: 128MB 16-bit NOR Flash
    - Ethernet
    - Two on-board RGMII 10/100/1G ethernet ports.
    - PHY #0 remains powered up during deep-sleep
    - CPLD
    - Clocks
    - System and DDR clock (SYSCLK, “DDRCLK”)
    - SERDES clocks
    - Power Supplies
    - USB
    - Supports two USB 2.0 ports with integrated PHYs
    - Two type A ports with 5V@1.5A per port.
    - SDHC
    - SDHC/SDXC connector
    - SPI
    - On-board 64MB SPI flash
    - I2C
    - Devices connected: EEPROM, thermal monitor, VID controller
    - Other IO
    - Two Serial ports
    - ProfiBus port

    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Priyanka Jain
    [York Sun: fixed Makefile]
    Acked-by: York Sun

    Priyanka Jain