14 Mar, 2019
1 commit
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Fix coverity issue: CID 1477258: Uninitialized scalar variable (UNINIT)
uninit_use_in_call: Using uninitialized value txbuf when calling __fswab32.Test: Coverity scan pass.
Change-Id: If57f70c272ef49a6636a59ae3b5dcc5430fd1753
Signed-off-by: Luo Ji
03 Nov, 2018
1 commit
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When building mxc_spi driver on ARM64 platforms like iMX8MM, get
such build warnings below. Fix it in this patch.In file included from include/common.h:48:0,
from drivers/spi/mxc_spi.c:9:
drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’:
drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
_func_, bitlen, (u32)dout, (u32)din);
^
include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
^~~~~
drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
_func_, bitlen, (u32)dout, (u32)din);
^
include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
^~~~~Signed-off-by: Ye Li
Reviewed-by: Peng Fan
29 Oct, 2018
1 commit
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In flexspi driver, each sf command will disable the module in release bus
function. So reading from flexspi memory-map address using "md" command
can't work. When iMX8MM kicks M4 image to run flexspi NOR XIP,
this causes problem.Signed-off-by: Ye Li
31 May, 2018
1 commit
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Since the fdt API is changed, update to use devfdt_get_addr.
Otherwise, build the DM SPI will fail.Signed-off-by: Ye Li
23 May, 2018
2 commits
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The address size is 3 bytes when using BAR mode, but the driver
supposes the 4bytes mode is enabled and uses 4 bytes address. This
cause address issue.Also the mask needs set to 23bits for 3 bytes address.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
(cherry picked from commit 2e9a9e0fe379306f7c1065f9afa9e67386be2503) -
If not initialize unused LUT to 0, the value is random which might
cause qspi command failure.On i.MX8QM/QXP, it works ok because ROM inittialize them to 0, but on
i.MX8MM, ROM not initialize them, so let's do it here.Signed-off-by: Peng Fan
(cherry picked from commit c4bd49c7b249073415f052fb28cd5a4ad374a318)
27 Apr, 2018
9 commits
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When the power domain driver is enabled, we need to enable clocks after power
domain on. The clock settings in board level codes must be removed, needs to
set them when the device is probed. Add this weak function in flexspi driver,
that SoC codes can implement the clock settings.Reviewed-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit a4d334e70839021a50dca2ad4ad98ecee16081f9) -
i.MX8QM ROM didn't calculate the DLL correctly in some cases, to avoid
the wrong DLL setting impact the following functions, reset them to the
default value when probe.Signed-off-by: Han Xu
(cherry picked from commit da3c2a9f09afa45a428809b7bf3f981a1ccb7f2e) -
Update the LUT settings, spi_xfer to use the 4bytes address read/write/erase
commands.
Also add a function to enter the 4bytes mode for flash device.Signed-off-by: Ye Li
(cherry picked from commit 704c1c357d5566e6b3a72c57427d90ba08f9ef0f) -
Add fsl_fspi driver for flexspi controller. This driver supports:
1. DDR Quad output
2. Prefetch function for improve read performance.
3. Fast read and Quad read for one line read mode.
4. Read flash FSR register.
5. DM.Signed-off-by: Han Xu
Signed-off-by: Ye Li
(cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa) -
The i.MX8M reuses the QSPI controller from i.MX7D. Add the CONFIG_IMX8M
define to the driver.Signed-off-by: Ye Li
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Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af) -
support to read the flag status in driver to avoid the spi-nor framework
wait_for_ready hang issue.Signed-off-by: Han Xu
(cherry picked from commit 767faa948d2d140b6d56ee505f81f8f57c045a3d) -
There are two problems in enabling DDR mode in this new driver:
1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
cause explicit problem.
2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
like DDR_EN are cleared during these operations. When we using DDR mode QSPI boot, the TDH bit
is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
So these operations will fail.
The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
after using DDR mode QSPI boot on 6UL/ULL EVK boards.Signed-off-by: Ye Li
(cherry picked from commit 16270556212e6c7422e87f69572c90f1afe6998b) -
The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.Signed-off-by: Ye Li
(cherry picked from commit 5a69ddb7e9886e082da42ddf673415702975ee60)
14 Feb, 2018
8 commits
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Signed-off-by: Tuomas Tynkkynen
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Signed-off-by: Tuomas Tynkkynen
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Signed-off-by: Tuomas Tynkkynen
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Signed-off-by: Tuomas Tynkkynen
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Signed-off-by: Tuomas Tynkkynen
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Signed-off-by: Tuomas Tynkkynen
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Signed-off-by: Tuomas Tynkkynen
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Signed-off-by: Tuomas Tynkkynen
08 Feb, 2018
1 commit
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Check if ns before and not after dereferencing it.
Indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt
26 Jan, 2018
2 commits
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Add option to set spi controller clock frequency via device tree
using standard clock bindings.Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)Reviewed-by: Marek Vasut
Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki
24 Jan, 2018
12 commits
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Make flash writes 32 bit aligned by using bounce buffers to deal with
non 32 bit aligned buffers.
This is required because as per TI K2G TRM[1], the external master is
only permitted to issue 32-bit data interface writes until the last word
of an indirect transfer. Otherwise indirect writes is known to fail
sometimes.[1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf
Signed-off-by: Vignesh R
Acked-by: Marek Vasut
Acked-by: Simon Goldschmidt
Reviewed-by: Jason Rush
Acked-by: Jason Rush
Reviewed-by: Jagan Teki -
This reverts commit 57897c13de03ac0136d64641a3eab526c6810387.
Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.Signed-off-by: Vignesh R
Acked-by: Marek Vasut
Acked-by: Simon Goldschmidt
Reviewed-by: Jason Rush
Acked-by: Jason Rush
Reviewed-by: Jagan Teki -
This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.
This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.Signed-off-by: Simon Goldschmidt
Signed-off-by: Vignesh R
Acked-by: Marek Vasut
Reviewed-by: Jason Rush
Acked-by: Jason Rush
Reviewed-by: Jagan Teki -
Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.Tested on TI K2G platform:
Tested-by: Vignesh RTested on a socfpga-cyclonev board:
Tested-by: Simon GoldschmidtSigned-off-by: Jason Rush
Reviewed-by: Jagan Teki
Acked-by: Simon Goldschmidt
Acked-by: Marek Vasut -
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz. However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Reviewed-by: Jagan Teki -
Remove a superfluous newline, and reduce the scope of a variable.
Reviewed-by: Simon Glass
Reviewed-by: Jagan Teki
Signed-off-by: Mario Six -
A previous patch removed the spi_flash_probe_fdt function, which
contained the last call of the spi_setup_slave_fdt function, which is
now equally obsolete.This patch removes the function.
Reviewed-by: Simon Glass
Reviewed-by: Jagan Teki
Signed-off-by: Mario Six -
0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT
node") added a helper function spi_base_setup_slave_fdt to to set up a
SPI slave from a given FDT blob. The only user was the exynos SPI
driver.But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed
the use of this function, hence rendering it obsolete.Remove this function, as well as the CONFIG_OF_SPI option, which guarded
only this function.Reviewed-by: Simon Glass
Reviewed-by: Jagan Teki
Signed-off-by: Mario Six -
This patch fixes a printf specifier style violation, reduces the scope
of a variable, and turns a void pointer that is used with pointer
arithmetic into a u8 pointer.Signed-off-by: Mario Six
Reviewed-by: Jagan Teki -
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Jagan Teki -
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Jagan Teki -
wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Jagan Teki
23 Jan, 2018
1 commit
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This converts the following to Kconfig:
CONFIG_DAVINCI_SPISigned-off-by: Adam Ford
12 Jan, 2018
1 commit
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The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.Add the compatible entry for 6ul/7d.
Signed-off-by: Peng Fan