26 Mar, 2017
2 commits
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Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance testSigned-off-by: Ken Lin
Reviewed-by: Stefano Babic
Acked-by: Ian Ray -
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin
Reviewed-by: Stefano Babic
Acked-by: Ian Ray
29 Nov, 2016
1 commit
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Change the PMIC bulk configuration from auto mode to sync mode to avoid
voltage dropout issue seen in auto mode.Signed-off-by: Ken Lin
Signed-off-by: Akshay Bhat
24 Sep, 2016
1 commit
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Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap )Replace all include directives for with .
Signed-off-by: Masahiro Yamada
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini
28 Jul, 2016
1 commit
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imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Martin Donnelly
Signed-off-by: Fabio Estevam
08 Jun, 2016
1 commit
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Don't try to configure the backlight when CONFIG_VIDEO_IPUV3 isn't set.
Signed-off-by: Andrew Shadura
19 Apr, 2016
5 commits
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On a reset/reboot, the display power needs to be off for atleast 500ms
before turning it back on. So add a delay to the boot process to meet
the display timing requirement.Signed-off-by: Akshay Bhat
Cc: Stefano Babic -
Setup the LCD backlight brightness control pin to use PWM
Signed-off-by: Akshay Bhat
Cc: Stefano Babic -
To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.Signed-off-by: Akshay Bhat
Cc: Stefano Babic -
B450v3/B650v3 uses single channel LVDS and does not support HDMI.
B850v3 uses dual channel LVDS and supports HDMI. Hence split the display
setup into two different functions.Signed-off-by: Akshay Bhat
Cc: Stefano Babic -
Certain pins are not used on the i.MX6, and should have a neutral
pad configuration in order to reduce electrical interference on
the board. This commit defines these pins with a default value
rather than relying on the system defaults.Signed-off-by: Justin Waters
Signed-off-by: Akshay Bhat
Cc: Stefano Babic
09 Mar, 2016
1 commit
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Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI displayBasic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2Signed-off-by: Akshay Bhat
Reviewed-by: Peng Fan