Eric Lee / smarc-uboot

21 Feb, 2014

1 commit

20 Feb, 2014

1 commit

19 Feb, 2014

4 commits

  • bb7cd0ddf   spi: ti_qspi: Add delay before xfer for am43xx ... Browse Code »

    Without this delay, write/read is failing.
    Looks like, the WIP always remain set and hence a timeout
    occurs leading to the error.

    Without this patch, device does not get probed also.
    Here is the log.

    U-Boot#
    U-Boot#
    U-Boot#
    U-Boot# sf probe 0
    SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
    Failed to initialize SPI flash at 0:0
    U-Boot# sf probe 0

    While with this patch, log is
    U-Boot# sf probe 0
    SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
    U-Boot# sf erase 0 0x80000
    SF: 524288 bytes @ 0x0 Erased: OK
    U-Boot# mw 81000000 0xdededede 0x40000
    U-Boot# sf write 81000000 0 0x40000
    SF: 262144 bytes @ 0x0 Written: OK
    U-Boot# sf read 82000000 0 0x40000
    SF: 262144 bytes @ 0x0 Read: OK
    U-Boot# md 0x82000000

    Signed-off-by: Sourav Poddar
    Reviewed-by: Jagannadha Sutradharudu Teki

    Sourav Poddar
     
  • 570533b82   spi: ti_qspi: Add AM43xx specifics changes ... Browse Code »

    Add AM43xx specific changes.

    Signed-off-by: Sourav Poddar
    Reviewed-by: Jagannadha Sutradharudu Teki

    Sourav Poddar
     
  • 5d584ccec   spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3 ... Browse Code »

    SPI_MODE_3 requires clk high when inactive. The SCLK_CTL
    field of the config reg was not configured in case of CPOL.
    Fix configuration so that SPI_MODE_3 which uses CPOL configures
    the clk line to be high in inactive state.

    Signed-off-by: Markus Niebel
    Reviewed-by: Jagannadha Sutradharudu Teki

    Markus Niebel
     
  • 999c39a45   spi: xilinx: Move timeout calculation out of the loop ... Browse Code »

    Timeout calculation should be out of the data loop.
    This patch increase spi bandwidth for 30%.

    Signed-off-by: Michal Simek
    Reviewed-by: Jagannadha Sutradharudu Teki

    Michal Simek
     

17 Jan, 2014

1 commit

16 Jan, 2014

1 commit

11 Jan, 2014

2 commits

  • 12f00caf6   spi: sh_spi: Use sh_spi_clear_bit() instead of open-coded ... Browse Code »

    We have a sh_spi_clear_bit() function, there's no reason not to use it.

    Signed-off-by: Axel Lin
    Acked-by: Nobuhiro Iwamatsu
    Reviewed-by: Jagannadha Sutradharudu Teki

    Axel Lin
     
  • 66cb9eb1d   spi: Add Faraday SPI controller support ... Browse Code »

    The Faraday FTSSP010 is a multi-function controller
    which supports I2S/SPI/SSP/AC97/SPDIF. However This
    patch implements only the SPI mode.

    NOTE:
    The DMA and CS/Clock control logic has been altered
    since hardware revision 1.19.0. So this patch
    would first detects the revision id of the underlying
    chip, and then switch to the corresponding software
    control routines.

    Signed-off-by: Kuo-Jung Su
    Signed-off-by: Jagannadha Sutradharudu Teki
    CC: Tom Rini

    Kuo-Jung Su
     

19 Dec, 2013

2 commits

  • 60acde43d   spi: tegra: clear RDY bit prior to every transfer ... Browse Code »

    The RDY bit indicates that a transfer is complete. This needs to be
    cleared by SW before every single HW transaction, rather than only
    at the start of each SW transaction (those being made up of n HW
    transactions).

    It seems that earlier HW may have cleared this bit autonomously when
    starting a new transfer, and hence this code was not needed in practice.
    However, this is generally a good idea in all cases. In Tegra124, the
    HW behaviour appears to have changed, and SW must explicitly clear this
    bit. Otherwise, SW will believe that transfers have completed when they
    have not, and may e.g. read stale data from the RX FIFO.

    Signed-off-by: Yen Lin
    [swarren, rewrote commit description, unified duplicate RDY clearing code
    and moved it right before the start of the HW transaction, unconditionally
    exit loop after reading RX data, rather than checking if TX FIFO is empty,
    since it is guaranteed to be]
    Signed-off-by: Stephen Warren
    Reviewed-by: Jagannadha Sutradharudu Teki

    Yen Lin
     
  • 16f47c9c5   spi: Add support SH Quad SPI driver ... Browse Code »

    This patch adds a driver for Renesas SoC's Quad SPI bus.
    This supports with 8 bits per transfer to use with SPI flash.

    Signed-off-by: Kouei Abe
    Signed-off-by: Nobuhiro Iwamatsu
    Signed-off-by: Jagannadha Sutradharudu Teki

    Nobuhiro Iwamatsu
     

10 Dec, 2013

3 commits

06 Dec, 2013

2 commits

  • 9bac8f776   spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus] ... Browse Code »

    For invalid bus number, current code returns NULL in the default case of
    switch-case statements. In additional, pins[bus] is always not NULL because
    it is the address of specific row of the two-dimensional array.
    Thus this patch removes these unnecessary test.

    Signed-off-by: Axel Lin
    Acked-by: Scott Jiang
    Signed-off-by: Sonic Zhang

    Axel Lin
     
  • 727cbe14b   spi: bfin_spi: Remove unnecessary test for bus and pins[bus] ... Browse Code »

    For invalid bus number, current code returns NULL in the default case of
    switch-case statements. In additional, pins[bus] is always not NULL because
    it is the address of specific row of the two-dimensional array.
    Thus this patch removes these unnecessary test.

    Signed-off-by: Axel Lin
    Acked-by: Scott Jiang
    Signed-off-by: Sonic Zhang

    Axel Lin
     

12 Nov, 2013

2 commits

  • 5753d09b1   spi: omap3: add support for more word lengths ... Browse Code »

    Current implementation only supports 8 bit word lengths, even though
    omap3 can handle anything between 4 and 32.

    Update the spi interface to support changing the SPI word length,
    and implement it in omap3_spi driver to support the full range of
    possible word lengths.
    This implementation is backwards compatible by defaulting to the old
    behavior of 8 bit word lengths.
    Also, it required a change to the omap3_spi non static I/O functions,
    but since they are not used anywhere else, no collateral changes are required.

    Cc: Tom Rini
    Cc: Jagannadha Sutradharudu Teki
    Cc: Igor Grinberg
    Signed-off-by: Nikita Kiryanov

    Nikita Kiryanov
     
  • 54a759c88   spi: omap3: remove semicolon from #define ... Browse Code »

    Remove unnecessary semicolon from #define SPI_WAIT_TIMEOUT

    Cc: Tom Rini
    Cc: Jagannadha Sutradharudu Teki
    Cc: Igor Grinberg
    Cc: Gerhard Sittig
    Signed-off-by: Nikita Kiryanov

    Nikita Kiryanov
     

01 Nov, 2013

1 commit

16 Oct, 2013

2 commits

15 Oct, 2013

2 commits

08 Oct, 2013

3 commits

  • c4a796329   spi: exynos: Support word transfers ... Browse Code »

    Since SPI register access is so expensive, it is worth transferring data
    a word at a time if we can. This complicates the driver unfortunately.

    Use the byte-swapping feature to avoid having to convert to/from big
    endian in software.

    This change increases speed from about 2MB/s to about 4.5MB/s.

    Signed-off-by: Simon Glass
    Signed-off-by: Rajeshwari S Shinde
    Reviewed-by: Jagannadha Sutradharudu Teki

    Rajeshwari Shinde
     
  • 120af1572   spi: exynos: Minimise access to SPI FIFO level ... Browse Code »

    Accessing SPI registers is slow, but access to the FIFO level register
    in particular seems to be extraordinarily expensive (I measure up to
    600ns). Perhaps it is required to synchronise with the SPI byte output
    logic which might run at 1/8th of the 40MHz SPI speed (just a guess).

    Reduce access to this register by filling up and emptying FIFOs
    more completely, rather than just one word each time around the inner
    loop.

    Since the rxfifo value will now likely be much greater that what we read
    before we fill the txfifo, we only fill the txfifo halfway. This is
    because if the txfifo is empty, but the rxfifo has data in it, then writing
    too much data to the txfifo may overflow the rxfifo as data arrives.

    This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.

    Signed-off-by: Simon Glass
    Signed-off-by: Rajeshwari S Shinde
    Reviewed-by: Jagannadha Sutradharudu Teki

    Rajeshwari Shinde
     
  • 8d203afdd   spi: exynos: Support a delay after deactivate ... Browse Code »

    For devices that need some time to react after a spi transaction
    finishes, add the ability to set a delay.

    Implement this as a delay on the first/next transaction to avoid
    any delay in the fairly common case where a SPI transaction is
    followed by other processing.

    Signed-off-by: Simon Glass
    Signed-off-by: Rajeshwari S Shinde
    Reviewed-by: Jagannadha Sutradharudu Teki

    Rajeshwari Shinde
     

07 Oct, 2013

1 commit

  • 1d0933eaf   spi: add TI QSPI driver ... Browse Code »

    Adds a SPI master driver for the TI QSPI peripheral.
    - Added quad read support.
    - Added memory mapped support.

    Signed-off-by: Matt Porter
    Signed-off-by: Sourav Poddar
    Signed-off-by: Jagannadha Sutradharudu Teki

    Matt Porter
     

27 Aug, 2013

1 commit

21 Aug, 2013

1 commit

  • 997399fa4   powerpc: Fix CamelCase checkpatch warnings ... Browse Code »

    85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
    because of this code checkpatch script generates "WARNING: Avoid CamelCase".

    Convert variables name to normal naming convention and modify board, driver
    files with updated the new structure.

    Signed-off-by: Prabhakar Kushwaha
    Acked-by: York Sun

    Prabhakar Kushwaha
     

07 Aug, 2013

3 commits

31 Jul, 2013

1 commit

24 Jul, 2013

1 commit

12 Jul, 2013

1 commit

28 Jun, 2013

1 commit

26 Jun, 2013

3 commits

  • 9a30903b4   spi: mxc_spi: Update pre and post divider algorithm ... Browse Code »

    The spi clock divisor is of the form x * (2**y), or x << y, where x is
    1 to 16, and y is 0 to 15. Note the similarity with floating point numbers.
    Convert the desired divisor to the smallest number which is >= desired divisor,
    and can be represented in this form. The previous algorithm chose a divisor
    which could be almost twice as large as needed.

    Signed-off-by: Troy Kisky
    Signed-off-by: Dirk Behme

    Dirk Behme
     
  • 8d4c4ffb9   spi: mxc_spi: Fix pre and post divider calculation ... Browse Code »

    Fix two issues with the calculation of pre_div and post_div:

    1. pre_div: While the calculation of pre_div looks correct, to set the
    CONREG[15-12] bits pre_div needs to be decremented by 1:

    The i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM
    Rev. 0, 11/2012) states:

    CONREG[15-12]: PRE_DIVIDER
    0000 Divide by 1
    0001 Divide by 2
    0010 Divide by 3
    ...
    1101 Divide by 14
    1110 Divide by 15
    1111 Divide by 16

    I.e. if we want to divide by 2, we have to write 1 to CONREG[15-12].

    2. In case the post divider becomes necessary, pre_div will be divided by
    16. So set pre_div to 16, too. And not 15.

    Both issues above are tested using the following examples:

    clk_src = 60000000 (60MHz, default i.MX6 ECSPI clock)

    a) max_hz == 23000000 (23MHz, max i.MX6 ECSPI read clock)

    -> pre_div = 3 (divide by 3 => CONREG[15-12] == 2)
    -> post_div = 0 (divide by 1 => CONREG[11- 8] == 0)
    => 60MHz / 3 = 20MHz SPI clock

    b) max_hz == 2000000 (2MHz)

    -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15)
    -> post_div = 1 (divide by 2 => CONREG[11- 8] == 1)
    => 60MHz / 32 = 1.875MHz SPI clock

    c) max_hz == 1000000 (1MHz)

    -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15)
    -> post_div = 2 (divide by 4 => CONREG[11- 8] == 2)
    => 60MHz / 64 = 937.5kHz SPI clock

    d) max_hz == 500000 (500kHz)

    -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15)
    -> post_div = 3 (divide by 8 => CONREG[11- 8] == 3)
    => 60MHz / 128 = 468.75kHz SPI clock

    Signed-off-by: Dirk Behme

    Dirk Behme
     
  • f3424c554   cros: exynos: add SPI support for cros_ec ... Browse Code »

    This patch adds SPI support for carrying out the cros_ec protocol.

    Signed-off-by: Hung-ying Tyan
    Signed-off-by: Randall Spangler
    Signed-off-by: Simon Glass
    Acked-by: Simon Glass

    Hung-ying Tyan