14 Jan, 2015

1 commit


08 Jul, 2014

1 commit


20 Jun, 2014

1 commit


19 Dec, 2013

2 commits

  • Updating the Multiplier and Dividers value for all DPLLs.
    Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
    returned the MPU DPLL is locked.
    At different OPPs follwoing are the MPU locked frequencies.
    OPP50 300MHz
    OPP100 600MHz
    OPP120 720MHz
    OPPTB 800MHz
    OPPNT 1000MHz
    According to the latest DM following is the OPP table dependencies:
    VDD_CORE VDD_MPU
    OPP50 OPP50
    OPP50 OPP100
    OPP100 OPP50
    OPP100 OPP100
    OPP100 OPP120
    So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
    Following are the DPLL locking frequencies at OPP NOM:
    Core locks at 1000MHz
    Per locks at 960MHz
    LPDDR2 locks at 266MHz
    DDR3 locks at 400MHz

    Touching AM33xx files also to get DPLL values specific to board but no
    functionality difference.
    Signed-off-by: Lokesh Vutla

    Lokesh Vutla
     
  • Add support for reading onboard EEPROM to enable
    board detection.

    Signed-off-by: Sekhar Nori
    Signed-off-by: Lokesh Vutla

    Sekhar Nori
     

15 Aug, 2013

1 commit