06 May, 2020
40 commits
-
Update SECO event example description to clarify the
error reported.Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit 1018252a576697e8f80ab78a1dcb15f1866e1fb8) -
v5.4 kernel has removed the "fsl-" prefix from DTB. Update the kernel DTB
names for imx8 and imx8m platforms.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit d6a88a98716d4efc59140a1544dbcdf22f07784a) -
iMX8DX MEK board has similar design with 8QXP MEK. The major changes are
1. DDR changed to 16bits 1GB DDR part
2. USB3.0 is removed and only support OTG on typec port. (No SW change needed)This patch adds new defconfigs and DTS file for this new board.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8185fa9fa8e48d64d4abf8066bf080f02343d484) -
i.MX8MP speed grade use same layout as i.MX8MN, so reuse it for i.MX8MP
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
(cherry picked from commit 6e4f8d87652ac949de9a668e94c3ff27b48ca6b9) -
Need to enable read urgent for NoC panic signal
Signed-off-by: Jian Li <jian.li@nxp.com
(cherry picked from commit d966293a2e566a0116b0660c9c6c416951d35c83) -
Change the SPL to non-DM and enable USB/tcpc, TMU, flexspi, FEC
and eQOS.Signed-off-by: Ye Li
-
Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocksSigned-off-by: Ye Li
-
Update DTS files to support FEC, eQoS, DWC3 USB and flexspi
1. Update nodes and assigned clocks for flexspi, FEC, eQos
2. Add nodes for DWC3 USB
3. Add i2c force idle
4. Add thermal nodesSigned-off-by: Ye Li
-
There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq,
then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM.Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus
clocks to OD frequency before it increases ARM voltage. So to conform to the
limitation, we'd better increases VDD_ARM to OD voltage in SPL.Signed-off-by: Ye Li
Reviewed-by: Anson Huang
(cherry picked from commit f9fdb7a6134d8929c2291303c006f7380d97faa8) -
when boot from A72, use fastboot to download images, the first usb
request buf to save image data may have problem with the cache, which
cause the last 64bytes of this packet to be wrong.flush this cache before data movement to avoid this issue.
Change-Id: Ic0927f1ec90ec9fb4cecdf4055bc7f536ef5471a
Signed-off-by: faqiang.zhu
(cherry picked from commit 45119132756b951c6f52e27625c06f94e4f0db59) -
iMX8MP supports two ENET controllers, have to update the function to
enable loading two MAC addresses.Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
(cherry picked from commit 61aebe41d5ba5f569cea233dec09da04539179bb) -
Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
(cherry picked from commit d00d6d0a22ba734f76444621a17f985ffba50705) -
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
(cherry picked from commit e442274ddd2cb6e9c4103e91cd284bfb01a4a636) -
So far u-boot only load SNSR25C for TMU main probe (probe 0). However,
kernel enables two probes. So it also needs to set default SNSR25C of
TCALIV1 for blank samples.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit f82edefd94c9f9922296c3133abf688aced55f14) -
Update TMU driver for imx8mp thermal which has two probes and supports
temperature range from -40 to 125. The driver still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.Reviewed-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit 2deda4eb4f5bc0b749e5cef1395a0b436448d4fa) -
Implement the callbacks to get phy mode interface and txclk
rate configuration.Reviewed-by: Ye Li
Signed-off-by: Fugang Duan
(cherry picked from commit ad2f34236694493b94c2cf6801eef4b7212eb89b) -
Add dwc eqos for imx support.
Reviewed-by: Ye Li
Signed-off-by: Fugang Duan
(cherry picked from commit 52751a41c92a719891c8154cfc488165cc42f713) -
Add RX delay enable support for RTL8211F PHY.
Reviewed-by: Ye Li
Signed-off-by: Fugang Duan
(cherry picked from commit 8e55d1e0bea57c0671a51258c48306be0066ae7c) -
Update PHY settings to select 24M ref clock and enable clock in
HSIOMIX GPR.Reviewed-by: Jun Li
Signed-off-by: Ye Li
(cherry picked from commit aa0f45fed58f891e246e6ec743a7de71eb69c911) -
to enable it, in uuu script add below command
fb: ucmd setenv stdout serial,fastboot
uuu add -v opition.
output will show in uuu consoleSigned-off-by: Frank Li
(cherry picked from commit a5e86802515221cdfa4b6d82e697cf9dc0d29a98) -
When we create software partition, we still need let parent
partition to configure sid, so move the check after sid failed.Acked-by: Ye Li
Signed-off-by: Peng Fan
(cherry picked from commit 501e11247c3a8ed8c142e6c4f4a5aca5fb608195) -
When doing reset_cpu, in normal case the WDOG_B outputs immediately
after we clean WDA bit. But on mscale, the WDOG_B may be later than
internal reset, and cause PMIC not reset. As we enabled the SD3.0
support, the PMIC must be reset to reset SD card.Change the reset_cpu to enable the WDOG_B for timeout as well, and set
WDOG timeout to 1s.Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit e78f889637636d8b67fe6250623f3473514f1a23)
(cherry picked from commit 7c3fbe91ac2bbd3041bc4d27456d8ac2bbffbb8d) -
Remove both configs to save SPL size, since we have decoupled the
CI_UDC with EHCI driverSigned-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 2b72e174551cbc25ad0d9d90136bfcb95c851951) -
On 2019.04 SPL, we enabled DM gadget driver for QM/QXP to support
dual USB ports. The CI_UDC DM gadget driver will call init function
inside EHCI mx6 driver, so when building SPL on iMX8QM/QXP with CI UDC
enabled, we have to enable usb host driver as well, and this introduces
about more than 40KB size to SPL.Move the common codes to a independent file, so that both host driver
and gadget driver can call it, then decouple the host and gadget driver.Note: the patch only applies to ci_udc gadget DM driver. For non-DM gadget
driver, it still depends ehci host interfaces.Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 1afed171a77b4c95cd4ea76f29d5a0a6bb199820) -
Add AHAB encrypted boot documentation for i.MX8/8x family devices
covering the following topics:- How to encrypt and sign the 2nd container in flash.bin image.
- How to encrypt and sign a standalone container image.Include a CSF example to encrypt 2nd container in flash.bin image.
Signed-off-by: Catia Han
Signed-off-by: Breno Lima
(cherry picked from commit dc18ee2c6c06ab9364dc08c70830acc8c6dcceac) -
Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.The module also adds some commands:
- snvs_cfg: Configure the SNVS HP and LP registers
- snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
- tamper_pin_cfg: Change the configuration of the tamper pins
- snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bitsSigned-off-by: Franck LENORMAND
(cherry picked from commit 75aa7f2254f0883aa14568ac32702b1ca15367e4)
Signed-off-by: Ye Li
(cherry picked from commit 2f3804bdfe29a3c134a1753d6fa92881ea3e2b30) -
add support for imx8qxp to read boot search count from fuse in nandbcb
Signed-off-by: Han Xu
(cherry picked from commit b69aec21178ee2e81955dfd7e32b2792d0446c2e) -
On i.MX8MN, we can only support DLL-ON mode only, so update the timing
to support 2400mts & 1066mts setpoint.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
(cherry picked from commit c8347f8eb51e4a603ed5f1649129dd3a0a8ea9f9)
(cherry picked from commit 1466b915bb7df3942b4aa67ff9518a3dd461bf9c) -
Add the nandfit_part environment to notify uuu to burn flash.bin to
nandfit partition for iMX8QM/QX/MQ/MM platformsSigned-off-by: Han Xu
(cherry picked from commit 79474268a4d7ec473435181b85176b266549f278)
Signed-off-by: Clement Faure
Reviewed-by: Ye Li -
Enable CONFIG_CMD_USB_MASS_STORAGE by default to enable UMS flashing.
Signed-off-by: Clement Faure
Acked-by: Ye Li
(cherry picked from commit 52fddd71c5fc2bf10d9e551197f90cf4096fbc71) -
add the mtdparts config for iMX6ULL
Signed-off-by: Han Xu
(cherry picked from commit 66430af4cee0e18a211244114ca4648342c7d995) -
Add more BCH setting mode and remove the unnecessary platform constrain
Signed-off-by: Han Xu
(cherry picked from commit eb97412a839ce7a27267beee2dc0ab264d7fa131) -
Add the ARCH_MX8 in Kconfig for supporting iMX8QX in nandbcb
Signed-off-by: Han Xu
(cherry picked from commit a91c8b42b6d8385bbd09652a5e18e3c2286eb305) -
The original nandbcb tool was designed for imx6 only, when trying to
leverage it to replace the kobs-ng tool, we found the design is not
friendly for supporting all platforms. To support all iMX6/7/8 platforms
and for easy further maintain, I reconstruct the structure of the tool.The main changes including:
1. Use platform_data to determine the logic branches rather than simply use SOC name.
2. More data structures as parameter for functions.
3. Global variables to define the FCB/DBBT/FW locations.
4. Implement the kobs-ng default 4 FCB/4 DBBT/2 FW layout.
5. Support Hamming coding/ 40bit BCH/ 62bit BCH coding FCB.
6. Dump and compare all written FCB/DBBT to verify data integrity.The tool has been verified on iMX6Q/DL, 6SX, 7D, 6ULL, iMX8QX, iMX8MM.
Signed-off-by: Han Xu
(cherry picked from commit b41b3812f19716cdd479805d879d9236b02a666b) -
The signature is generated using manufacturing protection private key.
Fix typo in fsl_mfgprot.c.
Signed-off-by: Breno Lima
(cherry picked from commit a14286a86fd73b6dcd2d15c3051c17653922a50f) -
i.MX8/8x devices support CAAM manufacturing protection through SECO
APIs, SECO FW generates P-384 private key in every OEM closed boot.Add support for SECO enabled devices in mfgprot U-Boot command, the
following commands are available:=> mfgprot pubk
=> mfgprot signSigned-off-by: Breno Lima
(cherry picked from commit 1fdb9726fdc4642d0f24104ec2e4099d59569468) -
SECO provides APIs to support CAAM manufacturing protection:
- sc_seco_get_mp_key()
- sc_seco_get_mp_sign()
- sc_seco_update_mpmr()Add SCFW APIs support.
Signed-off-by: Breno Lima
(cherry picked from commit 18def97fc07fec226f2e1342f2008bf449c453c2) -
- Advantage of park mode
When only a single Async endpoint is active.- Behavior of park mode
1. The controller prefetches data/TRBs to do 3 * burst_size worth
of packets.
2. When park mode is disabled there will be some delay between
bursts on the USB. This can be avoided if park mode is enabled
in cases of only one endpoint is active.
3. But this delay is significant only with systems of large
latencies.
4. We have noticed that in cases where a device NAKs often, it
tends to bring down the performance for a single endpoint case.- Issue on "park mode"
1. LSP (List Processor) goes in and out of park mode irrespective
of the fact that there are more endpoints active. #LSP consider
that there is only one endpoint active.
2. This causes master scheduler and transaction handlers to think
that they are in park mode even though they are not. This is
because request to transaction handlers, generated by HSCH is
in park mode when the request is made
3. This causes a case where the master scheduler calculates wrongly
the number of TRB cache space available.
4. Because of the wrongly calculated number of TRB spaces, the core
fetches more TRBS than there is space for.
5. This causes overwriting the TRB cache area into the TRQ cache
area which is next to the TRB cache area.
6. This causes invalidating an entry in the TRQ
7. This causes transaction handlers to ignore a request in the TRQ
which it should have processed.
8. This causes the main scheduler to hang because it is waiting for
status from transaction handler.
9. This causes host controller to hang.- Work Around
Disabling park mode for super speed by setting GUCTL1[17] to be 1.The STAR number is 9001415732, which is target to be released around
May,2020.Reviewed-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit 191211adfc8a797875079c228a10269c5b0d7e13) -
Optee has 4MB shared memory at its top space which was assigned to
non-secure OS partition in ATF. By default this memory is added to
u-boot DDR banks and will pass to kernel. This means kernel has possibility
to allocate from this memory for system usage. At same time this memory is
used by optee and mem-remapped by optee kernel driver. So it is possible to
have conflict and cause kernel crash.Fix the issue by removing the shared memory from u-boot DDR banks. Then it
is not visible for both u-boot and kernel and can avoid such issue.Signed-off-by: Ye Li
Reviewed-by: Anson Huang
(cherry picked from commit 164279c42de0d058b7abe198cc154ee683087e6a) -
Both imx8mn/imx8mm EVK boards have eMMC 5.1 chip and support SD3.0
So we enable the HS400ES and UHS configs to enhance eMMC/SD accessSigned-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit cf83fe7dcfcb14dd633ad43ef387793a863e111a)
