12 Jan, 2018

5 commits

• f94c44e51   riscv: Add Kconfig to support RISC-V ... Browse Code »

  Add Kconfig and makefile for RISC-V
  Also modify MAINTAINERS for it.

  Signed-off-by: Rick Chen
  Signed-off-by: Rick Chen
  Signed-off-by: Greentime Hu
  Cc: Padmarao Begari

  Rick Chen

  2018-01-12 21:05:12 +0800  
• 6020faf62   riscv: nx25: include: Add header files to support RISC-V ... Browse Code »

  Add header files for RISC-V.
  Cache, ptregs, data type and other definitions are included.

  Signed-off-by: Rick Chen
  Signed-off-by: Rick Chen
  Signed-off-by: Greentime Hu

  Rick Chen

  2018-01-12 21:05:12 +0800  
• 039ed7c57   riscv: nx25: dts: Add AE250 dts to support RISC-V ... Browse Code »

  AE250 is the Soc using NX25 cpu core base on RISC-V arch.
  Details please see the doc/README.ae250.

  Signed-off-by: Rick Chen
  Signed-off-by: Rick Chen
  Signed-off-by: Greentime Hu

  Rick Chen

  2018-01-12 21:05:12 +0800  
• 8bbb2909c   riscv: nx25: lib: Add relative lib funcs to support RISC-V ... Browse Code »

  Add makefile, interrupts.c and boot.c,... functions
  to support RISC-V arch.

  Signed-off-by: Rick Chen
  Signed-off-by: Rick Chen
  Signed-off-by: Greentime Hu
  Cc: Padmarao Begari

  Rick Chen

  2018-01-12 21:05:12 +0800  
• e8e39597a   riscv: cpu: Add nx25 to support RISC-V ... Browse Code »

  Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

  Verifications:
  1. startup and relocation ok.
  2. boot from rom or ram both ok.
  2. timer driver ok.
  3. uart driver ok
  4. mmc driver ok
  5. spi driver ok.
  6. 32/64 bit both ok.

  Detail verification message please see doc/README.ae250.

  Signed-off-by: Rick Chen
  Signed-off-by: Rick Chen
  Signed-off-by: Greentime Hu
  Cc: Padmarao Begari

  Rick Chen

  2018-01-12 21:05:12 +0800