13 Jan, 2014

1 commit

  • Since hardware revision 1.11.0, the following interrupt status
    registers are now W1C (i.e., write 1 clear):

    1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5)
    2. Interrupt Source Group 2 Register (0x14C) (All bits)

    And before revision 1.11.0, these registers are all R/W.
    Which means software must write a 0 to clear the status.

    Signed-off-by: Kuo-Jung Su
    CC: Marek Vasut

    Kuo-Jung Su
     

24 Jul, 2013

1 commit


13 Jun, 2013

1 commit