06 Feb, 2016
1 commit
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Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).Signed-off-by: Bin Meng
Reviewed-by: Heiko Schocher
Reviewed-by: Simon Glass
Reviewed-by: Minkyu Kang
29 Jul, 2015
1 commit
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The board manual desribes ON as boolean 1 and OFF as boolean 0.
Updating README with correct boolean values.Signed-off-by: Raghav Dogra
Reviewed-by: York Sun
23 Apr, 2014
1 commit
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Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordinglySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
04 Feb, 2014
1 commit
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Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.Update rootfs start address to reflect correct memory map.
Also fix minor typo in README
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
22 Jan, 2014
1 commit
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u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.So, Increase the u-boot binary size to 768KB.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
15 Oct, 2013
1 commit
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Signed-off-by: Wolfgang Denk
25 May, 2013
1 commit
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Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: Stephen George
Signed-off-by: Andy Fleming
31 Jan, 2013
1 commit
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B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
configuration reset source. The RCW source is set by appropriate
DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
- total four refclk, including CPRI clock schemeSigned-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Shaveta Leekha
Signed-off-by: Priyanka Jain
Signed-off-by: Poonam Aggrwal
Signed-off-by: Roy Zang
Signed-off-by: Sandeep Singh
Signed-off-by: Andy Fleming
