Eric Lee / smarc-uboot

08 Feb, 2018

1 commit

21 Oct, 2017

1 commit

  • 0a9ef4515   Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to Kconfig ... Browse Code »

    This converts the following to Kconfig:
    CONFIG_NAND_MXC
    CONFIG_NAND_OMAP_GPMC
    CONFIG_NAND_OMAP_GPMC_PREFETCH
    CONFIG_NAND_OMAP_ELM
    CONFIG_SPL_NAND_AM33XX_BCH
    CONFIG_SPL_NAND_SIMPLE
    CONFIG_SYS_NAND_BUSWIDTH_16BIT

    Signed-off-by: Adam Ford
    Reviewed-by: Heiko Schocher
    [trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
    add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
    Signed-off-by: Tom Rini

    Adam Ford
     

13 Sep, 2017

1 commit

13 Aug, 2017

1 commit

10 May, 2017

1 commit

10 Mar, 2017

1 commit

  • 8dda2e2f9   ARM: Migrate errata to Kconfig ... Browse Code »

    This moves all of the current ARM errata from various header files and in to
    Kconfig. This allows for a minor amount of cleanup as we had some instances
    where both a general common header file was enabling errata as well as the
    board config. We now just select these once at the higher level in Kconfig

    Signed-off-by: Tom Rini

    Tom Rini
     

22 Nov, 2016

1 commit

  • 983e37007   arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms ... Browse Code »
    29

    This moves what was in arch/arm/cpu/armv7/omap-common in to
    arch/arm/mach-omap2 and moves
    arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
    as subdirectories. All refernces to the former locations are updated to
    the current locations. For the logic to decide what our outputs are,
    consolidate the tests into a single config.mk rather than including 4.

    Signed-off-by: Tom Rini

    Tom Rini
     

17 Sep, 2016

1 commit

07 Sep, 2016

1 commit

  • fa2f81b06   TI: Rework SRAM definitions and maximums ... Browse Code »

    On all TI platforms the ROM defines a "downloaded image" area at or near
    the start of SRAM which is followed by a reserved area. As it is at
    best bad form and at worst possibly harmful in corner cases to write in
    this reserved area, we stop doing that by adding in the define
    NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
    area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
    At current we define the end of scratch space at 0x228 bytes past the
    start of scratch space this this gives us a lot of room to grow. As
    these scratch uses are non-optional today, all targets are modified to
    respect this boundary.

    Tested on OMAP4 Pandaboard, OMAP3 Beagle xM

    Cc: Albert Aribaud
    Cc: Nagendra T S
    Cc: Vaibhav Hiremath
    Cc: Lokesh Vutla
    Cc: Felipe Balbi
    Cc: Igor Grinberg
    Cc: Nikita Kiryanov
    Cc: Paul Kocialkowski
    Cc: Enric Balletbo i Serra
    Cc: Adam Ford
    Cc: Steve Sakoman
    Cc: Stefan Roese
    Cc: Thomas Weber
    Cc: Hannes Schmelzer
    Cc: Thomas Chou
    Cc: Masahiro Yamada
    Cc: Simon Glass
    Cc: Joe Hershberger
    Cc: Sam Protsenko
    Cc: Heiko Schocher
    Cc: Samuel Egli
    Cc: Michal Simek
    Cc: Wolfgang Denk
    Cc: Mateusz Kulikowski
    Cc: Ben Whitten
    Cc: Stefano Babic
    Cc: Bin Meng
    Cc: Sekhar Nori
    Cc: Mugunthan V N
    Cc: "B, Ravi"
    Cc: "Matwey V. Kornilov"
    Cc: Ladislav Michl
    Cc: Ash Charles
    Cc: "Kipisz, Steven"
    Cc: Daniel Allred
    Signed-off-by: Tom Rini
    Tested-by: Lokesh Vutla
    Acked-by: Lokesh Vutla
    Tested-by: Ladislav Michl

    Tom Rini
     

27 Aug, 2016

1 commit

  • 067716bac   ARM: Move SYS_CACHELINE_SIZE over to Kconfig ... Browse Code »

    This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
    cases we are mirroring the values used by the Linux Kernel here. Also,
    so long as (and in this case, it is true) we implement flushes in hunks
    that are no larger than the smallest implementation (and given that we
    mirror the Linux Kernel, again we are fine) it is OK to align higher.
    The biggest changes here are that we always use 64 bytes for CPU_V7 even
    if for example the underlying core is only 32 bytes (this mirrors
    Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
    Linux Kernel) as we do not need multi-platform support (to this degree)
    and only the Cavium ThunderX 88xx series has a use for such large
    alignment.

    Cc: Albert Aribaud
    Cc: Marek Vasut
    Cc: Stefano Babic
    Cc: Prafulla Wadaskar
    Cc: Luka Perkov
    Cc: Stefan Roese
    Cc: Nagendra T S
    Cc: Vaibhav Hiremath
    Acked-by: Lokesh Vutla
    Cc: Steve Rae
    Cc: Igor Grinberg
    Cc: Nikita Kiryanov
    Cc: Stefan Agner
    Acked-by: Heiko Schocher
    Cc: Mateusz Kulikowski
    Cc: Peter Griffin
    Acked-by: Paul Kocialkowski
    Cc: Anatolij Gustschin
    Acked-by: "Pali Rohár"
    Cc: Adam Ford
    Cc: Steve Sakoman
    Cc: Grazvydas Ignotas
    Cc: Nishanth Menon
    Cc: Stephen Warren
    Cc: Robert Baldyga
    Cc: Minkyu Kang
    Cc: Thomas Weber
    Cc: Masahiro Yamada
    Cc: David Feng
    Cc: Alison Wang
    Cc: Michal Simek
    Cc: Simon Glass
    Cc: York Sun
    Cc: Shengzhou Liu
    Cc: Mingkai Hu
    Cc: Prabhakar Kushwaha
    Cc: Aneesh Bansal
    Cc: Saksham Jain
    Cc: Qianyu Gong
    Cc: Wang Dongsheng
    Cc: Alex Porosanu
    Cc: Hongbo Zhang
    Cc: tang yuantian
    Cc: Rajesh Bhagat
    Cc: Josh Wu
    Cc: Bo Shen
    Cc: Viresh Kumar
    Cc: Hannes Schmelzer
    Cc: Thomas Chou
    Cc: Joe Hershberger
    Cc: Sam Protsenko
    Cc: Bin Meng
    Cc: Christophe Ricard
    Cc: Anand Moon
    Cc: Beniamino Galvani
    Cc: Carlo Caione
    Cc: huang lin
    Cc: Sjoerd Simons
    Cc: Xu Ziyuan
    Cc: "jk.kernel@gmail.com"
    Cc: "Ariel D'Alessandro"
    Cc: Kever Yang
    Cc: Samuel Egli
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Hans de Goede
    Cc: Ian Campbell
    Cc: Siarhei Siamashka
    Cc: Boris Brezillon
    Cc: Andre Przywara
    Cc: Bernhard Nortmann
    Cc: Wolfgang Denk
    Cc: Ben Whitten
    Cc: Tom Warren
    Cc: Alexander Graf
    Cc: Sekhar Nori
    Cc: Vitaly Andrianov
    Cc: "Andrew F. Davis"
    Cc: Murali Karicheri
    Cc: Carlos Hernandez
    Cc: Ladislav Michl
    Cc: Ash Charles
    Cc: Mugunthan V N
    Cc: Daniel Allred
    Cc: Gong Qianyu
    Signed-off-by: Tom Rini
    Acked-by: Masahiro Yamada
    Acked-by: Chin Liang See
    Tested-by: Stephen Warren
    Acked-by: Paul Kocialkowski

    Tom Rini
     

26 Apr, 2016

1 commit

31 Jan, 2016

1 commit

  • 3709844f2   armv7: add cacheline sizes where missing ... Browse Code »

    Some armv7 targets are missing a cache line size declaration.
    In preparation for "arm: cache: Implement cache range check for v7"
    patch, add these declarations with the appropriate value for
    the target's SoC or CPU.

    Signed-off-by: Albert ARIBAUD
    Reviewed-by: Tom Rini

    Albert ARIBAUD
     

20 Jan, 2016

1 commit

22 Nov, 2015

3 commits

12 Oct, 2015

1 commit

28 Jul, 2015

1 commit

  • 9a0f4004c   configs: split ti_armv7_common into a omap generic header ... Browse Code »

    TI armv7 based SoCs are based on two architectures - one based on OMAP
    generation architecture and others based on Keystone architecture.

    Many of the options are architecture specific, however a lot are common
    with v7 architecture. So, step 1 will be to move out OMAP specific stuff
    from ti_armv7_common into a ti_armv7_omap.h header which is then used
    by all the relevant architecture headers.

    Reviewed-by: Tom Rini
    Signed-off-by: Nishanth Menon

    Nishanth Menon
     

13 Mar, 2015

2 commits

13 Feb, 2015

2 commits

24 Oct, 2014

1 commit

31 Aug, 2014

1 commit

18 Apr, 2014

2 commits

25 Jan, 2014

1 commit