15 Feb, 2018
1 commit
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Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.Signed-off-by: Tom Rini
10 Feb, 2018
1 commit
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To make this driver easier to be reused, dual-license DDR driver.
Signed-off-by: York Sun
CC: Simon Glass
CC: Tom Rini
CC: Heinrich Schuchardt
CC: Thomas Schaefer
CC: Masahiro Yamada
CC: Robert P. J. Day
CC: Alexander Merkle
CC: Joakim Tjernlund
CC: Curt Brune
CC: Valentin Longchamp
CC: Wolfgang Denk
CC: Anatolij Gustschin
CC: Ira W. Snyder
CC: Marek Vasut
CC: Kyle Moffett
CC: Sebastien Carlier
CC: Stefan Roese
CC: Peter Tyser
CC: Paul Gortmaker
CC: Peter Tyser
CC: Jean-Christophe PLAGNIOL-VILLARD
31 Jan, 2018
3 commits
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Variable "row_density" is no longer used. Drop it from DIMM structure.
Signed-off-by: York Sun
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DDR4 RDIMM has some information in SPD to be used to calculate the
control words for register chip. The rest can be found from JEDEC
spec DDR4RCD02.Signed-off-by: York Sun
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On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.Signed-off-by: York Sun
19 Jan, 2016
1 commit
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.Signed-off-by: Tom Rini
25 Feb, 2015
1 commit
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Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.Signed-off-by: York Sun
23 Apr, 2014
1 commit
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Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
26 Nov, 2013
1 commit
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Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.Signed-off-by: York Sun