31 Oct, 2016
9 commits
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Enable ROCKCHIP_SPL_BACK_TO_BROM and disable CONFIG_SPL_MMC_SUPPORT
to save memory in order to enable add source code for dram capacity
auto-detect.Signed-off-by: Kever Yang
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rk3399 has two mmc dev controller:
mmc 0: SD card;
mmc 1: EMMCU-Boot will scan the mmc boot device configured by CONFIG_SYS_MMC_ENV_DEV,
since evb has emmc on board, let's set the EMMC as default.Signed-off-by: Kever Yang
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The GRF base address is missing, fix it.
Signed-off-by: Kever Yang
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The Clock Multiplier in rk3399 EMMC programmable clock generator
is broken, we can remove its support from SoC GRF register.Without this patch, rk3399 emmc driver is not work after below patch
applied:
6dffdbc mmc: sdhci: Add the programmable clock mode supportSigned-off-by: Kever Yang
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.Signed-off-by: Simon Glass
Reviewed-by: Kever Yang -
This function is called from outside the driver. It should be placed into
common SoC code. Move it.Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.Signed-off-by: Simon Glass
Reviewed-by: Kever Yang -
This function is called from outside the driver. It should be placed into
common SoC code. Move it.Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.Signed-off-by: Simon Glass
Reviewed-by: Kever Yang -
clk_rk3399 is driver name, not device name
Signed-off-by: Jacob Chen
Acked-by: Simon Glass -
I am not sure why this limit is changing. But my kernel
doesn't load when it's above 256. This was testing on the
rock2 board.Signed-off-by: Sandy Patterson
Updated commit subject:
Signed-off-by: Simon Glass
30 Oct, 2016
23 commits
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The Cubieboard4 is an A80 SoC based development board from Cubietech.
This board has a UART port, 4 USB host ports, a USB 3.0 OTG connector,
HDMI and VGA outputs, a micro SD slot, 8G eMMC flash, 2G DRAM, a WiFi/BT
combo chip, headphone and microphone jacks, IR receiver, and GPIO headers.Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
mksunxiboot is useful outside of u-boot, it is e.g. used by sunxi-tools.
Signed-off-by: Stefan Brüns
Signed-off-by: Hans de Goede -
The A80 Optimus Board was launched with the Allwinner A80 SoC.
It was jointly developed by Allwinner and Merrii.This board has a UART port, a JTAG connector, 2 USB host ports, a USB
3.0 OTG connector, an HDMI output, a micro SD slot, 16G eMMC flash,
2G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone
jack, IR receiver, and additional GPIO headers.Signed-off-by: Chen-Yu Tsai
[hdegoede@redhat.com: update existing Merrii_A80_Optimus_defconfig
instead of adding a new defconfig]
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on the Pine64.
This is limited to the first USB controller at the moment, which is
connected to the lower USB socket on the Pine64 board.
[Andre: remove unneeded defines, enable OHCI, add commit message]Signed-off-by: Amit Singh Tomar
Signed-off-by: Andre Przywara
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede -
Both the A80 Optimus board and the Cubieboard 4 use a zq value of
4145117, or 0x3f3fdd.Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
Originally dram clock was set to 480MHz, but this behaves
unstable. To improve stability the clock is reduced to 384MHzSigned-off-by: Stefan Mavrodiev
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede -
The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses
are at an offset of 0x200 within the SID address space.Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
missing an alias entry to trigger the driver instantiation by U-Boot.
Add the line to point U-Boot to the Ethernet DT node.
This enables TFTP boot on the Pine64.Signed-off-by: Andre Przywara
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede -
In Allwinner's SDK the A80 is clocked to 1008 MHz by default.
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
ARCH_SUNXI selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT
is not used.Signed-off-by: Masahiro Yamada
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede -
The A80 can support 8-bit eMMC with reset on the PC pingroups.
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
CONFIG_SUNXI -> CONFIG_ARCH_SUNXI
and removed CONFIG_SUNIX from config_whitelist.txtCc: Simon Glass
Cc: Ian Campbell
Cc: Hans de Goede
Signed-off-by: Jagan Teki
Reviewed-by: Hans de Goede
Signed-off-by: Hans de Goede -
Now that DRAM initialization and clock setup is supported,
we can enable SPL for the A80.[wens@csie.org: Added commit message]
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).[wens@csie.org: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
Since the A80 has many cores which we intend to use in SMP fashion,
we should set the SMP bit for the boot CPU.[wens@csie.org: Added commit message]
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.[wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.[wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai
[hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks]
[hdegoede@redhat.com: Fix checkpatch warnings]
Signed-off-by: Hans de Goede -
OHCI has a known limitation of allowing only 32-bit DMA buffer
addresses, so we have a lot of u32 variables around, which are assigned
to pointers and vice versa. This obviously creates issues with 64-bit
systems, so the compiler complains here and there.
To allow compilation for 64-bit boards which use only memory below 4GB
anyway (and to avoid more invasive fixes), adjust some casts and types
and assume that the EDs and TDs are all located in the lower 4GB.
This fixes compilation of the OHCI driver for the Pine64.Signed-off-by: Andre Przywara
Reviewed-by: Hans de Goede
29 Oct, 2016
8 commits
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This was turned off by accident, re-enble.
Signed-off-by: Tom Rini
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Signed-off-by: Jagan Teki
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ARMv7 Tegra boards aren't currently covered by any other travis-ci jobs.
Add a new job to build them.Signed-off-by: Stephen Warren
Reviewed-by: Tom Rini
Reviewed-by: Heiko Schocher -
Use buildman to compile any U-Boot binary tested by test/py. This
re-uses all the work done elsewhere to make buildman work within
Travis-CI, in particular related to toolchain downloading and buildman
config file creation.Signed-off-by: Stephen Warren
Reviewed-by: Heiko Schocher -
Introduce run-time DDR PHY training.
Signed-off-by: Masahiro Yamada
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Add the LD11 SoC data and adjuts the printf() format because this is
a 64-bit SoC. Otherwise, 16-digits pointer addresses would break
the log format.Signed-off-by: Masahiro Yamada
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Do not hard-code the number of DX blocks because it is a different
value for LD11 SoC.Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it
is the last user.Signed-off-by: Masahiro Yamada
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The DDR PHY register view of LD11 is slightly different from that
of LD4/Pro4/sLD8, but it will be possible to share the register
macros (and I want to re-use as much code as possible). Change
the code in the more flexible form.Signed-off-by: Masahiro Yamada
