20 Jan, 2018
7 commits
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Now this driver is used across stm32f4, stm32f7 and stm32h7
SoCs family, give it a generic name.Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha -
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.Cc: Dan Murphy
Signed-off-by: Tom Rini -
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.Cc: Bin Meng
Cc: Simon Glass
Cc: Philipp Tomsich
Signed-off-by: Tom Rini
Reviewed-by: Simon Glass -
Add support for simple memory fill operation. With large data sizes
it is much faster to use EDMA for memory fill rather than CPU.Signed-off-by: Tero Kristo
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omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".Fix it here by using "&= ~()" to reset a bit.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini -
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini -
The omap hsmmc host controller can have the ADMA2 feature. It brings better
read and write throughput.
On most SOC, the capability is read from the hl_hwinfo register. On OMAP3,
DMA support is compiled out.Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
19 Jan, 2018
1 commit
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This reverts commit 46831c1a4cda75d92f7ad18d4e2b1eb196c62b2f.
This reserved area at the beginning of struct hsmm, will be used later to
support ADMASigned-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
18 Jan, 2018
1 commit
16 Jan, 2018
27 commits
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The operation should be OR, not BIT OR.
Signed-off-by: Peng Fan
Cc: Heiko Schocher
Cc: Stefano Babic -
The number 4 is dedicated on i.MX7ULP, but lpi2c will be reused on i.MX8,
4 is not valid. The seq number could be configured by alias node.The following patch will use i2c4 as the begin for i.MX7ULP.
Signed-off-by: Peng Fan
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this should be the norm for armv8 platforms.
Signed-off-by: Jorge Ramirez-Ortiz
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Signed-off-by: Jorge Ramirez-Ortiz
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Identify and distinguish between platform device type of MX7ULP
and LS1021A.This is a fix to commit 7edf5c45("serial: lpuart: add i.MX7ULP
support").Signed-off-by: Sriram Dash
Acked-by: Peng Fan
Reviewed-by: York Sun -
Signed-off-by: Zhao Qiang
Acked-by: Joe Hershberger -
This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig.
Signed-off-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
When we using network on board using sh-eth, it prints a lot of
"CACHE: Misaligned operation at range" messages.
This commit fixes this problem.Signed-off-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
This changes Change structure used in sh_eth_read and sh_eth_write function
from struct sh_eth_dev to struct sh_eth_info. This is necessary to convert
to Driver Model.Signed-off-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
bd_t is not used in sh_eth_config(). This deletes bd_t from sh_eth_config()
Signed-off-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
This fixes the chord style checked by checkpatch.pl.
Details of change details are as follows:- Fix typo
Change from alligned to aligned.
- Remove whitespace before ','
- Add spaces preferred around that '|'
- Fix missing a blank line after declarations
- Remove space after a cast declaration
- Fix format of block comments
- Add a blank line after function/struct/union/enum declarationsSigned-off-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
Add a b53_reg read/write command which allows inspecting the switch
registers. Because the Broadcom BCM53xx registers have different sizes,
we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain
expected results.Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger
Signed-off-by: Florian Fainelli -
Make sure that we pad small packets to a minimum length of 60 bytes
(without FCS). This is necessary to interface with Ethernet switches
that will reject RUNT frames unless padded correctly.Signed-off-by: Florian Fainelli
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Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar
to the Marvell MV88E617x. This takes care of configuring the minimum
amount out of the switch hardware such that each user visible port
(configurable) and the CPU port can forward packets between each other
while preserving isolation with other ports.This is useful for e.g: the Lamobo R1 board featuring a Broadcom
BCM53125 switch.Reviewed-by: Stefan Roese
Signed-off-by: Florian Fainelli -
This implementation manages several clocks, disable and
free all of them in case of error during probe and in remove
callback.Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
Acked-by: Joe Hershberger -
Add missing dev_count_phandle_with_args() to avoid
compilation issue.Signed-off-by: Patrice Chotard
Reviewed-by: Joe Hershberger -
This patch fixes a problem in the mvneta driver where if more than
one packet arrives between calls to mvneta_recv(), the additional
descriptors will be marked as free even though only one descriptor
has been read and processed from the receive queue. This causes
the additional packet(s) to be delayed until the next packet arrives.
>From this point on all packets will be delayed because the receive
queue will contain unprocessed packets but the hardware shows no
busy descriptors.Signed-off-by: Jason Brown
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
Since the return value is a signed int, if the leading MSB of rdreg is a 1,
it will get signed extended and will return a negative value which is an
error even though we read the correct value.Fixes: dfcc496ed7e2 ("net: mii: Changes not made by spatch")
Signed-off-by: Chris Brandt
Acked-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
First, this table could never be included in the build anyway because
SH_ETH_TYPE_RZ is not defined until later in the file.
Second, the register PIR was missing, so PHY MDIO never worked.
Third, after adding the PIR register, the table is EXACTLY the same as
sh_eth_offset_gigabit, so there is no value to it.Therefore, just delete it use the gigabit one.
Signed-off-by: Chris Brandt
Acked-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
The macros inl and outl maybe already be defined from file
arch/arm/include/asm/io.h so there may be no reason to define them.
And if you do try defined them here, you get a redefined complier warning.Signed-off-by: Chris Brandt
Acked-by: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger -
This commit allows extended Marvell registers to be read with:
foo > mdio rx FEC 3.10
Reading from bus FEC
PHY at address 0:
3.16 - 0x1063
foo > mdio wx FEC 3.10 0x1011The above code changes the way ETH connector LEDs blink.
Signed-off-by: Lukasz Majewski
Reviewed-by: York Sun
Acked-by: Joe Hershberger -
Need to not access the byte after the input_buffer.
Reported-by: Coverity (CID: 144423)
Signed-off-by: Joe Hershberger -
Although Xilinx Zynq SoC was using MACB similar hardware. However,
U-boot MACB driver was not supporting Xilinx Zynq SoC. This patch is
to add support for the Xilinx Zynq SoC to the existing MACB network
driver.This patch is to add Zynq GEM DMA Config, provide callback
function for different linkspeed for case of using Xilinx Zynq
Programmable Logic as GMII to RGMII converter.This patch convert the return value to use error codes.
Signed-off-by: Wilson Lee
Cc: Chen Yee Chew
Cc: Keng Soon Cheah
Cc: Joe Hershberger
Cc: Wenyou Yang
Acked-by: Joe Hershberger -
This is the node that would contain, for example, the framebuffer setup
by an earlier stage.Signed-off-by: Rob Clark
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Signed-off-by: Jorge Ramirez-Ortiz
15 Jan, 2018
1 commit
12 Jan, 2018
3 commits
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Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan -
In order to discard this code when unused in SPL we need to guard the
command with a check for CONFIG_SPL_BUILD and we rearrange the code
slightly to make this cleaner.Cc: Jaehoon Chung
Signed-off-by: Tom Rini -
By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.This means that theoretically, the highest bus reachable downstream is
bus 1.Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.Signed-off-by: Koen Vandeputte
