27 Jan, 2021
1 commit
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Multiple LX2(LX2160A/LX2162A SoC) personality variants
exists based on CAN-FD and security bit in SVR.Currenly SVR_SOC_VER mask only security bit.
Update SVR_SOC_VER to mask CAN_FD and security bit
for LX2 products.Signed-off-by: Wasim Khan
18 Sep, 2020
1 commit
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This patch moves the SVR definitiones to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.Signed-off-by: Hou Zhiqiang
08 Sep, 2020
1 commit
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LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.Signed-off-by: Meenakshi Aggarwal
26 Dec, 2019
1 commit
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Enable AHB support for Flexspi controller interface meaning
memory can be accessed via md command using absolute addressesSigned-off-by: Yogesh Gaur
Signed-off-by: Ashish Kumar
Signed-off-by: Rajat Srivastava
Signed-off-by: Kuldeep Singh
Reviewed-by: Priyanka Jain
21 Oct, 2019
3 commits
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LX2160A/LX2120A/LX2080A SVR value should be
0x873600/0x873620/0x873602
Previous values were valid only if CAN fuse is blown.Signed-off-by: Wasim Khan
Signed-off-by: Priyanka Jain -
ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.To disable multimedia feature on non-multimedia version,
set the status property to disabled in dts nodes.Signed-off-by: Tang Yuantian
Signed-off-by: Priyanka Jain -
Add LS1027A, LS1018A and LS1017A personalities support to
LS1028A SoC family.LS1028A is the prime personality of LS1028A SoC family.
LS1027A is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72
core, low power versions of the QorIQ LS1028A and LS1027A
SoCs respectively.Signed-off-by: Tang Yuantian
Signed-off-by: Priyanka Jain
22 May, 2019
1 commit
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Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.Signed-off-by: Sudhanshu Gupta
Signed-off-by: Rai Harninder
Signed-off-by: Rajesh Bhagat
Signed-off-by: Bhaskar Upadhaya
Signed-off-by: Tang Yuantian
Reviewed-by: Prabhakar Kushwaha
18 Jan, 2019
1 commit
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LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER.
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun
07 Dec, 2018
4 commits
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LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUsSigned-off-by: Bao Xiaowei
Signed-off-by: Hou Zhiqiang
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Vabhav Sharma
Signed-off-by: Sriram Dash
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.Signed-off-by: York Sun
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Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
Reviewed-by: York Sun -
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
[YS: fix multiple checkpatch issues]
Reviewed-by: York Sun
27 Jul, 2018
2 commits
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To get full access of QSPI space, initialize AHB interface.
Signed-off-by: York Sun
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Remove the old implementation in order to enable DM for sata.
Signed-off-by: Tang Yuantian
Reviewed-by: Simon Glass
Reviewed-by: York Sun
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
23 Mar, 2018
1 commit
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1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.Signed-off-by: Calvin Johnson
Signed-off-by: Anjaneyulu Jagarlmudi
Acked-by: Joe Hershberger
24 Jan, 2018
1 commit
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Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.Signed-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
Reviewed-by: York Sun
11 Jan, 2018
1 commit
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Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively. Calculate those parameters from port clock frequency.
Overwrite those registers with calculated values to get better OOB
timing.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun
14 Dec, 2017
1 commit
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Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.Signed-off-by: Wenbin Song
Reviewed-by: York Sun
11 Sep, 2017
2 commits
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Some erratum patch might need it to program registers.
Signed-off-by: Ran Wang
Reviewed-by: York Sun -
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.Signed-off-by: Alison Wang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Signed-off-by: Raghav Dogra
Signed-off-by: Shaohui Xie
[YS: Revised commit message]
Reviewed-by: York Sun
01 Aug, 2017
1 commit
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Update SVR as per the SOC document.
-LS2081A: 0x870919 -> 0x870918
-LS2041A: 0x870915 -> 0x870914Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun
06 Jun, 2017
1 commit
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We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.Signed-off-by: Simon Glass
24 May, 2017
1 commit
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The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.Signed-off-by: Priyanka Jain
Signed-off-by: Santan Kumar
Reviewed-by: York Sun
19 Jan, 2017
2 commits
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The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.Signed-off-by: Wenbin Song
Signed-off-by: Mingkai Hu
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if neededSigned-off-by: Hou Zhiqiang
Reviewed-by: York Sun
23 Nov, 2016
2 commits
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The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC moduleSigned-off-by: Priyanka Jain
Reviewed-by: York Sun -
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
07 Oct, 2016
2 commits
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By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.Signed-off-by: Tang Yuantian
[York Sun: Reformatted commit message]
Reviewed-by: York Sun -
The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun
15 Sep, 2016
1 commit
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As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun
27 Jul, 2016
1 commit
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The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.Signed-off-by: Hou Zhiqiang
Signed-off-by: Mihai Bantea
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
Reviewed-by: York Sun
29 Jun, 2016
1 commit
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Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.So append "A" to SoC names.
Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
13 Jun, 2016
1 commit
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Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
04 Jun, 2016
1 commit
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The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4Signed-off-by: Calvin Johnson
Signed-off-by: Makarand Pawagi
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
07 Apr, 2016
1 commit
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LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.Signed-off-by: York Sun
CC: Prabhakar Kushwaha
Reviewed-by: Prabhakar Kushwaha
29 Mar, 2016
2 commits
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Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
Reviewed-by: York Sun -
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
Reviewed-by: York Sun
26 Jan, 2016
1 commit
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Freescale's LS2040A is a another personality of LS2080A SoC
without AIOP support consisting of 4 armv8 cores.Signed-off-by: Pratiyush Mohan Srivastava
Acked-by: Prabhakar Kushwaha
Reviewed-by: York Sun
