13 Jan, 2014
2 commits
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The array reserved as a placeholder in the structure ipu_idmac
should contain 44 32bit unsigned integer entries instead of 45
ones, because the placeholder is located bewteen the register
IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address
offsets of 0x804c and 0x8100 respectively.Reported-by: Robin Gong
Acked-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying -
The array reserved1 as a placeholder in the structure ipu_cm
should contain 4 32bit unsigned integer entries instead of 16
ones, because the placeholder is located bewteen the register
IPU_CH_DB_MODE_SEL_1 and the register IPU_ALT_CH_DB_MODE_SEL_0
with the address offsets of 0x154 and 0x168 respectively.Reported-by: Robin Gong
Acked-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying
10 Jan, 2014
2 commits
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Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.Conflicts:
include/configs/exynos5250-dt.hSigned-off-by: Tom Rini
09 Jan, 2014
8 commits
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To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Pantelis Antoniou
Cc: Wolfgang Denk
Acked-by: Pantelis Antoniou -
The eMMC and the SD-Card specifications describe the optional SET_DSR command.
During measurements at our lab we found that some cards implementing this feature
having really strong driver strengts per default. This can lead to voltage peaks
above the specification of the host on signal edges for data sent from a card to
the host.Since availability of a given card type may be shorter than the time a certain
hardware will be produced it is useful to have support for this command (Alternative
would be changing termination resistors and adapting the driver strength of the
host to the used card.)Following proposal for an implementation:
- new field that reflects CSD field DSR_IMP in struct mmc
- new field for design specific DSR value in struct mmc
- board code can set DSR value in mmc struct just after registering an controller
- mmc_startup sends the the stored DSR value before selecting a card, if DSR_IMP is setAdditionally the mmc command is extended to make is possible to play around with different
DSR values.The concept was tested on a i.MX53 based platform using a Micron eMMC card where the default
DSR is 0x0400 (12mA) but in our design 0x0100 (0x0100) were enough. To use this feature for
instance on a mx53loco one have to add a call to mmc_set_dsr() in board_mmc_init() after
calling fsl_esdhc_initialize() for the eMMC.Signed-off-by: Markus Niebel
Acked-by: Pantelis Antoniou -
Fixup prints to show where the print is done from, and
a few minor formatting/grammar issues.Signed-off-by: Darwin Rambo
Acked-by: Pantelis Antoniou -
Bounce buffer implementation takes care of proper data buffer alignemt
and correct flush/invalidation of data cache at once so we no longer
depend on input data variety and make sure CPU and MMC controller deal
with expected data in case of enabled data cache.Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in
board configuration, otherwise corresponding library won't be compiled
and linker will fail to build resulting executable.Difference since v1 - fixed compile-time warning with type casting to
"void *":Slight edit to remove UTF8 characters in the commit message.
Acked-by: Jaehoon Chung
Tested-by: Jaehoon Chung
Acked-by: Pantelis Antoniou====
passing argument 2 of 'bounce_buffer_start' discards 'const' qualifier
from pointer target type
====Signed-off-by: Alexey Brodkin
Cc: Mischa Jonker
Cc: Alim Akhtar
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Amar
Cc: Kyungmin Park
Cc: Minkyu Kang
Cc: Simon Glass
Cc: Pantelis Antoniou
Cc: Andy Fleming -
The original codes misused recvbuf in source buffer instead of sendbuf,
and read from incorrect offset 14 instead of 22.Signed-off-by: Che-Liang Chiou
Signed-off-by: Simon Glass
Reviewed-by: Simon Glass
Tested-by: Che-Liang Chiou -
Add a simple TPM emulator for sandbox. It only supports a small subset of
TPM operations. However, these are enough to perform common tasks.Note this is an initial commit to get this working, but it could use
cleaning up (for example constants instead of open-coded values).Signed-off-by: Simon Glass
Signed-off-by: Simon Glass
Reviewed-by: Simon Glass -
Provide a way to use any host file or device as a block device in U-Boot.
This can be used to provide filesystem access within U-Boot to an ext2
image file on the host, for example.The support is plumbed into the filesystem and partition interfaces.
We don't want to print a message in the driver every time we find a missing
device. Pass the information back to the caller where a message can be printed
if desired.Signed-off-by: Henrik Nordström
Signed-off-by: Simon Glass
- Removed change to part.c get_device_and_partition()Signed-off-by: Simon Glass
Reviewed-by: Simon Glass -
To enhance the SDMMC DesignWare driver to use calloc instead of
malloc. This will avoid the incident that uninitialized members
of mmc structure are later used for NULL comparison.Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Mischa Jonker
Cc: Alexey Brodkin
Cc: Andy Fleming
Cc: Pantelis Antoniou
Acked-by: Pantelis Antoniou
08 Jan, 2014
1 commit
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The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.Signed-off-by: Tom Rini
06 Jan, 2014
1 commit
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Conflicts:
include/micrel.hThe conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
03 Jan, 2014
1 commit
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Enable fuse supply before fuse programming and disable after.
Signed-off-by: Sergey Alyoshin
Reviewed-by: Benoît Thébaudeau
31 Dec, 2013
1 commit
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Fix unaligned access in OneNAND core. The problem is that the ffchars[] array
is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed
to the memcpy_16() function. The memcpy_16() function will treat the buffer as
an array of "unsigned short", thus triggering unaligned access if the compiler
decided ffchars[] to be not aligned.I managed to trigger the problem with regular ELDK 5.4 GCC compiler.
Signed-off-by: Marek Vasut
Cc: Albert Aribaud
Cc: Scott Wood
Cc: Tom Rini
20 Dec, 2013
1 commit
19 Dec, 2013
13 commits
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claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.Signed-off-by: Sourav Poddar
Tested-by: Yebio Mesfin
Reviewed-by: Jagannadha Sutradharudu Teki -
Fix the register access in EHCI HCD. We need to use address of the register
as an ehci_writel() argument.Signed-off-by: Marek Vasut
Cc: Simon Glass -
In case the controller is not initialized, we shall not de-initialize it.
As the control structure will not be filled, we will produce a null ptr
dereference if the controller is not inited.Signed-off-by: Marek Vasut
Cc: Simon Glass -
The detection function of the EHCI PCI controller was really cryptic,
add a beefy comment and clean the portion of the code up a bit. No
change in the logic of the code.Signed-off-by: Marek Vasut
Cc: Simon Glass -
Code cleanup for dfu_bind_config function
Signed-off-by: Lukasz Majewski
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It is necessary to deter the host from sending subsequent DFU_GETSTATUS
request in the case of e.g. writing the buffer to medium.Here the timeout is increased when we fill up the whole buffer. This delay
allows eMMC memory to perform its internal operations.
Otherwise we end up with HOST's error regarding GET_STATUS receive timeout.Signed-off-by: Lukasz Majewski
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The method for exporting size of allocated buffer is provided.
It is afterwards used by USB's dfu function code.Signed-off-by: Lukasz Majewski
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The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.Signed-off-by: Yen Lin
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren
Reviewed-by: Jagannadha Sutradharudu Teki -
This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.Signed-off-by: Kouei Abe
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Jagannadha Sutradharudu Teki -
Add support for Macronix MX25L2006E SPI flash.
Signed-off-by: Luka Perkov
Reviewed-by: Jagannadha Sutradharudu Teki -
All other hex values in sf_probe.c are in lower case so we should
fix this one too.Signed-off-by: Luka Perkov
Reviewed-by: Jagannadha Sutradharudu Teki -
Create the i2c adapter object for the fifth bus on SoC with more than
4 buses. This allow using all the bus available on T30.Signed-off-by: Alban Bedel
Acked-by: Heiko Schocher
Signed-off-by: Tom Warren
18 Dec, 2013
8 commits
-
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
SH7753 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
If we change to software ecc and then back to hardware ecc, the nand ecc ops
pointers are populated with incorrect function pointers. This is related to the
way nand_scan_tail() handles assigning functions to ecc ops:If we are switching to software ecc/no ecc, it assigns default functions to the
ecc ops pointers unconditionally, but if we are switching to hardware ecc,
the default hardware ecc functions are assigned to ops pointers only if these
pointers are NULL (so that drivers could set their own functions). In the case
of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are
assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc,
the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite
them with hw ecc functions.
The result: sw ecc functions used to write hw ecc data.Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that
ops which were not assigned by the driver will get the correct default values
from nand_scan_tail().Cc: Scott Wood
Cc: Pekon Gupta
Signed-off-by: Nikita Kiryanov -
When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values
into the current nand chip's ecc.layout struct. This is done under the
assumption that the struct exists only to store values, so it is OK to overwrite
it, but there is at least one situation where this assumption is incorrect:When switching to 1 bit hamming code sw ecc, the job of assigning layout data
is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a
pointer to an existing struct prefilled with the appropriate values. This struct
doubles as both data and layout definition, and therefore shouldn't be
overwritten, but on the next switch to hardware ecc, this is exactly what's
going to happen. The next time the user switches to software ecc, they're
going to get a messed up ecc layout.Prevent this and possible similar bugs by explicitly using the
private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode.Cc: Scott Wood
Cc: Pekon Gupta
Signed-off-by: Nikita Kiryanov -
length is size_t so needs to be '%zd' not '%d' to avoid warnings.
Cc: Scott Wood
Signed-off-by: Tom Rini -
Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic
platform" (d016dc42cedbf6102e100fa9ecb58462edfb14f8) changed the way
software ECC is configured, both during boot, and during ecc switch, in a way
that is not backwards compatible with older systems:Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring
for software ecc, relying on nand_scan_tail() to select a default for ecc.size
(256), while the new version of omap_gpmc.c assigns ecc.size = pagesize,
which is likely to not be 256.Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert
to the original behavior.Cc: Igor Grinberg
Cc: Tom Rini
Cc: Scott Wood
Cc: Pekon Gupta
Signed-off-by: Nikita Kiryanov
Acked-by: Pekon Gupta -
Signed-off-by: Stefan Roese
Cc: Pekon Gupta
Cc: Scott Wood
[scottwood@freescale.com: wrap some long lines]
Signed-off-by: Scott Wood -
As per OMAP3530 TRM referenced below [1]
For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
- OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
- OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND deviceThus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
*for x8 NAND Device*
+--------+---------+---------+---------+---------+---------+---------+
| xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
+--------+---------+---------+---------+---------+---------+---------+*for x16 NAND Device*
+--------+--------+---------+---------+---------+---------+---------+---------+
| xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
+--------+--------+---------+---------+---------+---------+---------+---------+This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.[1] OMAP3530: http://www.ti.com/product/omap3530
TRM: http://www.ti.com/litv/pdf/spruf98x
Chapter-25: Initialization Sub-topic: Memory Booting
Section: 25.4.7.4 NAND
Figure 25-19. ECC Locations in NAND Spare AreasReported-by: Stefan Roese
Signed-off-by: Pekon Gupta
Tested-by: Stefan Roese
16 Dec, 2013
1 commit
13 Dec, 2013
1 commit
-
Signed-off-by: Masahiro Yamada
