15 May, 2012
40 commits
-
We want to able to decode Linux fdt keymaps, so bring part of this
enormous header file over to U-Boot.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Sometimes we don't need a full cell for each value. This provides
a simple function to read a byte array, both with and without
copying it.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
This enables LP0 to support suspend / resume on Seaboard.
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
This adds timings for T20 and T25 Seaboards, using the bindings found here:
http://patchwork.ozlabs.org/patch/132928/
We supply both full speed options for normal running, and half speed options
for testing / development.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus.
This allows us to talk to the PMU.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Add a definition of the memory controller node according to the bindings
here:http://patchwork.ozlabs.org/patch/132928/
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25).
Signed-off-by: Simon Glass
Acked-by: Stephen Warren
Signed-off-by: Jimmy Zhang
Signed-off-by: Tom Warren -
Tegra core power rail has leakage voltage around 0.2V while system in
suspend mode. The source of the leakage should be coming from PMC power
detect logic for IO rails power detection.
That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0'
to PWR_DET (APBDEV_PMC_PWR_DET_0).Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Call the function to put warmboot boot in a suitable place for resume.
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Save SDRAM parameters into the warmboot scratch registers
Signed-off-by: Simon Glass
Signed-off-by: Yen Lin
Signed-off-by: Tom Warren -
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.Signed-off-by: Yen Lin
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Adjust PMU to permit maximum frequency operation.
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.- Split PMU code into separate TPS6586X driver
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Add a basic header file for this register, to be filled in as needed.
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.Signed-off-by: Simon Glass
Acked-by: Stephen Warren
Signed-off-by: Tom Warren -
These headers provide access to additional Tegra features.
flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registersSigned-off-by: Simon Glass
Signed-off-by: Yen Lin
Signed-off-by: Tom Warren -
Provides an interface to aes.c for the warmboot code.
Signed-off-by: Simon Glass
Signed-off-by: Yen Lin
Signed-off-by: Tom Warren -
Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
We want to include this from board code, so move the header into
an easily-accessible location.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Add support for AES using an implementation from Karl Malbrain.
This offers small code size (around 5KB on ARM) and supports 128-bit
AES only.Signed-off-by: Yen Lin
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
This power management chip supports battery charging and a large number
of power supplies. This initial driver only provides the ability to adjust
the two synchronous buck converters SM0 and SM1 in a stepwise manner.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
This macro is generally useful to make it available in common.
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren
Acked-by: Tom Rini
Acked-by: Mike Frysinger -
We need to iterate through subnodes of a parent, looking only at
compatible nodes. Add a utility function to do this for us.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
fdtdec_locate_array() locates an integer array but does not copy it. This
saves the caller having to allocated wasted space.Access to array elements should be through the fdt32_to_cpu() macro.
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Do not define serial_putc() and serial_puts() calls if
CONFIG_SPL_SERIAL_SUPPORT is set.Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk
Acked-by: Stefano Babic -
If the WP function is NULL, simply assume the card is always RW.
Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Wolfgang Denk
Cc: Detlev Zundel
Cc: Fabio Estevam
Acked-by: Stefano Babic -
Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
This code is part of battery boot support for i.MX28.
Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF
data pins interferes with the BootROM's boot mode sampling. So shut the
controller down.Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
This patch implements code that samples i.MX28 boot pads and reports boot mode
accordingly.Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
Pass memory size from SPL via structure located in SRAM instead of SCRATCH
registers. This allows passing more data about boot from SPL to U-Boot, like the
boot mode pads configuration.Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
Add "update_sd_firmware" command to easily reload the SD card of
m28evk kit. This comes handy when the board boots from SD card.Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
Abstract out common register setup. This also configured r_cntrl
to correct value at registration time.Signed-off-by: Marek Vasut
Cc: Detlev Zundel
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Wolfgang Denk -
After an update to the MX51 reference manual (Rev. 5), the
values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
are now clearly wrong:"Bit 13:
High / Low Output Voltage Range. This bit selects the output voltage mode for
SD2_CMD. 0 High output voltage mode
1 Low output voltage mode"The values are currently negated in code - fixed.
Reported-by: David Jander
Signed-off-by: Stefano Babic
CC: Marek Vasut
CC: David Jander
Acked-by: David Jander
Acked-by: Marek Vasut -
This solves issues when larger amount of DRAM is used, like 256MB.
Behave the same in case of CPU bypass as we do in case of EMI
bypass, but wait 15 ms. We need to wait until the clock domain
stabilizes.This issue seemed to have been caused by not waiting after frobbing
with the CPU bypass, it was unrelated to memory, but had a direct
impact, causing trouble. This was yet another X-File of the
imx-bootlets, sigh. The conclusion is, trying a semi-random delay
(there is delay after the EMI bypass change), the issue is fixed.Another possible explanation is that we do not do the "simple memory
test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
the memory, while also outputing something on the serial port). This
might have caused the similar delay in the imx-bootlets and therefore
they didn't need to add this explicitly.For now, this seems good fix enough, but to me, whole that memory
init code in imx-bootlets is completely flunked and it'd need deeper
investigation.Signed-off-by: Marek Vasut
Cc: Wolfgang Denk
Cc: Detlev Zundel
Cc: Stefano Babic
Cc: Fabio Estevam
Acked-by: Stefano Babic
Acked-by: Detlev Zundel
