11 Feb, 2019
3 commits
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The usb mass storage (f_mass_storage.c) uses fixed usb index 0,
this causes problem while CDNS3 USB controller index is 1.
Modify the API of fsg to pass the controller index.Signed-off-by: Ye Li
Reviewed-by: Jun Li -
According to latest datasheet IMX8MMCEC_Rev_0, the typical voltage
of VDD_DRAM for 1.5GHz DDR clock is 0.95v. Because BD71847MWV PMIC
does not support 0.95v output. We change the voltage to 0.975v as
the note in datasheet mentioned it is acceptable and supported.Signed-off-by: Ye Li
Reviewed-by: Bai Ping -
Sync the SCFW API to latest commit below:
commit 0721a2af721fca45e9d7e9b673b669ffab9aca7f
Author: Glen Wienecke
Date: Sun Feb 10 19:16:56 2019 -0600SCF-296: Partition reboot should not reset FSPI/OCRAM if in use
- Update ss_rsrc_reset to return BUSY error if FSPI/OCRAM in use
- Update pm_update_ridx to skip power transition if FSPI/OCRAM in use
- For user_mode update requests, reflect mode achieved after pm_update_ridx
- Add PM SVC call to get active mode (user_mode not accurate during transitions)
- Undo some MISRA updates that changed ss_rsrc_reset to void functionSigned-off-by: Glen Wienecke
Signed-off-by: Ye Li
Acked-by: Peng Fan
06 Feb, 2019
1 commit
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Add ability for hab_status command to show All HAB events and not just
HAB failure eventsSigned-off-by: Utkarsh Gupta
Reviewed-by: Ye Li
31 Jan, 2019
2 commits
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Open configs to add trusty os support for imx8q xen
build. The rpmb keyslot package must be checked and
copied to secure memory before trusty os boot.Change-Id: I66201783fa8439f2685377c10f257f064057dcfa
Signed-off-by: Ji Luo -
Since misc_seco APIs are deprecated in SCFW, need switch to new
APIs.Signed-off-by: Ye Li
Acked-by: Peng Fan
30 Jan, 2019
2 commits
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Update SCFW API to below commit which has deprecated APIs with
misc_seco prefix.commit 30b8f67097d65c6e22f218b106aeafdc636aece3
Author: Chuck Cannon
Date: Fri Jan 25 15:24:55 2019 -0600SCF-60: MISRA fixes.
Signed-off-by: Chuck Cannon
Signed-off-by: Ye Li
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Current container parser only load 0x400 as container header size.
However, the signature block in container header may exceed 0x400 size,
when using certificate or 4096bits RSA keys to sign image, so we
have to load the entire header according to container length field.
Otherwise the container authentication will failSigned-off-by: Ye Li
Reviewed-by: Peng Fan
25 Jan, 2019
4 commits
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SCFW has taken to reset the base board by deasserting BB_PER_RST_B(SCU_GPIO0_01) on
imx8QM MEK board, and has removed the SC_R_BOARD_R1 functionality.
So We don't need to explicitly use SC_R_BOARD_R1, delete the codes from u-boot.Signed-off-by: Ye Li
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Since different ARM2/Validation boards use different kernel FDT, configure
them to CONFIG_DEFAULT_FDT_FILE in defconfigSigned-off-by: Ye Li
Reviewed-by: Peng Fan -
There are two new validation boards: LPDDR4 board (30123) and DDR3L board (30010)
for imx8x family 17x17 chips. These two boards have same design except the DDR.
Since SCFW is resposible for DDR initialization, U-boot could use one build to
cover two boards.
The 8DX 17x17 DDR3L ARM2 has been added into u-boot before, so we rename the config
CONFIG_TARGET_IMX8DX_DDR3_ARM2 to CONFIG_TARGET_IMX8X_17X17_VAL to cover DDR3L and
LPDDR4.Considering 8DX and 8QXP 17x17 may solder to the boards, we create two defconfig:
one for DX and another for 8qxp to share with the CONFIG_TARGET_IMX8X_17X17_VAL
but with different FDTs.Signed-off-by: Ye Li
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Before booting kernel, we check all nodes in kernel FDT whether they
are owned in our partition. If it is not owned, we will disable it in FDT.For fused iMX8X 17x17 parts, like DC0 is disabled, SCFW only disable SC_R_DC_0,
other sub-modules in DC0 SS are still assign to our partition. Since DC0 is fused,
we actually can't access these sub-modules.This patch changes the algorithm to check resources along the power domain tree to the
top node of that SS power domain. If any resource in the PD tree is not owned, we will
disable the peripheral node.
For example, the i2c0_mipi_lvds1 peripheral node, according to power domain tree,
we checks resources: SC_R_MIPI_1_I2C_0 --> SC_R_MIPI_1 --> SC_R_DC_0. When SC_R_DC_0
is not owned, we will disable the i2c0_mipi_lvds1 peripheral node from FDT.Signed-off-by: Ye Li
24 Jan, 2019
1 commit
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For dual bootloader, slot selection is made at spl stage, go to
fastboot when current slot is marked as unbootable in AVB will
give the user a chance to recover current slot with fastboot
commands. But in this scenario, the device can't switch to another
bootable slot automatically when a slot is marked as unbootable.Reboot the board when current slot is marked as unbootable to make the
slot switch happen in spl.Test: Slot switch to 'b' automatically when 'a' is marked as unbootable
on imx8qxp_mek.Change-Id: I94237965970d0c17ed564cf76e08d353f7b9c047
Signed-off-by: Luo Ji
22 Jan, 2019
4 commits
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The imx8qm_arm2 has duplcated settings for initrd_addr and initrd_high,
and needs to change initrd_addr to 0x83100000 to align with other imx8
boards.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
On most of mx6 and mx7 platforms, we set the initrd address to 0x3800000
offset from DRAM base. However, the optee address is 0x4000000 offset from
DRAM base. So it will cause memory overlap when using initramfs and optee at
same time, for example using uuu to boot into kernel.To fix the conflict, we set initrd address to 0x6680000 offset from DRAM base,
because OPTEE needs reserve 32MB memory from 0x4000000 offset to 0x6000000 offset.Signed-off-by: Ye Li
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On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.Signed-off-by: Ye Li
Reviewed-by: Bai Ping -
Since imx8mm TMU needs to load some registers from fuse, this is arch
dependent operation and may vary on different platforms. So add
a interface for arch level initialization.Signed-off-by: Ye Li
21 Jan, 2019
6 commits
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Fix some warinings as "defined but not used [-Wunused-function]".
for CAAM.Test: Build and boot on imx8qm_mek.
Change-Id: I632257615a237ca2de96937e121e7a4bcab415ce
Signed-off-by: Luo Ji -
According to the latest datasheet, software is expected to program
the VDD_SOC voltage to the typical value 0.85V prior to the first
DRAM memory access. At default the VDD_SOC is 0.8V from PMIC BUCK1,
so we have to change it to 0.85V in SPL.Signed-off-by: Ye Li
Tested-by: Anson Huang -
Enable the new mipi panel driver and add parameters to board codes.
We enable the RM68200_WXGA as default panel, users can set "panel"
environment variable to switch to different panel.Signed-off-by: Ye Li
Reviewed-by: Fancy Fang -
Since LCDIF does not have a dedicated PLL as its source, we have to
find a best frequency closed to the target frequency. The previous
method is finding a closed clock with actual frequency higher than target.
But this causes problem to DSI PHY clock which uses target frequency to
calculate its clock parameters. When the actaul pixclock is higher,
it may violates the requirement between DSI PHY clock and LCDIF pixclock clock.
clk_byte_freq >= dpi_pclk_freq * DPI_pixel_size / ( 8 * (cfg_num_lanes + 1))So we'd better selecting a LCDIF clock not exceed the target frequency.
Signed-off-by: Ye Li
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The previous driver uses a hard coded value which generates the DSI
PHY clock can fit HX8363 WVGA screen. But when switching to new WXGA
screen which needs higher pixclock and higher DSI PHY clock, the
hard coded parameters can't work.
Change to follow kernel codes to find the best value of CM, CN, CO
parameters for DSI PHY clock to meet pixclock requirement.Signed-off-by: Ye Li
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mx7ulp EVK B will use two mipi dsi panels, the new panel RM68200_WXGA
supports WXGA resolution.Signed-off-by: Ye Li
19 Jan, 2019
1 commit
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When booting M4 with alt_config enabled, M4 will reserve 128MB for
video framebuffer from 0x88000000 to its partition, but Dom0 linux
loading address is 0x85000000, which will cause confict, so change
xenlinux_addr from 0x85000000 to 0x92000000.Signed-off-by: Flynn xu
Reviewed-by: Peng Fan
18 Jan, 2019
5 commits
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Kick the CAAM JR3 before kicking the SMMU, so SMMU error
won't affect CAAM functions.Test: build and boot on imx8qxp_mek.
Change-Id: Iaa9a6084f226f81a087aac1eced93e8785861113
Signed-off-by: Ji Luo -
Open configs to enable dual bootloader feature for
imx8q Android Auto.Test: Build and boot on imx8q.
Change-Id: I99da2ee6b87efd201e16df1046188ae86cab1466
Signed-off-by: Ji Luo -
Support dual bootloader feature for imx8q which uses the
container format. Move the A/B slot select and verify to
SPL stage, the bootloader rollback index will be stored
at the last 8K bytes of eMMC rpmb storage.Test: Boot and rbindex verify pass on imx8q.
Change-Id: I0a48210f65984a083037a0cd3f9558951029ed7d
Signed-off-by: Ji Luo -
The CAAM driver in u-boot will use JR0 by default, but for
imx8q, both JR0 and JR1 are assigned to SECO and A core
should never access them.
Power on the JR3 in this patchset and use it to complete
the CAAM operations for imx8q.Test: CAAM self test cases pass for imx8q.
Change-Id: Ie3d77d1f2910e7f4c257c797c12b5c8a30ad936a
Signed-off-by: Ji Luo -
Add CAAM RNG generating and BLOB encap/decap
self test cases.Test: Test cases pass on imx8qm_mek/imx6qp_sabresd.
Change-Id: I538f7b1581b36df83a3006ac133ca9e7b57ab4f0
Signed-off-by: Ji Luo
17 Jan, 2019
1 commit
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Add new u-boot command "imx_tamper" to configure and check the tamper pins.
The codes are used for reference and test. So command is disabled at default,
user can enable it by adding CONFIG_IMX_TAMPER=y to defconfigThe iMX7D has 10 tamper pins those can be used for SNVS tamper detection.
Tamper 9 pin is NVCC_DRAM power switch for LPSR by default.
It must be fused to tamper function by command
=> fuse prog -y 1 3 0x80000000
Otherwise, SNVS power consumption would be highWhen tamper is detected, CPU can't enter/stay in SNVS mode,
the tamper must be cleared and disabled before enter SNVS.Signed-off-by: Ye Li
Signed-off-by: Shaojun Wang
Acked-by: Peng Fan
16 Jan, 2019
4 commits
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Current MXC NAND driver uses memory BBT, it will create memory BBT in each
booting by searching bad blocks.This patch enables the flash BBT, so the NAND driver can read back Bad block
table on the flash chip to create memory BBT.Signed-off-by: Ye Li
Acked-by: Peng Fan -
The new uuu will change to burn entire boot image to nandfit mtdpart not
only the FIT image. We enable REDUND offset configuration here, so that SPL will
try to find FIT header at two locations: the begin of nandfit mtdpart and
the 0x57c00 offset of nandfit mtdpart. This helps to be compatible with both
old and new uuu.Signed-off-by: Ye Li
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The RAW image support must be disabled, otherwise a RAW image can be used
to bypass FIT image.Signed-off-by: Ye Li
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Add the NAND support to SPL container parser and enable it for imx8qxp arm2
nand reworked board.
The SPL NAND will read from nandfit mtdpart (128MB offset) to parsing the entire
boot image and get the 3rd container from it. This requires burning tool (uuu)
to program the entire boot image into nandfit.Signed-off-by: Ye Li
15 Jan, 2019
2 commits
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Add new u-boot command "ahab_status" to display seco events
and current lifecycle. It parses the seco event only for authenticating
container command, so that user can know the authentication failure.Signed-off-by: Ye Li
Acked-by: Peng Fan -
Update SCFW API from below SCFW commit which provides
the API to get seco eventscommit 50355d4b11b089be8fc1bc13afa7da001b081a44
Author: Chuck Cannon
Date: Mon Jan 14 12:30:42 2019 -0600SCF-275: Fix monitor error on command 'event'.
Signed-off-by: Chuck Cannon
Signed-off-by: Ye Li
09 Jan, 2019
4 commits
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Due to some USB configurations are moved to header file to bypass
SPL build. Changes android and androidatuo defconfigs and header
files to avoid build break.Signed-off-by: Ye Li
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Enable the SPL SDP driver and USB driver in MEK board codes and defconfigs.
Because the USB driver needs larger malloc pool, increase the malloc size
and disable simple mallocSigned-off-by: Ye Li
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The SPL won't use host mode, and the tcpc is default set as device mode.
So we don't need to access tcpc in SPL.Signed-off-by: Ye Li
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Add support to f_sdp to search and load iMX8 container image or iMX8M
FIT image by new UUU command SDPV.When using the SDPV, the uuu will continue to send out data after first
level boot loader used by ROM. This means uuu won't skip to the offset
of the second boot loader, and the padding data before second boot loader
will be sent out. So we have to search the FIT header or container header
in the buffer that SDP received.The new BCD value is used by uuu to distinguish if the SPL supports the
SDPV.Signed-off-by: Ye Li