06 Aug, 2018
1 commit
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the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.the same method can be use for DDR4. will be added later.
Signed-off-by: Bai Ping
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
20 Nov, 2017
1 commit
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Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.Signed-off-by: Ian Ray
Signed-off-by: Martyn Welch
14 Aug, 2017
1 commit
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NVM Express (NVMe) is a register level interface that allows host
software to communicate with a non-volatile memory subsystem. This
interface is optimized for enterprise and client solid state drives,
typically attached to the PCI express interface.This adds a U-Boot driver support of devices that follow the NVMe
standard [1] and supports basic read/write operations.Tested with a 400GB Intel SSD 750 series NVMe card with controller
id 8086:0953.[1] http://www.nvmexpress.org/resources/specifications/
Signed-off-by: Zhikang Zhang
Signed-off-by: Wenbin Song
Signed-off-by: Bin Meng
Reviewed-by: Tom Rini
12 Jul, 2017
2 commits
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At present we have the SCSI drivers in the drivers/block and common/
directories. It is better to split them out into their own place. Use
drivers/scsi which is what Linux does.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present we have the SATA and PATA drivers mixed up in the drivers/block
directory. It is better to split them out into their own place. Use
drivers/ata which is what Linux does.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
22 May, 2017
1 commit
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This subsystem is quite old. It has been replaced with a driver-model
version (UCLASS_THERMAL). Boards are free to convert to that if required,
but here is a removal patch that could be applied in the meantime.Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
Reviewed-by: Tom Rini
10 May, 2017
1 commit
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The PHY framework provides a set of APIs to control a PHY. This API is
derived from the linux version of the generic PHY framework.
Currently the API supports init(), deinit(), power_on, power_off() and
reset(). The framework provides a way to get a reference to a phy from the
device-tree.Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Simon Glass
18 Apr, 2017
1 commit
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If the system is running PSCI firmware, the System Reset function
(func ID: 0x80000009) is supposed to be handled by PSCI, that is,
the SoC/board specific reset implementation should be moved to PSCI.
U-Boot should call the PSCI service according to the arm-smccc
manner.The arm-smccc is supported on ARMv7 or later. Especially, ARMv8
generation SoCs are likely to run ARM Trusted Firmware BL31. In
this case, U-Boot is a non-secure world boot loader, so it should
not be able to reset the system directly.Signed-off-by: Masahiro Yamada
14 Apr, 2017
1 commit
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Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
05 Jan, 2017
1 commit
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Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.Signed-off-by: York Sun
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini
27 Sep, 2016
1 commit
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This version is based on the Marvell U-Boot version with this patch
applied as latest patch:Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
device mode" from 2016-07-05.Signed-off-by: Stefan Roese
Cc: Nadav Haklai
Cc: Kostya Porotchkin
Cc: Wilson Ding
Cc: Victor Gu
Cc: Hua Jing
Cc: Terry Zhou
Cc: Hanna Hawa
Cc: Haim Boot
22 Sep, 2016
1 commit
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Add missing Kconfig to fpga subsystem to be able
to add new options.Signed-off-by: Michal Simek
12 Aug, 2016
1 commit
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Create drivers/sysreset and move sysreset-uclass and all sysreset
drivers there.Signed-off-by: Max Filippov
Acked-by: Simon Glass
20 Jun, 2016
1 commit
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A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.Signed-off-by: Stephen Warren
Acked-by: Simon Glass
27 May, 2016
1 commit
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A mailbox is a hardware mechanism for transferring small message and/or
notifications between the CPU on which U-Boot runs and some other device
such as an auxilliary CPU running firmware or a hardware module.This patch defines a standard API that connects mailbox clients to mailbox
providers (drivers). Initially, DT is the only supported method for
connecting the two.The DT binding specification (mailbox.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.Signed-off-by: Stephen Warren
Acked-by: Simon Glass
19 Apr, 2016
1 commit
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Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig
entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on
platforms with AEMIF controller.Reported-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
02 Apr, 2016
1 commit
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Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass
22 Jan, 2016
1 commit
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Add a uclass that supports Pulse Width Modulation (PWM) devices. It
provides methods to enable/disable and configure the device.Signed-off-by: Simon Glass
02 Nov, 2015
1 commit
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This commit adds:
- new uclass id: UCLASS_ADC
- new uclass driver: drivers/adc/adc-uclass.cThe new uclass's API allows for ADC operation on:
* single-channel with channel selection by a number
* multti-channel with channel selection by bit maskADC uclass's functions:
* single-channel:
- adc_start_channel() - start channel conversion
- adc_channel_data() - get conversion data
- adc_channel_single_shot() - start/get conversion data
* multi-channel:
- adc_start_channels() - start selected channels conversion
- adc_channels_data() - get conversion data
- adc_channels_single_shot() - start/get conversion data for channels
selected by bit mask
* general:
- adc_stop() - stop the conversion
- adc_vdd_value() - positive reference Voltage value with polarity [uV]
- adc_vss_value() - negative reference Voltage value with polarity [uV]
- adc_data_mask() - conversion data bit maskThe device tree can provide below constraints/properties:
- vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1)
- vss-polarity-negative: if true: Vss = vss-microvolts * (-1)
- vdd-supply: phandle to Vdd regulator's node
- vss-supply: phandle to Vss regulator's node
And optional, checked only if the above corresponding, doesn't exist:
- vdd-microvolts: positive reference Voltage [uV]
- vss-microvolts: negative reference Voltage [uV]Signed-off-by: Przemyslaw Marczak
Cc: Simon Glass
Signed-off-by: Minkyu Kang
23 Oct, 2015
2 commits
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Implement a Timer uclass to work with lib/time.c.
Signed-off-by: Thomas Chou
Acked-by: Simon Glass -
Many System on Chip(SoC) solutions are complex with multiple processors
on the same die dedicated to either general purpose of specialized
functions. Many examples do exist in today's SoCs from various vendors.
Typical examples are micro controllers such as an ARM M3/M0 doing a
offload of specific function such as event integration or power
management or controlling camera etc.Traditionally, the responsibility of loading up such a processor with a
firmware and communication has been with a High Level Operating
System(HLOS) such as Linux. However, there exists classes of products
where Linux would need to expect services from such a processor or the
delay of Linux and operating system being able to load up such a
firmware is unacceptable.To address these needs, we need some minimal capability to load such a
system and ensure it is started prior to an Operating System(Linux or
any other) is started up.NOTE: This is NOT meant to be a solve-all solution, instead, it tries to
address certain class of SoCs and products that need such a solution.A very simple model is introduced here as part of the initial support
that supports microcontrollers with internal memory (no MMU, no
execution from external memory, or specific image format needs). This
basic framework can then (hopefully) be extensible to other complex SoC
processor support as need be.Reviewed-by: Simon Glass
Signed-off-by: Nishanth Menon
Acked-by: Simon Glass
31 Aug, 2015
4 commits
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This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
Sort different types of drivers in alphabetical order.
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Right now PHYS_TO_BUS shows in the Kconfig main menu, move it.
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Make "Generic Driver Options" menu show on the top in the Kconfig.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
22 Jul, 2015
3 commits
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Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.Signed-off-by: Simon Glass
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Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.Signed-off-by: Simon Glass
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Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass
26 Jun, 2015
1 commit
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Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.Remove the configs that behave this way from the archs.
A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:SPIFLASH
DISPLAY_BOARDINFOSigned-off-by: Joe Hershberger
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini
30 Apr, 2015
1 commit
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It is useful to be able to keep track of the available CPUs in a multi-CPU
system. This uclass is mostly intended for use with SMP systems.The uclass provides methods for getting basic information about each CPU.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
14 Apr, 2015
1 commit
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On some SoCs, DMA-capable peripherals see a different address space to
the CPU's physical address space. Create an API to allow platform-agnostic
drivers to convert between the two address spaces when programming DMA
operations.This API will exist on all platforms, but will have a dummy implementation
when this feature is not required. Other platforms will enable
CONFIG_PHYS_TO_BUS and provide the required implementation.Signed-off-by: Stephen Warren
13 Feb, 2015
2 commits
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Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.Signed-off-by: Simon Glass
Reviewed-by: Masahiro Yamada -
Add a suitable Kconfig for this directory.
Signed-off-by: Simon Glass
Reviewed-by: Masahiro Yamada
25 Sep, 2014
1 commit
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This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Tested-by: Simon Glass
