05 Mar, 2018
1 commit
-
Add entries for the R8A77965 M3N SoC.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
25 Feb, 2018
3 commits
-
The device-tree node for the PMU clk controller assigns to its parent
(i.e. PLL_PPLL) even though this clock currently is set up statically
by an init-function.In order to avoid unexpected failures, a simple implementation of
set_rate (which accepts requests, but notifies the caller of the
preset frequency in its return value) and get_rate (which always
returns the preset frequency) are added.Note that this is required for the RK808 PMIC to probe successfully on
the RK3399-Q7, following the support for the assigned-clocks property.References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()")
Signed-off-by: Philipp Tomsich
Tested-by: Klaus Goger -
Since commit ba1f96672522 ("net: designware: add clock support"), the
designware GMAC driver enables all referenced clocks. While this is a
no-op for the RK3368 during boot-up (reset behaviour has all the clock
gates open anyway), we still need to handle the clock-ids passed in
the enable op of the clock-driver and return a success.This change extends the RK3368 clk driver to:
(a) provide a enable op
(b) signals success to the caller when the clocks for the GMAC are
enabled (no actual action is necessary as the gates are open
after reset)References: commit ba1f96672522 ("net: designware: add clock support")
Signed-off-by: Philipp Tomsich
Tested-by: Klaus Goger -
Since commit ba1f96672522 ("net: designware: add clock support"), the
designware GMAC driver enables all referenced clocks. While this is a
no-op for the RK3399 during boot-up (reset behaviour has all the clock
gates open anyway), we still need to handle the clock-ids passed in
the enable op of the clock-driver and return a success.This change extends the enable-op of the rk3399 clk driver to signal
success to the caller when the clocks for the GMAC are enabled.References: commit ba1f96672522 ("net: designware: add clock support")
Signed-off-by: Philipp Tomsich
Tested-by: Klaus Goger
16 Feb, 2018
1 commit
-
The SD driver calls clk_set_rate() before clk_enable(), yet clk_set_rate()
implementation in the clock driver does not set the SD-IF divider. Fix it.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
30 Jan, 2018
1 commit
-
Since 'commit f4fcba5c5baa ("clk: implement clk_set_defaults()")'
STM32F4 family board can't boot.Above patch calls clk_set_rate() for all nodes with assigned-clock-rates
property. Clock driver for STM32F family doesn't implement .set_rate
callback which make clk_set_defaults() exit on error and prevent board
to boot.Fixes: f4fcba5c5baa ("clk: implement clk_set_defaults()")
Signed-off-by: Patrice Chotard
29 Jan, 2018
11 commits
-
The set_parent implementations do not make sense when OF_PLATDATA is
enabled. We guard these against OF_PLATDATA and don't populate the
set_parent-op when this is the case.Signed-off-by: Philipp Tomsich
-
Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.Signed-off-by: David Wu
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich -
The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.Signed-off-by: David Wu
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich -
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.Signed-off-by: David Wu
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich -
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.Signed-off-by: David Wu
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich -
The RK3399 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3399 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
simply ignore the set_rate() operation and return 0 to signal success.Signed-off-by: Philipp Tomsich
Tested-by: David WuSeries-changes: 2
- Fixed David's email address. -
Linux uses the properties 'assigned-clocks', 'assigned-clock-parents'
and 'assigned-clock-rates' to configure the clock subsystem for use
with various peripheral nodes.This implements clk_set_defaults() and hooks it up with the general
device probibin in drivers/core/device.c: when a new device is probed,
clk_set_defaults() will be called for it and will process the
properties mentioned above.Note that this functionality is designed to fail gracefully (i.e. if a
clock-driver does not implement set_parent(), we simply accept this
and ignore the error) as not to break existing board-support.Signed-off-by: Philipp Tomsich
Tested-by: David WuSeries-changes: 2
- Fixed David's email address.Series-version: 2
Cover-letter:
clk: support assigned-clock, assigned-clock-parents, assigned-clock-ratesFor various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC),
the parent-clock needs to be set via the DTS. This adds the required
plumbing and implements the GMAC case for the RK3399.
END -
This implements the (newly added) set_parent() operation for the
RK3399 with a focus on allowing the RGMII clock parent to be
configured via the assigned-clock-parents property of the GMAC node.This implementation supports only the GMAC (in fact only the RGMII
clock parent) and allows to set this clock's parent either to the
internal SCLK_GMAC or to an external clock input (identifiable by it
providing a 'clock-output-name' of "gmac_clkin").Signed-off-by: Philipp Tomsich
Tested-by: David WuSeries-changes: 2
- Fixed David's email address. -
The logic in clk_get_by_index() may be useful for other properties
than 'clocks': e.g. 'assigned-clocks' and 'assigned-clock-parents'
follows the same model.This commit refactors clk_get_by_index() by introducing an internal
function clk_get_by_indexed_prop() that allows to specify the name
of the property to process. The original clk_get_by_index() call
is simply directed through this helper function with the property
name fixed to "clocks".Signed-off-by: Philipp Tomsich
Tested-by: David WuSeries-changes: 2
- Fixed David's email address. -
Clocks may support multiple parents: this change introduces an
optional operation on the clk-uclass to set a clock's parent.Signed-off-by: Philipp Tomsich
Tested-by: David WuSeries-changes: 2
- Fixed David's email address.
28 Jan, 2018
5 commits
-
PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
00: PLLSAIP = 2
01: PLLSAIP = 4
10: PLLSAIP = 6
11: PLLSAIP = 8Previously, the divider value was incorrectly set to 6.
Signed-off-by: Patrice Chotard
-
Move SYSCFG clock setup into configure_clocks() instead of calling
clock_setup() from board file.As this clock is only needed in case of ethernet enabled and as
both stm32f4 and stm32f7 are using the Designware ethernet IP,
we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed.Move the RMII setup from board_early_init_f() to board_init()
to insure that RMII bit is set only when clock driver is initialized.Signed-off-by: Patrice Chotard
-
Thanks to 'commit ba1f96672522 ("net: designware: add clock support")'
we don't need anymore to setup the STMMAC clock in board.Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha -
All current STM32F4 supported boards uses a 8MHz external oscillator.
All current STM32F7 supported boards uses a 25MHz external oscillator.In order to introduce the new stm32f429-evaluation board which uses a
25MHz external oscillator without creating a dedicated struct
stm32_clk_info for this board, retrieve the external oscillator
frequency from DT and set pll_m accordingly to obtain 1MHz for the VCO.Signed-off-by: Patrice Chotard
26 Jan, 2018
1 commit
25 Jan, 2018
13 commits
-
Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux
kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Add common clock code for Renesas RCar Gen2 platforms.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Add macros for the DIV6P1 clock type, which is used on Gen2
and optionally also on Gen3.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Pull code which is common for RCar Gen2 and RCar Gen3 into
separate source file. No functional change.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Add Kconfig entries for each SoC clock table, so they can be
compiled in or out at build time. This can reduce the size of
the binary if desired.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this
is thus far always zero. Split the tables so the RMSTPCR can be set
too.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Extract the macros specific to Gen3 clock into a separate header.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Not all SoCs have the same PLL configuration options,
so make those PLL configuraion tables per-SoC.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Not all drivers use the same IDs, so make those IDs per-driver.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Split the massive driver into smaller per-SoC drivers and pull the
common code into a separate file. This would allow configuring out
unnecessary clock drivers once the Kconfig changes are in and also
allow adding more clock tables easily.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
24 Jan, 2018
1 commit
-
wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Jagan Teki
22 Jan, 2018
3 commits
-
The Makefile entries in the clk driver directory were not alphabetically
sorted. Correct this.Reviewed-by: Simon Glass
Signed-off-by: Mario Six -
The clk uclass was converted to support a live device tree recently,
hence the global data pointer declarations are no longer needed.Reviewed-by: Simon Glass
Signed-off-by: Mario Six -
Fix a mis-indented function call in clk_fixed_rate.c
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
