19 Feb, 2014
2 commits
11 Feb, 2014
1 commit
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Add a callback so that a board can implement it's own specific routine to
toggle the port's #PERST line or #define a GPIO to do so.Signed-off-by: Marek Vasut
06 Feb, 2014
1 commit
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The driver is no longer used, remove it.
Signed-off-by: Marek Vasut
Cc: Albert Aribaud
Cc: Michael Schwingen
Cc: Tom Rini
04 Feb, 2014
1 commit
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Current print only display width of PCIe device. Add print to display
PCIe generation supported by the device.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
26 Jan, 2014
1 commit
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Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.Signed-off-by: Marek Vasut
Cc: Albert Aribaud
Cc: Eric Nelson
Cc: Fabio Estevam
Cc: Stefano Babic
10 Nov, 2013
1 commit
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This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.Signed-off-by: Paul Burton
01 Nov, 2013
1 commit
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Signed-off-by: Masahiro Yamada
17 Oct, 2013
1 commit
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Previously, the address of a requested capability is define like that
"#define PCI_DCR 0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
1. Read Status register in PCIe configuration space to confirm that
Capabilities List is valid.
2. Find the address of Capabilities Pointer Register.
3. Find the address of requested capability from the first capability.Signed-off-by: Zhao Qiang
07 Oct, 2013
1 commit
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Forcibly set hose->pci_prefetch to NULL to make sure it will be setup.
This will help if for any reason callers didn't make sure themselves to
NULL the field.Signed-off-by: Thierry Reding
10 Aug, 2013
1 commit
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T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.1. Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.2. add the status/control register define
use status/control register to judge the link status3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.This patch fixes the PCIe card link up issue on T4240QDS.
Signed-off-by: Roy Zang
Signed-off-by: Minghuan Lian
Signed-off-by: York Sun
25 Jul, 2013
2 commits
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Signed-off-by: Tom Rini
24 Jul, 2013
4 commits
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Qemu emulates the Galileo GT64120 System Controller
which provides a CPU bus to PCI bus bridge.The patch adds driver for this bridge and enables
PCI support for the emulated Malta board.Signed-off-by: Gabor Juhos
Cc: Daniel Schwierzeck -
Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini -
Even though the header files is used only by the
pci_ftpci100 driver, it contains declaration for
a function which is used by external code.Move the header file to a common location which
lets external code use it.Compile tested only.
Cc: Macpaul Lin
Signed-off-by: Gabor Juhos -
The pci_ftpci_init() function is implemented
in 'drivers/pci/pci_ftpci100.c' however it is
always called by external code.Add function declaration into ftpci100.h to
make it visible for external code.Compile tested only.
Cc: Macpaul Lin
Signed-off-by: Gabor Juhos
21 Jun, 2013
1 commit
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Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.Signed-off-by: Liu Gang
Signed-off-by: Andy Fleming
08 Jun, 2013
1 commit
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The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.Also add the new option into the configuration
files of the boards which needs that.Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:powerpc:
--------------------- SUMMARY ----------------------------
Boards compiled: 641
Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
----------------------------------------------------------
Note: the warnings for ELPPC and MPC8323ERDB are present even
without the actual patch.x86:
--------------------- SUMMARY ----------------------------
Boards compiled: 1
----------------------------------------------------------arm:
--------------------- SUMMARY ----------------------------
Boards compiled: 311
----------------------------------------------------------nds32:
--------------------- SUMMARY ----------------------------
Boards compiled: 3
----------------------------------------------------------Cc: Tom Rini
Cc: Daniel Schwierzeck
Signed-off-by: Gabor Juhos
28 Nov, 2012
1 commit
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Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.Signed-off-by: Yuanquan Chen
Signed-off-by: Andy Fleming
23 Oct, 2012
3 commits
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Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.Signed-off-by: Liu Gang
Signed-off-by: Andy Fleming -
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1Signed-off-by: York Sun
Signed-off-by: Kumar Gala
Signed-off-by: Andy Fleming
Signed-off-by: Roy Zang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming -
Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT
not defined.Signed-off-by: York Sun
Signed-off-by: Andy Fleming
22 Oct, 2012
1 commit
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The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is EP or RC mode.Signed-off-by: Minghuan Lian
Signed-off-by: Andy Fleming
26 Sep, 2012
1 commit
22 Sep, 2012
1 commit
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The following commit introduced some warnings associated with using
pci_addr_t instead of a proper 32-bit data type.commit af778c6d9e2b945ee03cbc53bb976238a3374f33
Author: Andrew Sharp
Date: Wed Aug 1 12:27:16 2012 +0000pci: fix errant data types and corresponding access functions
On some platforms pci_addr_t is defined as a 64-bit data type so its not
proper to use with pci_{read,write}_config_dword.Signed-off-by: Kumar Gala
02 Sep, 2012
4 commits
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Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a
quick enumberation of the PCI devices, but don't need any setup work done.
This is very beneficial on platforms that have u-boot loaded by another
boot loader which does a more sophisticated job of setup of PCI devices
than u-boot. That way, u-boot can just read what's there and get on
with life. This is what SeaBIOS does.Signed-off-by: Andrew Sharp
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Refactor the common PCI code just a tiny bit surrounding the PCI_PNP
(pciauto) stuff. Makes the code a tiny bit easier to read, and also
makes it more obvious that almost no platform needs to setup or use the
pci_config_table stuff.Signed-off-by: Andrew Sharp
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I tried to clean up the white space and formatting offenses and
inconsistencies in the generic PCI code that obviously has been around for
some time. Emphasis on large increases in readability and maintainability
and consistency. I omitted the platform/processor specific files in
the drivers/pci directory because I wanted to leave those file to those
that care more about them.Signed-off-by: Andrew Sharp
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In a couple of places, unsigned int and pci_config_*_dword were being
used when u16 and _word should be used. Unsigned int was also being
used in a couple of places that should be pci_addr_t.Signed-off-by: Andrew Sharp
23 Aug, 2012
1 commit
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For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.Environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.For the master module, need to finish these processes:
1. Initialize the PCIE port and address space.
2. Set inbound PCIE windows covered slave's u-boot image stored in
master's NOR flash.
3. Set outbound windows in order to configure slave's registers
for the core's releasing.
4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
or "PCIE3" using the following command:setenv bootmaster PCIE1
saveenvSigned-off-by: Liu Gang
Signed-off-by: Andy Fleming
31 Mar, 2012
1 commit
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The FSL PCI driver uses local prototypes for
pciauto_[pre|post]scan_setup_bridge(), this does not seem right,
so move them to the file.Fixed a small extern declaration too, this is harmless but distracts
the view since all other prototypes are explicitly external.Signed-off-by: Linus Walleij
05 Mar, 2012
1 commit
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Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.Reported-by: Wolfgang Denk
Signed-off-by: Linus Walleij
06 Dec, 2011
1 commit
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FTPCI100 is a SoC PCI componenet of Faraday company.
Which is usually built into SoC chips for providing
embedded PCI functions.Signed-off-by: Gavin Guo
Signed-off-by: Macpaul Lin
28 Oct, 2011
1 commit
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fsl_pci_init.c: In function 'fsl_pci_init':
fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but
argument 6 has type 'long unsigned int'
fsl_pci_init.c:347: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'volatile u32 *'fsl_pci_init.c: In function 'fsl_pci_init':
fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned
int', but argument 4 has type 'pci_addr_t'
fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned
int', but argument 5 has type 'pci_size_t'
fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but
argument 6 has type 'long unsigned int'Signed-off-by: Marek Vasut
Cc: Wolfgang Denk
Cc: Simon Glass
Cc: Mike Frysinger
16 Oct, 2011
1 commit
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PCI cards might need some time after reset to respond. On some
boards (mpc5200 or mpc8260 based) the PCI bus reset is deasserted
at pci_init_board() time, so we currently can not use available
"pcidelay" option for waiting before PCI bus scan since this
waiting takes place before calling pci_init_board(). By moving
the pcidelay code to the new location using of the "pcidelay"
option is possible on mpc5200 or mpc8260 based boards, too.Since pci_hose_scan() could be called multiple times, restrict
the function to wait only during its first call and to ignore
pcidelay for any further call (as pointed out by Matthias).Signed-off-by: Anatolij Gustschin
Cc: Matthias Fuchs
Acked-by: Stefan Roese
Acked-by: Matthias Fuchs
Tested-by: Matthias Fuchs
29 Jul, 2011
1 commit
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Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/addressSigned-off-by: Mike Williams
23 Jun, 2011
1 commit
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clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc.
code and use u-boot's PCI infrastructure instead. Move board-specific PCI
setup code (clock/reset) to board directory.Signed-off-by: Michael Schwingen
04 Apr, 2011
1 commit
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FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.xAdded new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status registerAdded new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala
29 Mar, 2011
1 commit
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The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala