16 Nov, 2017

1 commit


01 Feb, 2017

1 commit

  • Armada 38x has four PCI ports, not three.

    The optimization in pci_init_board() seems to assume that every port has
    three lanes. This is obviously wrong, and breaks support for Armada 38x.

    Signed-off-by: Dirk Eibach
    Signed-off-by: Mario Six
    Reviewed-by: Stefan Roese
    Signed-off-by: Stefan Roese

    Dirk Eibach
     

24 Sep, 2016

1 commit


14 Jan, 2016

1 commit

  • Armada XP has support for X4 lanes, boards specify this in their
    serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration
    is stored in GEN_PURP_RES_2_REG.

    When enumerating PEX, subsequent interfaces of an X4 lane must be
    skipped. Otherwise the enumeration hangs up the board.

    The way this is implemented here is not exactly beautiful, but it mimics
    how Marvell's BSP does it. Alternatively we could get the information
    using board_serdes_cfg_get(), but that won't lead to clean code, either.

    Signed-off-by: Phil Sutter
    Acked-by: Stefan Roese
    Reviewed-by: Tom Rini

    Phil Sutter
     

18 Aug, 2015

1 commit

  • This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.

    Besides the driver, this patch also removes the statically defined
    PCI MBUS windows. As they are not needed anymore, since this PCIe
    driver now creates the windows dynamically.

    Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
    PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
    eval board using this Intel E1000 PCIe card in the PCIe 0 slot.

    This port was done in cooperation with Anton Schubert.

    Signed-off-by: Anton Schubert
    Signed-off-by: Stefan Roese
    Cc: Luka Perkov
    Cc: Dirk Eibach

    Anton Schubert