16 Aug, 2018
1 commit
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Enable TZASC on i.MX 8mm.
There is a need on 8MM to enable
the BYPASS ID SWAP bit (GPR10 bit 1) in order
for GPU not to generated AXI bus errors.Signed-off-by: Silvano di Ninno
Reviewed-by: Peng Fan
15 Aug, 2018
3 commits
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enable fastboot for i.MX8MM flexspi u-boot
Signed-off-by: Han Xu
(cherry picked from commit ea221c08862666926e613f649359905400773d9c)
Signed-off-by: Ye Li -
Update AHAB codes to use container image related structures in image.h
Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
Add relevant functions and files to parse the container image set from mmc/sd
and get the total size of it. So we can get the offset of u-boot-atf.bin image
when it is padded to container image set at 1KB alignment position.Signed-off-by: Ye Li
13 Aug, 2018
1 commit
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This is debug patch, pushed by mistake. Since we already support
DDR3 ARM2 in previous commit, must revert it.This reverts commit d0602d2ee64c9ad2bf38a38bfb84f8ff9ac9b68d.
Signed-off-by: Ye Li
11 Aug, 2018
4 commits
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In file included from arch/arm/mach-imx/imx8m/soc.c:11:0:
arch/arm/mach-imx/imx8m/soc.c: In function ‘imx_gpc_set_m_core_pgc’:
./arch/arm/include/asm/io.h:44:28: warning: cast to pointer from integer of differen t size [-Wint-to-pointer-cast]
#define __arch_getl(a) (*(volatile unsigned int *)(a))
^
./arch/arm/include/asm/io.h:122:31: note: in expansion of macro ‘__arch_getl’
#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
^~~~~~~~~~~
arch/arm/mach-imx/imx8m/soc.c:427:8: note: in expansion of macro ‘readl’
val = readl(GPC_BASE_ADDR + offset);
^~~~~
./arch/arm/include/asm/io.h:49:29: warning: cast to pointer from integer of differen t size [-Wint-to-pointer-cast]
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
^
./arch/arm/include/asm/io.h:117:48: note: in expansion of macro ‘__arch_putl’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
^~~~~~~~~~~
arch/arm/mach-imx/imx8m/soc.c:432:2: note: in expansion of macro ‘writel’
writel(val, GPC_BASE_ADDR + offset);
^~~~~~
arch/arm/mach-imx/imx8m/soc.c: In function ‘imx8m_usb_power’:
arch/arm/mach-imx/imx8m/soc.c:453:16: warning: unused variable ‘ret’ [-Wunused-varia ble]
unsigned long ret;
^~~Signed-off-by: Li Jun
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enable fastboot for i.MX8QX MEK FlexSPI u-boot
Signed-off-by: Han Xu
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When rewoked eMMC to MMC socket, change MMC driver can recognize the card
Enable the fastboot to test usb gadgetSigned-off-by: Ye Li
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Enable DWC3 USB support at i.MX850D platform
Signed-off-by: Frank Li
10 Aug, 2018
7 commits
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Add new dts, config and defconfig file for DX DDR3 ARM2 board. Since
it does not have USB3.0 and SD, disable them in DTS and header file. Also move
gpio expander to i2c1 according with its schematic.In defconfig, fastboot is default enabled due to we need uuu to program
eMMC.Signed-off-by: Ye Li
(cherry picked from commit e5b822615a5aa2fadb481002c286f35d996999f8) -
By default, imx8qm/qxp b0 silicon set the IO voltage to 2.5v, but mek/arm2
boards are designed as 1.8v voltage for enet IO, so force the IO voltage
to 1.8 by setting COMP_CTL_GPIO_1V8_3V3 pins like:
The pin setting:
1.8V/3.3V : bit4=0, bit[30]=1, bit[2:0]=000
2.5V : bit4=1, bit[30]=1, bit[2:0]=010Reviewed-by: Ye Li
Signed-off-by: Fugang Duan -
Enable SPL support for iMX8QM ARM2 boards
Signed-off-by: Teo Hall
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There is not needed for this in SPL.
Signed-off-by: Abel Vesa
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Do not build the imx_bootaux if the build is SPL when building for imx8.
Signed-off-by: Abel Vesa
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This will allow iMX8QX to have SPL support and later on the iMX8QM too.
Signed-off-by: Abel Vesa
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Now that iMX8QX and iMXQM will have SPL support, the socs list that support it
has to be updated. Instead of building 8m only build for all imx8.Signed-off-by: Abel Vesa
06 Aug, 2018
3 commits
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Refact the lpddr4 init flow on i.MX8MM EVK board. board level only need
to provide the necessary dram init related parameter.Signed-off-by: Bai Ping
(cherry picked from commit 72a06ef47c7c93de49730261adb8f251612d1883) -
the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.the same method can be use for DDR4. will be added later.
Signed-off-by: Bai Ping
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1) -
Still meet DPLL unstable issue on iMX8QXP B0 when doing various stress tests.
So switch back to use AVPLL for usdhc on B0Signed-off-by: Ye Li
(cherry picked from commit 099ddce37cf3100d0aeb0964db7b24e5a59ee1d0)
03 Aug, 2018
2 commits
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CONFIG_STACKSIZE is removed, so when enable CONFIG_CMD_BEE
there will be build failure.The previous CONFIG_STACKSIZE value is 128KB, so replace
CONFIG_STACKSIZE with SZ_128KB in bee.c to avoid build error.Signed-off-by: Peng Fan
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Signed-off-by: Shenwei Wang
Acked-by : Frank Li
01 Aug, 2018
2 commits
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i.MX6SLL boards enable fastboot as default.
Support: mx6sllevk_defconfig
mx6sllevk_epdc_defconfig
mx6sllevk_optee_defconfig
mx6sllevk_plugin_defconfig
uuu will use fastboot command to write emmc.Signed-off-by: Xiaoning Wang
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Base on MLK-18406: uuu write to any positionn of mmc
Support i.MX6 boards.Signed-off-by: Xiaoning Wang
28 Jul, 2018
1 commit
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Set the alert temperature = critical temperature - 20C, to avoid looping
the temperature at 85CSigned-off-by: Ye Li
(cherry picked from commit d4ccaa7c87576a5a9a246ee89a627dd8efd8ae07)
26 Jul, 2018
1 commit
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The check to HAB closed fuse (SEC_CONFIG[1]) on iMX8M platforms is
missed when addressing cherry-pick conflict to 2018 for commit
465407632f436cb55db1d261ee0adb7458220045Signed-off-by: Ye Li
20 Jul, 2018
4 commits
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After moving TRNG init to U-Boot/SPL for all boards, some i.MX6 boards
SL, SLL and ULL failed to boot.
These boards do not have CAAM.
This patch disable TRNG init for these three boards.Signed-off-by: Aymen Sghaier
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According to RM, usdhc 100MHz pad setting need to set SRE(slew rate
field) to 0x01(Medium Frequency Slew Rate 100MHz), usdhc 200MHz pad
setting need to set SRE to 0x11(Max Frequency Slew Rate 200MHz).Signed-off-by: Haibo Chen
(cherry picked from commit 9d19a3627124ff4d61e62d3031777b6041c07810) -
Add board level codes for enabling splash screen on imx8mm EVK. We
support two different display connecting to MIPI DSI miniSAS interfaces:1. MIPI2HDMI daughter card (default)
2. RM67191 OLED panelUsers can set "panel" env vairable to "MIPI2HDMI" or "RM67191_OLED" to
switch them after reboot.Signed-off-by: Ye Li
(cherry picked from commit 41f896ce26aa0f518b5cacb1d9660a0a085ee691) -
Enable the video PLL (594Mhz) and clocks in displaymix. Add the LCDIF clock
set interface to change its dot clock rate.
Update registers header file for LCDIF base address.Signed-off-by: Ye Li
(cherry picked from commit 3c27bc4bfa35dbebee2b5797c9137a2257946eca)
17 Jul, 2018
1 commit
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Call the TRNG init function at the end of arch_cpu_init()
Concerned SoCs are: i.MX6, i.MX7 and i.MX8MSigned-off-by: Aymen Sghaier
16 Jul, 2018
4 commits
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uuu can change emmc device number for fastboot
Signed-off-by: Frank Li
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We enabled the DM for xhci-imx8m driver which uses compatible string
"fsl, imx8mq-dwc3". But found a issue that u-boot will get four USB bus not two.
The reason is the low level driver xhci-dwc3 also adds the DM support which uses
compatible string "snps,dwc3". Thus, one USB node and its dwc3 subnode are both
binded as independent USB bus.Since the xhci-imx8m driver uses xhci-dwc3 as low level driver, to fix the issue
we add -u-boot.dtsi files to change the USB node compatible string to
"simple-bus" and change dwc3 node compatibe string to "fsl, imx8mq-dwc3". Then
xhci-dwc3 DM driver won't bind any node.Signed-off-by: Ye Li
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Checks whether the HDMI FW is running before initialize the HDMI display.
So that for cases like mfgtool and imx-boot image without HDMI FW, the
u-boot won't be blocked.Signed-off-by: Ye Li
(cherry picked from commit 273b45dd3cf8773462400857c8b48b70bcfe96bb) -
Get such warning below in fuse driver, due to a u32 pointer is converted to ulong then
passed as ulong pointer.
This is dangerous when assigning value to the memory where ulong pointer points to.
So use a intermediate variable to hand over value. Also fix the indenting issue in this patch.arch/arm/cpu/armv8/imx8/fuse.c: In function ‘fuse_sense’:
arch/arm/cpu/armv8/imx8/fuse.c:33:25: warning: passing argument 3 of ‘call_imx_sip_ret2’
makes pointer from integer without a cast [-Wint-conversion]
(unsigned long)val, 0, 0);
^
In file included from ./arch/arm/include/asm/arch/sys_proto.h:7:0,
from arch/arm/cpu/armv8/imx8/fuse.c:13:
./arch/arm/include/asm/imx-common/sys_proto.h:94:15: note: expected ‘long unsigned int *’
but argument is of type ‘long unsigned int’
unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, unsigned long *reg1,
unsigned long reg2, unsigned long reg3);Signed-off-by: Ye Li
(cherry picked from commit 8c9f2dbf90c7908c5df1ac3727e8c177c8809240)
15 Jul, 2018
1 commit
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The API to get the value of environment variable is not
correct, use correct API. This fix the build errors like
below:
arch/arm/mach-imx/built-in.o: In function `mmc_get_env_dev':
uboot-imx/arch/arm/mach-imx/imx8/cpu.c:840:
undefined reference to `get_env_ulongTest: Build pass for imx8qm/imx8qxp.
Change-Id: I4fa65d1cd808ec6a737c419b278fce9cce2b1e7b
Signed-off-by: Luo Ji
14 Jul, 2018
1 commit
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uuu can write to any position of mmc
sdps: boot -f ../mkimage_imx8dv/imx-mkimage/iMX8QX/flash.binFB: ucmd setenv fastboot_dev mmc
FB: ucmd setenv mmcdev ${emmc_dev}
FB: ucmd mmc dev ${emmc_dev}
FB: flash -raw2sparse all xx.sdcardSigned-off-by: Frank Li
(cherry picked from commit ca96e0bd1aea1996904b0a71fb1d74c3f5176929)Conflicts:
arch/arm/cpu/armv8/imx8/cpu.c
drivers/usb/gadget/f_fastboot.c
include/configs/imx8qxp_mek.h
12 Jul, 2018
1 commit
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In optee enabled defconfig, the trust zone is enabled in DCD. On iMX6UL/ULL, there
is IC limitation that LCDIF master access can only be non-secure, because PL301
hard code the m_3/4/5 to non-secure masters. It causes LCDIF fails to fetch data
from memory.This patch adds a workaround to change trust zone Region 0 attribute to allow both secure
and non-secure read/write. So it permits the LCDIF master access to memory.
Since optee will configure Region 0 by itself, this should not introduce problem to optee.Signed-off-by: Ye Li
(cherry picked from commit 85be73bb5bab319c096f0893729835b3ceddafde)
11 Jul, 2018
1 commit
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The bootaux from community uses ulong to read private data and write to M4 TCM,
this cause problem on ARM64 platform where the ulong is 8bytes.
Fix it by using u32 to replace ulong.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
06 Jul, 2018
1 commit
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According to ADD, the target frequency for NOC bus clock is 750Mhz,
the default setting from ROM is selecting the PLL1_800M_clk as source.
This patch sets the PLL3 to 750Mhz and select it as the source of NOC
clock root.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit dc53b0d89b044e387779d4751dd4c7d3bfe0d0a9)
04 Jul, 2018
1 commit
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Modify the fuse subsystem to add a SMC call
for writing/reading to the OTP memory.Signed-off-by: Teo Hall