21 Aug, 2013

1 commit

  • 85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
    because of this code checkpatch script generates "WARNING: Avoid CamelCase".

    Convert variables name to normal naming convention and modify board, driver
    files with updated the new structure.

    Signed-off-by: Prabhakar Kushwaha
    Acked-by: York Sun

    Prabhakar Kushwaha
     

23 Oct, 2012

1 commit


25 Sep, 2009

1 commit


29 Aug, 2009

1 commit

  • The number of CPUs are getting detected dynamically by checking the
    processor SVR value. Also removed CONFIG_NUM_CPUS references from all
    the platforms with 85xx/86xx processors.

    This can help to use the same u-boot image across the platforms.

    Also revamped and corrected few Freescale Copyright messages.

    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Kumar Gala

    Poonam Aggrwal
     

13 Jun, 2009

1 commit


24 Jan, 2009

1 commit


20 Dec, 2008

1 commit

  • Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
    and print it out, but don't save it.

    This changes where its calculated and stored to be more consistent with the
    CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.

    The localbus frequency is added to sysinfo and calculated when sysinfo is
    set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.

    get_clocks() copies the frequency into the global data, as the other
    frequencies are, into a new field that is only enabled for MPC85xx and
    MPC86xx.

    checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
    from sysinfo, like the other frequencies, instead of calculating it on the
    spot.

    Signed-off-by: Trent Piepho
    Acked-by: Kumar Gala
    Acked-by: Jon Loeliger

    Trent Piepho
     

10 Jan, 2008

2 commits


12 Dec, 2007

1 commit


02 Aug, 2004

1 commit

  • - support larger DDR memories up to 2G on the PC8540/8560ADS and
    STXGP3 boards
    - Made MPC8540/8560ADS be 33Mhz PCI by default.
    - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
    and CONFIG_L2_INIT_RAM options.
    - Refactor Local Bus initialization out of SDRAM setup.
    - Re-implement new version of LBC11/DDR11 errata workarounds.
    - Moved board specific PCI init parts out of CPU directory.
    - Added TLB entry for PCI-1 IO Memory
    - Updated README.mpc85xxads

    wdenk
     

16 Oct, 2003

1 commit