24 Jan, 2018

1 commit

• 15a70a5da   spi: cadence_spi: Sync DT bindings with Linux ... Browse Code »

  Adopt the Linux DT bindings. This also fixes an issue
  with the indaddrtrig register on the Cadence QSPI
  device being programmed with the wrong value for the
  socfpga arch.

  Tested on TI K2G platform:
  Tested-by: Vignesh R

  Tested on a socfpga-cyclonev board:
  Tested-by: Simon Goldschmidt

  Signed-off-by: Jason Rush
  Reviewed-by: Jagan Teki
  Acked-by: Simon Goldschmidt
  Acked-by: Marek Vasut

  Jason Rush

  2018-01-24 14:37:50 +0800  

08 Feb, 2017

1 commit

• e160f7d43   dm: core: Replace of_offset with accessor ... Browse Code »

  At present devices use a simple integer offset to record the device tree
  node associated with the device. In preparation for supporting a live
  device tree, which uses a node pointer instead, refactor existing code to
  access this field through an inline function.

  Signed-off-by: Simon Glass

  Simon Glass

  2017-02-08 21:12:14 +0800  

15 Dec, 2016

2 commits

• 6d72810c6   spi: cadence_qspi: Move DT prop code to match layout ... Browse Code »

  Move the code to read the "sram-size" property into the other code
  that reads properties from the node, rather than the SF subnode.

  Signed-off-by: Phil Edworthy
  Reviewed-by: Jagan Teki

  Phil Edworthy

  2016-12-15 23:57:28 +0800  
• 7d403f284   spi: cadence_qspi: Use spi mode at the point it is needed ... Browse Code »

  Instead of extracting mode settings and passing them as separate
  args to another function, just pass the SPI mode as an arg.

  Signed-off-by: Phil Edworthy
  Reviewed-by: Jagan Teki

  Phil Edworthy

  2016-12-15 23:57:27 +0800  

24 Sep, 2016

1 commit

• 1221ce459   treewide: replace #include <asm/errno.h> with <linux/errno.h> ... Browse Code »

  Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
  the same content. (both just wrap )

  Replace all include directives for with .

  Signed-off-by: Masahiro Yamada
  [trini: Fixup include/clk.]
  Signed-off-by: Tom Rini

  Masahiro Yamada

  2016-09-24 05:55:42 +0800  

22 Sep, 2016

1 commit

• 08fe9c294   spi: Use mode for rx mode flags ... Browse Code »

  Make rx mode flags as generic to spi, earlier mode_rx is
  maintained separately because of some flash specific code.

  Cc: Simon Glass
  Cc: Bin Meng
  Cc: Michal Simek
  Cc: Siva Durga Prasad Paladugu
  Cc: Vignesh R
  Cc: Mugunthan V N
  Signed-off-by: Jagan Teki

  Jagan Teki

  2016-09-22 03:32:28 +0800  

09 Jul, 2016

1 commit

• 2372e14f1   spi: cadence_quadspi: Enable QUAD mode based on DT data ... Browse Code »

  Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
  mode, make use of mode_rx field of dm_spi_slave_platdata to determine
  whether to enable or disable QUAD mode. This is necessary to support
  muliple SPI controllers where one of them may not support QUAD mode.

  Signed-off-by: Vignesh R
  Tested-by: Marek Vasut
  Acked-by: Marek Vasut
  Reviewed-by: Jagan Teki

  Vignesh R

  2016-07-09 22:46:33 +0800  

05 Nov, 2015

3 commits

• 4e609b6cb   spi: cadence_qspi: Ensure check for max frequency in place ... Browse Code »

  Ensure the intended SCLK frequency not exceeding the maximum
  frequency. If that happen, SCLK will set to maximum frequency.

  Signed-off-by: Chin Liang See
  Cc: Dinh Nguyen
  Cc: Dinh Nguyen
  Cc: Marek Vasut
  Cc: Stefan Roese
  Cc: Vikas Manocha
  Cc: Jagannadh Teki
  Cc: Pavel Machek
  Acked-by: Pavel Machek

  Chin Liang See

  2015-11-05 09:34:15 +0800  
• 040f4ba74   spi: cadence_qspi: Fix fdt read of spi-max-frequency ... Browse Code »

  Fix the fdt read for spi-max-frequency as it's contained
  in the child node. Current state of code is always
  returning default value.

  Signed-off-by: Chin Liang See
  Cc: Dinh Nguyen
  Cc: Dinh Nguyen
  Cc: Marek Vasut
  Cc: Stefan Roese
  Cc: Vikas Manocha
  Cc: Jagannadh Teki
  Cc: Pavel Machek
  Acked-by: Marek Vasut
  Acked-by: Pavel Machek

  Chin Liang See

  2015-11-05 09:34:15 +0800  
• 98fbd71d7   spi: cadence_qspi: Ensure spi_calibration is run when sclk change ... Browse Code »

  Ensuring spi_calibration is run when there is a change of sclk
  frequency. This will ensure the qspi flash access works for high
  sclk frequency

  Signed-off-by: Chin Liang See
  Cc: Dinh Nguyen
  Cc: Dinh Nguyen
  Cc: Marek Vasut
  Cc: Stefan Roese
  Cc: Vikas Manocha
  Cc: Jagannadh Teki
  Cc: Pavel Machek
  Acked-by: Marek Vasut
  Reviewed-by: Jagan Teki

  Chin Liang See

  2015-11-05 09:34:15 +0800  

03 Jul, 2015

1 commit

• 90a2f7171   spi: cadence_qspi: get sram size from device tree ... Browse Code »

  sram size could be different on different socs, e.g. on stv0991 it is 256 while
  on altera platform it is 128. It is better to receive it from device tree.

  Signed-off-by: Vikas Manocha
  Tested-by: Stefan Roese
  Reviewed-by: Jagannadh Teki

  Vikas Manocha

  2015-07-03 16:20:53 +0800  

30 Jan, 2015

1 commit

• 19a25f672   dm: spi: Move the per-child data size to the uclass ... Browse Code »

  This is common to all SPI drivers and specifies a structure used by the
  uclass. It makes more sense to define it in the uclass.

  Reviewed-by: Masahiro Yamada
  Signed-off-by: Simon Glass

  Simon Glass

  2015-01-30 08:09:55 +0800  

07 Jan, 2015

1 commit

• 1dc7d00f2   spi: cadence_qspi: Fix checking return value of fdt_first_subnode() ... Browse Code »

  fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found.
  0 is supposed to be a valid offset returns from fdt_first_subnode().

  Signed-off-by: Axel Lin
  Reviewed-by: Jagannadha Sutradharudu Teki

  Axel Lin

  2015-01-07 15:00:54 +0800  

06 Dec, 2014

1 commit

• 10e8bf88c   spi: Add Cadence QSPI DM driver used by SoCFPGA ... Browse Code »

  This driver is cloned from the Altera Rockerboard.org U-Boot
  repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
  modification to support the U-Boot driver model (DM).

  As mentioned above, in this new version I ported this driver to the
  new driver model (DM). One big advantage of this move is that now
  multiple SPI drivers can be enabled on one platform. And since the
  SoCFPGA also has the Designware SPI master controller integrated,
  this feature is really needed to support both controllers.

  Because of this, this series needs the DT support for SoCFPGA
  to be applied. For DT based probing in the SPI DM.

  Signed-off-by: Stefan Roese
  Cc: Chin Liang See
  Cc: Dinh Nguyen
  Cc: Vince Bridgers
  Cc: Marek Vasut
  Cc: Pavel Machek
  Cc: Simon Glass
  Cc: Jagannadha Sutradharudu Teki

  Stefan Roese

  2014-12-06 20:52:46 +0800