09 Nov, 2020
1 commit
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Make sure are RGMII internal delay modes are covered.
Signed-off-by: Madalin Bucur
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
15 Jan, 2016
1 commit
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With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.Simple uses of sprintf are also converted to use strcpy.
Signed-off-by: Ben Whitten
Acked-by: Wolfgang Denk
Reviewed-by: Tom Rini
30 Oct, 2015
1 commit
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The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
Reviewed-by: York Sun
06 Dec, 2014
2 commits
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BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains
selection bits and connected status bit. So the Corresponding mux
value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN.Signed-off-by: Minghuan Lian
Signed-off-by: Shaohui Xie
Reviewed-by: York Sun -
The new device trees use a more generic interface for
supporting muxing mdio buses. The mux property is thus
specified in "reg", rather than "fsl,hydra-mdio-muxval".In order to support using old device trees, we keep the
old fixup in there. Linux will therefore see the both
properties, but will ignore fsl,hydra-mdio-muxval.Signed-off-by: Chunhe Lan
Reviewed-by: York Sun
17 Oct, 2013
1 commit
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Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
1. Confirm whether QSGMII Riser Card is used.
2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.Signed-off-by: Zhao Qiang
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
08 Nov, 2011
1 commit
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TBI PHY address (TBIPA) register has been set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.cSo remove the duplicate code on QorIQ frame manager Ethernet related
platforms, which include Hydra board, P4080DS board and P2041rdb board.Signed-off-by: Roy Zang
Cc: Andy Fleming
Signed-off-by: Kumar Gala
18 Oct, 2011
1 commit
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Add common function fdt_set_node_status() to assist in various locations
that we set a nodes status. This function utilizes the status values
that are part of the EPAPR spec (on power.org).fdt_set_status_by_alias() is based on fdt_set_node_status() but uses an
alias string to identify the node to update.We also add some shortcut functions to help the common cases of setting
"okay" and "disabled":fdt_status_okay()
fdt_status_disabled()
fdt_status_okay_by_alias()
fdt_status_disabled_by_alias()Finally, we fixup the corenet_ds ethernet code which previously had
a function by the same name that can be replaced with the new helpers.Signed-off-by: Shengzhou Liu
Signed-off-by: Kumar Gala
Acked-by: Gerald Van Baren
30 Sep, 2011
1 commit
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Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS &
P5020DS ("Hydra").The lane_to_slot[] array is initialized dynamically, since board switches
can be used to control the muxing of SERDES lanes to slots.The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate
slot. The SERDES configuration is queried to help determine the routing
between MACs and slot/phy combination.If a XAUI card is inserted, muxing for that card is enabled and never
turned off. The PHY address for the 10G XAUI card depends on the slot in
which it's inserted. If it's in slot 1, the address is 4. If it's in
slot 2, the address is 0.Update the MDIO routing in the P3041DS and P5020DS device trees based on
the board-level muxing. The SERDES configuration determines which
SGMII/XGMII boards are located in which slots, and so the MDIO bus needs
to be muxed correctly whenever talking to a PHY connected to any Fman MAC.
The Fman Ethernet nodes in the device tree also need to be routed to the
correct PHYs.Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Ioana Radulescu
Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming
Signed-off-by: Kumar Gala
