04 Mar, 2016
11 commits
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Need the CONFIG_MX6 for using the mx6_ecspi_fused funtion, otherwise will
break build for other platforms like MX7.Signed-off-by: Ye Li
(cherry picked from commit 9433975cef6a5aef3ff4709ebe68ba97f78740f0) -
Some type style problems found by review-commits for previous patch
MLK-12483, fix them in this patch and re-check.Signed-off-by: Ye Li
(cherry picked from commit 8ada91778f7f28dd33b80f515a35d09c1398933c) -
Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF.Signed-off-by: Ye Li
(cherry picked from commit 61789a160ae023ba6f7d37da74be957d22505736) -
The list_first_entry always assumes the list is not empty, it won't return NULL pointer when
the list is empty. So the "if (pdesc == NULL)" becomes a dead code. Fix the issue by calling
the list_empty before the list_first_entry.(Coverity CID 29934)
Signed-off-by: Ye.Li
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Fix a read from pointer after free issue in nand error handling path,
which was found by coverity.Signed-off-by: Han Xu
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unsigned long long data might have strange data if first bit of u8 data
was 1. this patch cast it to (unsigned long long)ex)
u8 data8;
u64 data64;data8 = 0x80;
data64 = (data8 << 24); // 0xffffffff80000000
data64 = (((unsigned long long)data8) << 24); // 0x80000000;(reported by Coverity)
Signed-off-by: Haibo Chen
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Introudce wp_enable. If want to check WPSPL, then in board code,
need to set wp_enable to 1.Take i.MX6UL for example, to some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.Suggested-by: Ye.Li
Signed-off-by: Peng Fan -
We can rely on finish bit for temperature reading for TO1.1.
Also introduce CHIP_REV_xx macros for 7D.Signed-off-by: Peng Fan
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Clear DLL_CTRL delay line settings at USDHC initialization to eliminate the
pre-settings from boot rom. U-boot should re-init the USDHC not reply on the
value set by boot from.On MX6DL, the ROM has set the default delay line(DLLCTRL) to 0x1000021,
when eMMC works on DDR mode in kernel, it will possibly cause data CRC errors.
Even u-boot always use eMMC in SDR mode, for safety sake, it is better to clear it too.Signed-off-by: Ye.Li
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By Coverity check, the clk_set_rate function dereferences the clk pointer
without checking whether it is NULL. This may cause problem when clk is NULL.
Fix the problem by adding NULL check.Signed-off-by: Ye.Li
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We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2].
If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds
the size of stp_rep array.Acked-by: Liu Ying
Signed-off-by: Peng Fan
06 Nov, 2015
1 commit
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The fastboot.exe will get var partition-type:* firstly when "fastboot flash * *".
The uboot did not support get var partition-type: default.
This patch mask info the error when gat cat partition-type.Signed-off-by: zhang sanshan
04 Nov, 2015
1 commit
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The ci_udc driver tries to use the ULPI interface for the USB OTG controller,
but this type is not supported by all i.MX6 and i.MX7 platforms. When setting to
ULPI, other platforms except the 6UL refuse the settings and keep default value.
But on 6UL, the PTW bit of PORTSC1 register which is documented as RO can change.
This cause the interface setting problem with USB PHY.Fix the issue by removing the ULPI setting for i.MX6 and i.MX7. All will use default
UTMI setting.Signed-off-by: Ye.Li
16 Oct, 2015
1 commit
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The cod change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes).Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.Signed-off-by: Han Xu
28 Aug, 2015
1 commit
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CONFIG_FASTBOOT is not used, since we have CONFIG_FSL_FASTBOOT and
CONFIG_CMD_FASTBOOT for fastboot. "drivers/fastboot" can be discarded.Signed-off-by: Peng Fan
03 Aug, 2015
2 commits
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Since setup_waveform_file in different boards code have same implementation,
move setup_waveform_file to board common code. Also rename it to
board_setup_waveform_fileThis patch also fix a bug when using flush_cache. We should pass
'waveform_buf' to flush_cache, but not a string named 'addr'.Signed-off-by: Peng Fan
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Support draw image on E-ink screen.
1. The image format should be PGM-P5 raw data format.
2. The image should be named epdc_logo.pgm.
3. If no epdc_logo.pgm found in the first partition(FAT), will choose
to draw black border on the screen.
4. Default configuration is to draw image at pos (0,0). If 'splashpos'
env is set, will choose the pos from 'splashpos'.
5. The image size should not be bigger than screen total pixel size.
6. Implement board_setup_logo_file in board/freescale/common/epdc_setup.c
7. Introudce function prototype for board_setup_logo_file.Note: i.MX7D EPDC supports advanced mode and standard mode. Since current
PXP in uboot for i.MX7D not ready, only support standard mode now.
advanced and standard mode needs waveform firmware's support.Signed-off-by: Peng Fan
28 Jul, 2015
1 commit
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The bootargs is not set correctly.
The final bootargs consist of uboot's bootargs and bootimg's bootargs.
This patch set bootimg's bootargs as final bootargs if uboot's bootargs is not set.
And take uboot's bootargs as final bootargs if uboot's bootargs is set.Signed-off-by: zhang sanshan
27 Jul, 2015
1 commit
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'fastboot reboot-bootloader' is took as 'fastboot reboot' in V2015.04.
The length of fastboot command is decided by the length of cmd_dispatch_info's cmd.
So need put reboot-bootloader in front of reboot.Signed-off-by: zhang sanshan
13 Jul, 2015
3 commits
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Enable fastboot command "fastboot flash data"
Custom may need to update data partition in fastboot mode.
This patch enable flash data partition in emmc\sd.Signed-off-by: Zhang Sanshan
Signed-off-by: Ye.Li -
enable fastboot command: "fastboot reboot-bootloader"
After type this command, the board will reboot to bootloader mode.
Set ANDROID_FASTBOOT_BOOT flag in SNVS_LPGPR before reboot.Signed-off-by: Zhang Sanshan
Signed-off-by: Ye.Li -
1. Replace the UDC driver with community's USB gadget d_dnl driver.
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Change the booti command to boota, due to the booti has been used for
ARM64 image boot.
5. Modify boota implementation to load ramdisk and fdt to their loading
addresses specified in boot.img header, while bootm won't do it for
android image.
6. Modify the android image HAB implementation. Authenticate the boot.img
on the "load_addr" for both SD and NAND.
7. Enable new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
8. Use community's way to combine cmdline in boot.img and u-boot environment,
not overwrite the cmdline in boot.imgSigned-off-by: Ye.Li
12 Jun, 2015
1 commit
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From temp sensor guys:
"
I confirmed the math with him(had do the accuracy study) today.
The new, final equation is:Tmeas = (Nmeas - n1) / slope + t1 + offset
n1= fused room count
t1= 25
offset=3.580661
slope= 0.4148468 – 0.0015423*n1
"87723f903454aaf17336e0fe9098ea7911c19f3c update the thermal with not
accurate slope parameters. This patch fix it.Signed-off-by: Peng Fan
29 May, 2015
1 commit
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There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.Signed-off-by: Nitin Garg
Signed-off-by: Peng Fan
20 May, 2015
1 commit
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Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB
for mx7d. So that the warm reset is disabled.Signed-off-by: Ye.Li
13 May, 2015
1 commit
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The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL,
so when using this structure to access gpr registers needs to change
the base address to IOMUXC_BASE_ADDR.Signed-off-by: Ye.Li
07 May, 2015
3 commits
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Add maximum ecc strength for each platfrom to avoid the calculated ecc
exceed the limitation.Signed-off-by: Han Xu
(cherry picked from commit fdc5bac6ae8b699924c4e84b86e38aa73f694827) -
This patch adds enable/disable hooks support for ldb_di[0/1] clocks
and enables/disables them when necessary.Signed-off-by: Liu Ying
(cherry picked from commit 839a1da941be48baf27c9cb28939cc6b2030424a) -
The LDB is found in MX6 variants and MX53, so this patch makes the ldb_di clock
relevant code be built only for them.Signed-off-by: Liu Ying
(cherry picked from commit c0dc175a9780505ec8939bda5dda9c2ec549a7f0)
06 May, 2015
1 commit
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From IC guys:
"
After a thorough accuracy study of the Temp sense circuit,
we found that with our current equation, an average part can
read 7 degrees lower than a known forced temperature.
We also found out that the standard variance was around 2C;
which is the tightest distribution that we could create.
We need to change the temp sense equation to center the average
part around the target temperature.Old Equation:
Temp = Troom,cal – slope*(Count measured – Count room fuse)
Where
Troom,cal = 25C and
Slope = 0.4297157 – (0.0015974 * Count room fuse)New Equation:
Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset
Where
Troom,cal = 25C and
Slope = 0.4445388 – (0.0016549 * Count room fuse)
Offset = 3.580661
"According the new equation, update the thermal driver.
c1 and c2 changed to u64 type and update comments.Signed-off-by: Peng Fan
05 May, 2015
4 commits
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Add platform check to avoid to access the reserved register
Signed-off-by: Fugang Duan
Signed-off-by: Peng Fan -
i.MX6UL qspi controller also needs at least 16 bytes when writing.
Signed-off-by: Peng Fan
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comment out GPIO6/7 for MX6UL
Signed-off-by: Peng Fan
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I2C4 support for i.MX
Signed-off-by: Peng Fan
29 Apr, 2015
6 commits
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The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
HOLDTIME + 1 is the number of clk cycles the fec is holding the output.
Set the right hold time value when the MDC root clock is greater than
100Mhz.The issue was reported on i.MX28 and is fixed by Uwe Kleine-König in kernel:
https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/
drivers/net/ethernet/freescale/fec_main.c?id=63c607321492c5efc7a31bc4ea734b877f8e7f87Signed-off-by: Fugang Duan
(cherry picked from commit 0373a160e7f698064a6625e85f9120b6c81c1b61) -
Update pcie code to align with imx_v2014.04. Mainly add DEBUG
related stuff.Signed-off-by: Peng Fan
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The string display on second line repeats the last word of
first line and does not show full.
This is the bug introduced by the fixing to MLK-10542.Signed-off-by: Ye.Li
(cherry picked from commit ac430cee8c42f0acad9e126631d772b99f1166ea)
(cherry picked from commit ff62c5b275a9b5e47d570d3eb10622799bf12070) -
The caculation of left space for version string is not correct, should
use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space
than actual have and cause string to overlay logo picture.Also current version string display only supports two lines words at max.
This also causes overlay when the LCD pixel colume size is not enough.Signed-off-by: Ye.Li
(cherry picked from commit ed53487d36a886fb4557088804a4b5232b168889) -
Fix reading temperature.
Signed-off-by: Peng Fan
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Change to load EPDC waveform from FAT partition and allocate waveform
buffer, framebuffer and working buffer in dynamic manner not static.
So many EPDC configurations are removed.To enable the EPDC feature, must define CONFIG_MXC_EPDC and CONFIG_SPLASH_SCREEN.
Signed-off-by: Ye.Li
(cherry picked from commit 4d55a4124be3a3a6288c3c845d17fd9d4f2b8b43)Conflicts:
include/configs/mx6slevk.h
