23 Jul, 2015

1 commit


10 Jul, 2015

1 commit

  • Since commit 09c3280754f8 (mtd, nand: Move common functions from
    cmd_nand.c to common place), NAND commands would not work at all
    on large devices.

    => nand read 80000000 10000 10000

    NAND read: Offset exceeds device limit
    => nand erase 100000 100000

    NAND erase: Offset exceeds device limit

    The type of the "size" of "struct mtd_info" is uint64_t, while
    mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
    The chipsize is wrapped around if the argument is given with 2GB
    or larger.

    Acked-by: Heiko Schocher
    Acked-by: Scott Wood
    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     

02 Jul, 2015

1 commit


01 Jul, 2015

6 commits


30 Jun, 2015

4 commits

  • sst25wf040b doesn't support Auto Address Increment Programming command.
    Remove SST_WR flag.

    Signed-off-by: Haikun Wang
    Tested-by: Haikun Wang
    Reviewed-by: Jagannadh Teki

    Haikun Wang
     
  • Move common functions from cmd_nand.c (for calculating offset
    and size from cmdline paramter) to common place, so they could
    used from other commands which use mtd partitions.

    For onenand the arg_off_size() is left in common/cmd_onenand.c.
    It should use now the common arg_off() function, but as I could
    not test onenand I let it there ...

    Signed-off-by: Heiko Schocher
    Acked-by: Scott Wood
    Reviewed-by: Jagannadh Teki

    Heiko Schocher
     
  • Add MTD layer driver for spi, original patch from:
    http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced

    Changes from Heiko Schocher against this patch:
    - Remove compile error if not defining CONFIG_SPI_FLASH_MTD:

    LD drivers/mtd/spi/built-in.o
    drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister':
    /home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
    drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
    drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister':
    /home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
    drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
    make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1
    make: *** [drivers/mtd/spi] Fehler 2

    - Add a README entry.
    - Add correct writebufsize, to fit with Linux v3.14
    MTD, UBI/UBIFS sync.

    Note (From Jagan): For testing raw mtd parition erase/read/write operations
    using cmd_sf, sf_mtd should be required to register the spi flash device to
    MTD layer but the sf_mtd_info ops were not required until and unless if we
    use any flash filesystem layer say for example UBI. Due to this the foot-print
    got increased ~290bytes in non-UBI case here that should be acceptible.

    Signed-off-by: Daniel Schwierzeck
    Signed-off-by: Heiko Schocher
    Tested-by: Jagannadh Teki
    Reviewed-by: Jagannadh Teki

    Daniel Schwierzeck
     
  • Atmel DataFlash chips have commands different from common spi
    flash commands.
    Atmel DataFlash also have special page-size.
    This driver add support for accessing Atmel DataFlash.
    It is based on the Driver Model.
    Example:
    => sf probe 1:0
    SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 Bytes, total 264 KiB, revision d
    => sf erase 0 42000
    SF: 270336 bytes @ 0x0 Erased: OK
    => mw.l 82000000 45444342 20000
    => sf write 82000000 0 42000
    SF: 270336 bytes @ 0x0 Written: OK
    => sf read 83000000 0 42000
    SF: 270336 bytes @ 0x0 Read: OK
    => cmp.b 82000000 83000000 42000
    Total of 270336 byte(s) were the same

    Signed-off-by: Haikun Wang
    Tested-by: Haikun Wang
    Reviewed-by: Simon Glass
    Reviewed-by: Chakra Divi
    Reviewed-by: Jagan Teki

    Haikun Wang
     

28 Jun, 2015

1 commit


26 Jun, 2015

1 commit


18 Jun, 2015

2 commits


29 May, 2015

1 commit


25 May, 2015

10 commits

  • This changes enable ONFI detection. The Read ID command now allows
    one address byte which is needed for ONFI detection. To read the
    ONFI parameter page, the NAND_CMD_PARAM need to be supported. The
    CMD code enables one command and one address byte along with reading
    data from flash using R/B#, as specified by ONFI.

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • Add option to choose between current 24-error correction and 32-error
    correction through Kconfig. 32-error correction allow to use NAND
    chips which require up to 8-bit error correction per 512 byte (when
    using 2K pages).

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • This commit allows users to enable/disable the Freescale NFC
    controller found in systems like Vybrid (VF610), MPC5125, MCF54418
    or Kinetis K70 via Kconfig with more detailed help docs.

    Signed-off-by: Stefan Agner
    Acked-by: Stefano Babic
    [scottwood: updated vf610twr_nand_defconfig]
    Signed-off-by: Scott Wood

    Stefan Agner
     
  • Use in-band bad block table (NAND_BBT_NO_OOB) which allows to
    use the full OOB for hardare ECC purposes. Since there is no
    ECC correction on the OOB it is also safer to use in-band area
    to store the bad block table marker.

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • Implement read of OOB area only. When using column and sector size
    properties, only parts of the page can be read. However, this works
    only when hardware ECC is disabled, otherwise the ECC engine would
    ruin the data in the buffer. To allow OOB only reads, three points
    had to be addressed:
    - Set ECC mode per command.
    - Handle NAND_CMD_READOOB seperate. Make sure column and sector
    size is correctly set up, while disabling ECC.
    - Now, the OOB data end up at the beginning of the buffer. Remove
    the special handling of OOB (spareonly).

    Especially bad block scans benefit from this change. On a 512MiB
    SLC NAND device, the bad block scan took 1.5s less than before.

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • Allow bit flips in a empty page up to half of the recoverable
    bits (strength / 2).

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • Since we do not support sub-page writes anyway, reading the page
    back to the controller on SEQIN command is not required. Remove
    the page read on SEQIN.

    However, the column/page values relevant to the SEQIN command, hence
    set the column/row address on SEQIN command.

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • To improve performance we remember the current page in the buffer
    and avoid reading it twice. This implicit page cache increases
    complexity while does not increase performance in real world cases.
    This patch removes that feature.

    Acked-by: Bill Pringlemeir
    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • Signed-off-by: Jörg Krause
    Reviewed-by: Marek Vasut

    Jörg Krause
     
  • Calculate ecc strength according oobsize, but not hardcoded
    which is not aligned with kernel driver

    Signed-off-by: Peng Fan
    Signed-off-by: Ye.Li
    Reviewed-by: Marek Vasut
    Signed-off-by: Jörg Krause

    Peng Fan
     

23 May, 2015

1 commit


22 May, 2015

1 commit

  • On systems with caches enabled, NAND I/O may need to flush/invalidate
    the cache during read/write operations. For this to work correctly, all
    buffers must be cache-aligned. Fix nand_verify*() to allocate aligned
    buffers.

    This prevents cache alignment warnings from being spewed when using
    U-Boot to write an updated version of itself to flash on NVIDIA Tegra
    Seaboard (after perturbation of stack/data layout in current
    u-boot-dm/next branch).

    I have validatd (executed) nand_verify(), but I don't think I've executed
    nand_verify_page_oob(); testing of that would be useful.

    Cc: Peter Tyser
    Cc: Heiko Schocher
    Cc: Scott Wood
    Fixes: 59b5a2ad83df ("nand: Add verification functions")
    Signed-off-by: Stephen Warren
    Reviewed-by: Simon Glass
    Acked-by: Scott Wood

    Stephen Warren
     

15 May, 2015

1 commit


07 May, 2015

1 commit


28 Apr, 2015

4 commits

  • Tom Rini
     
  • Upto now flash sector_size is assigned from params which isn't
    necessarily a sector size from vendor, so based on the SECT_*
    flags from flash_params the erase_size will compute and it will
    become the sector_size finally.

    Bug report (from Bin Meng):
    => sf probe
    SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
    total 2 MiB, mapped at ffe00000

    => sf erase 0 +100
    SF: 65536 bytes @ 0x0 Erased: OK

    Signed-off-by: Jagannadha Sutradharudu Teki
    Reported-by: Bin Meng
    Tested-by: Bin Meng

    Jagannadha Sutradharudu Teki
     
  • With SPI flash moving to driver model, commit fbb0991 "dm: Convert
    spi_flash_probe() and 'sf probe' to use driver model" ignored the
    SST flash-specific write op (byte program & word program), which
    actually broke the SST flash from wroking.

    This commit makes SST flash work again under driver model, by adding
    SST flash-specific handling in the spi_flash_std_write().

    Signed-off-by: Bin Meng
    Reviewed-by: Jagannadha Sutradharudu Teki

    Bin Meng
     
  • Add a new member 'flags' in struct spi_flash to store the flash flags
    during spi_flash_validate_params().

    Signed-off-by: Bin Meng
    Reviewed-by: Jagannadha Sutradharudu Teki

    Bin Meng
     

24 Apr, 2015

2 commits

  • This adds NAND boot support for LS2085AQDS, using SPL framework.
    Details of forming NAND image can be found in README.

    Signed-off-by: Scott Wood
    [York Sun: Remove +S from defconfig after commit 252ed872]
    Signed-off-by: York Sun

    Scott Wood
     
  • IFC has two register pages.Till IFC version 1.4 each
    register page is 4KB each.But IFC ver 2.0 register page
    size is 64KB each.IFC regiters structure is break into
    two viz FCM and RUNTIME.FCM(Flash control machine) registers
    are defined in PAGE0 and controls IFC generic functionality.
    RUNTIME registers are defined in PAGE1 and controls NAND and
    GPCM funcinality.

    FCM and RUNTIME structures defination is common for IFC
    version 1.4 and 2.0.

    Signed-off-by: Jaiprakash Singh
    Signed-off-by: York Sun

    Jaiprakash Singh
     

23 Apr, 2015

2 commits