17 Feb, 2014
1 commit
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Context loss counting relies on several prm function pointers that
serve as a "mapping" into the context loss registers and actually
allow reading and clearing of the registers. Use the same
from omap4 for am43xx as the layout of the prcm is similar.Signed-off-by: Dave Gerlach
04 Feb, 2014
1 commit
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Currently machine restart for AM43x is hooked with am43xx_restart
function, which calls functions that are in file prm33xx.c. This file
is not built for AM43x, So this give a build error for AM43x alone builds.
Fixing this by using omap44xx_restart.Reported-by: Felipe Balbi
Signed-off-by: Lokesh Vutla
03 Feb, 2014
1 commit
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The SyncTimer in AM43x seems to be clocked using an inaccuarte 32k
clock (CLK_32KHZ) derived from PER DPLL, causing system time to go
slowly (~10% deviation).Use gptimer as clocksource instead, as is done in the case of AM335x
(which does not have a SyncTimer). With this, system time keeping works
accurately.Signed-off-by: Rajendra Nayak
31 Jan, 2014
2 commits
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omap2_dpll_round_rate() doesn't actually round the given rate, even if
the name and the description so hints. Instead it only tries to find an
exact rate match, or if that fails, return ~0 as an error.What this basically means is that the user of the clock needs to know
what rates the dpll can support, which obviously isn't right.This patch adds a simple method of rounding: during the iteration, the
code keeps track of the closest rate match. If no exact match is found,
the closest is returned.Signed-off-by: Tomi Valkeinen
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Printing with unsigned long rates with %ld gives wrong result if the
rate is high enough. Fix this by using %lu.Signed-off-by: Tomi Valkeinen
29 Jan, 2014
2 commits
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In an effort to not have to hard code parent clock names for system timers,
this patch introduces a DT property "clock-default" to mux-clocks which allows
one to specify the default mux clock in DT by referring to the clock phandle.
Doing so would allow us to eliminate the clk_set_parent code from
mach-omap2/timer.c and also we wouldn't have to hardcode clock parent names in
the OMAP_SYS_32K_TIMER_INIT and OMAP_SYS_GP_TIMER_INIT macros.Tested on AM335x beaglebone with timer1 clock.
Cc: Nishanth Menon
Cc: Tero Kristo
Cc: Santosh Shilimkar
Tested-by: Sekhar Nori
Signed-off-by: Joel Fernandes -
HIGHMEM pages may not be mapped so we must kmap them before accessing.
This resolves a random OOPs error that was showing up during OpenSSL SHA tests.Signed-off-by: Joel Fernandes
22 Jan, 2014
2 commits
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HWMOD entries support for TI Dual Video Processing Front End (VPFE)
(aka Dual cam) of AM43xx platformSigned-off-by: Benoit Parrot
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Add clock property for both TI Video Processing Front End (VPFE)
instance (aka Dual cam) for AM43xx family of devices.Signed-off-by: Benoit Parrot
16 Jan, 2014
1 commit
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Do not reset GPIO5 at boot-up because GPIO5_7 is used
on AM437x GP-EVM to control VTT regulators on DDR3.
Without this some GP-EVM boards will fail to boot because
of DDR3 corruption.Signed-off-by: Dave Gerlach
15 Jan, 2014
1 commit
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On AM43x HS device, in certain scenarios, L3 errors that are
undocumented (those after highest value bit in flagmux) are occuring.
They can't be cleared as documentation mentions nothing about those
errors. Have the driver handle it the same way as for timeout, else isr
loops endlessly.Signed-off-by: Rajendra Nayak
Signed-off-by: Afzal Mohammed
18 Dec, 2013
1 commit
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Errors that cannot be cleared (determined by reading status register)
are currently handled by masking it. Status register is understood to be
raw status rather than result of masking, based on recent issue reported
by Vaibhav Hiremath (I could not make out from the documentation that it
is raw status).As that is the case, if after the occurance of an unclearable error,
another clearable L3 error happens that has lower binary weightage in
flagmux register (compared to the unclearable error that has occured),
and as status register is raw, isr will think that interrupt is raised
due to unclearable error(even though it was masked). This causes the new
error that could have been cleared, uncleared, resulting in isr getting
called repeatedly.Fix it by masking raw status with masked ones before handling the error.
Reported-by: Vaibhav Hiremath
Signed-off-by: Afzal Mohammed
Tested-by: Vaibhav Hiremath
11 Dec, 2013
14 commits
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Remove linkage of AM43XX_CM_PER_L3_CLKCTRL_OFFSET to l3_hwmod on
AM43XX to prevent driver bound to L3 from attempting to idle clock
at suspend time as this must be handled later by CM3 in suspend path
or system will hang.Signed-off-by: Dave Gerlach
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Update ocp node with resource information
Signed-off-by: Dave Gerlach
Signed-off-by: Afzal Mohammed -
Add AM43x information to handle L3 error.
Timeout doesn't have STDERRLOG_MAIN register. And per hardware team, L3
timeout error cannot be cleared the normal way (by setting bit 31 in
STDERRLOG_MAIN), instead it may be required to do system reset.
L3 error handler can't help in such scenarios.Hence indicate timeout target offset as "0xdeadbeef" as is done for
undocumented bits. This will also help to handle these cases seperately
in isr.Signed-off-by: Dave Gerlach
Signed-off-by: Afzal Mohammed -
Timeout errors in AM43x can't be cleared per h/w team, neither does it
have a STDERRLOG_MAIN to clear the error. Upon occurance of error from
such sources, mask it. Otherwise, isr would loop continously as
interrupt is not cleared at the source.This change also helps in handling undocumented flagmux bits gracefully.
As currently, L3 timeout error is observed on every boot of
AM43x ePOS EVM, degrade from WARN to pr_warn. Also provide sufficient
information on the source of unclearable error.Signed-off-by: Afzal Mohammed
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There are SoC's (like AM43x) that can have less than 3 clockdomains.
Modify the driver so that it can handle different number of
clockdomains to prepare for AM43x support.While at it use managed device resources and avoid a kfree in error path
which should not be done as the memory is not an allocated one.Signed-off-by: Afzal Mohammed
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On DRA7, unlike on OMAP4 and OMAP5, the flag mux input numbers used to indicate
the source of errors are not continous. Have a way in the driver to catch these
and WARN the user of the flag mux input thats either undocumented or wrong.Signed-off-by: Rajendra Nayak
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The dra7xx soc has the same l3-noc interconnect ip (as OMAP4 and OMAP5).
So make the driver code generic to make it easier to add the dra7xx
changes.Signed-off-by: Sricharan R
Signed-off-by: Rajendra Nayak -
Add proper interrupt data and register data so wkup_m3 can be
properly initialized for AM43xx by PM code.Signed-off-by: Dave Gerlach
Acked-by: Russ Dill -
Adjust AM43xx SRAM size down from 256k to 64k to match AM33xx. Because
AM43xx separates SRAM into 64k + 192k chunks, only use the first 64k so
that the second chunk can be powered off during suspend while keeping
the first in retention.Signed-off-by: Dave Gerlach
Acked-by: Russ Dill -
Without initial soft reset of GPMC during hwmod setup the CLKCTRL
for GPMC will not transition to idle state which prevents PER_PD
transition so this patch allows it.Signed-off-by: Dave Gerlach
Acked-by: Russ Dill -
Modify entry for dpll_per_clkdcoldo so autoidle bits are properly
controlled and clock is not unintentionally forced active,
preventing PER_PD transition. Force active bit is set by default at
boot so adding this will allow it to be handled automatically
by kernel.Signed-off-by: Dave Gerlach
Acked-by: Russ Dill -
Transitioning wkup_m3 driver to support reset framework means AM33XX
will use it as well.Signed-off-by: Dave Gerlach
Acked-by: Russ Dill -
Add the correct register offset and bit shift data for wkup_m3 reset
for both AM335x and AM43xx within reset driver at data index 1.Signed-off-by: Dave Gerlach
Acked-by: Russ Dill -
commit e455c636ddfc760eea84e736e0b974d3d6328621 (ARM: mach-omap2:
Introduce late_init function for AM43x) introduced .init_late =
am43xx_init_lateHowever, commit eea497ee2895101f0eeac36168deaba1c1047ee9 (ARM:
OMAP2+: Export SoC data to userspace) introduces .init_late =
am33xx_init_late, again!currently, we have DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened
Device Tree)") with two init_late entries! remove the wrong one.Reported-by: Dave Gerlach
Signed-off-by: Nishanth Menon
05 Dec, 2013
3 commits
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OpenSSL AF_ALG users need these options enabled so that OpenSSL
can use the crypto drivers, enable options for the same.Signed-off-by: Joel Fernandes
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Kernel can silenty fail for DT-boot after the decompression stage, if DTB is
overwritten. Instead of simply failing, we detect the condition and print an
error.One may think that it is sufficient for the bootloader to place the DTB away
from kernel, but this is not the right fix because: (1) We add more dependence
to the bootloader's stupidity (2) the decompressed kernel end address is not
known to the loader. Also, we shouldn't depend on bootloader for silently
failing us, so we detect the condition and error out.Signed-off-by: Joel Fernandes
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The correct bit is 24 for AHCLKX.
Acked-by: Tero Kristo
Signed-off-by: Peter Ujfalusi
26 Nov, 2013
3 commits
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For some SoCs like omap5/am33xx and am43xx, the SoC info like
family/machine/revision wasn't exported to userspace via
the /sys/devices/socX interface.Add the missing omap_soc_device_init() calls for these devices.
Signed-off-by: Rajendra Nayak
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Enabling the erratum for OMAP5/DRA7 platforms.
Signed-off-by: Sricharan R
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799270: Writing ACTLR.SMP when the L2 cache has been idle for an extended
period may not work correctly.Description:
If the L2 cache logic clock is stopped because of L2 inactivity, setting or
clearing the ACTLR.SMP bit might not be effective. The bit is modified in the
ACTLR, meaning a read of the register returns the updated value. However the
logic that uses that bit retains the previous value.1) The L2 cache block has been idle for 256 or more cycles with no memory requests
from any core, no external snoops, and no ACP requests.2) A CPU executes an “MCR p15,0,r0,c1,c0,1” instruction (write the ACTLR register)
that modifies ACTLR[6].Implications:
If the errata conditions occur when the ACTLR.SMP bit is being set at boot, the
instruction cache or TLB could become incoherent, as that CPU would not receive
necessary DVM requests.Workaround:
The following code must be executed with all interrupts disabled
r1 must contain the value of an Non-cacheable, SO, or Dev memory location
or register(typically a memory mapped register with no read side effects would be used)
mrc p15,0,r0,c1,c0,1 ; read current value of ACTLR
orr r0,r0,#0x40 ; set/clear SMP bit (ACTLR[6])
ldr r1, [r1] ; read a device register (location guaranteed not to hit the L1 cache)
and r1,r1,#0 ;
orr r0,r0,r1 ; create dummy dependency between dummy load and MCR to write SMP
MCR p15,0,r0,c1,c0,1
; Write CP15 ACTLR
ISB
DSBSigned-off-by: Sricharan R
Signed-off-by: Rajendra Nayak
21 Nov, 2013
2 commits
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Prevent ldm access crossing 1K page boundary by aligning relevant
section to 1K. AM43x hangs if ldm access crosses 1K page boundary. This
issue was hit with a particular combination of CONFIG options, presently
with CONFIG_PREEMPT enabled and CONFIG_DEBUG_LL disabled.Hang is due to bug in early internal version of AM43x engineering
sample, production version does not have this bug and can be reverted
at that time.Problem here is similar to as that mentioned in
"3ca5009 ARM: head.S: avoid ldm access crossing 1K page boundary".Signed-off-by: Afzal Mohammed
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DES IP already has main and interface clk as des_fck.
Node for des_fck is missing in clk tree. Adding the same.Signed-off-by: Lokesh Vutla
20 Nov, 2013
1 commit
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The hwmod init sequence involves initializing and idling all the
hwmods during bootup. If a module class has sysconfig, the init
sequence utilizes the module register base for performing any
sysc configuration.The module address space is being removed from hwmod database and
retrieved from the property of the corresponding DT node.
If a hwmod does not have its corresponding DT node defined and the
memory address space is not defined in the corresponding
omap_hwmod_ocp_if, then the module register target address space
would be NULL and any sysc programming would result in a NULL
pointer dereference and a kernel boot hang.Handle this scenario by checking for a valid module address space
during the _init of each hwmod, and leaving it in the registered
state if no module register address base is defined in either of
the hwmod data or the DT data.Signed-off-by: Suman Anna
Acked-by: Santosh Shilimkar
Tested-by: Nishanth Menon
Acked-by: Tony Lindgren
[paul@pwsan.com: use -ENXIO rather than -ENOMEM to indicate a missing address
space error; fixed checkpatch.pl problem]
Signed-off-by: Paul Walmsley
[rnayak@ti.com: Backported to 3.12]
Signed-off-by: Rajendra Nayak
19 Nov, 2013
1 commit
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CONFIG_PREEMPT_NONE causes RCU sched stalls when running an in-kernel test such
as tcrypt for a long period. CONFIG_PREEMPT will fix this by allowing the RCU
tasks to schedule while the tests are running.Signed-off-by: Joel Fernandes
14 Nov, 2013
1 commit
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This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.All information can be reconstructed by already known runtime
information.As we now use some functions that were previously only used from __init
context, annotations had to be dropped.[nm@ti.com: added error handling for runtime + suspend_late/early_resume]
Signed-off-by: Nishanth Menon
Signed-off-by: Daniel Mack
Tested-by: Joel Fernandes
Acked-by: Joel Fernandes
13 Nov, 2013
3 commits
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WDT1 module can take one of the below clocks as input functional
clock -
- On-Chip 32K RC Osc [default/reset]
- 32K from PRCMThe On-Chip 32K RC Osc clock is not an accurate clock-source as per
the design/spec, so as a result, for example, timer which supposed
to get expired @60Sec, but will expire somewhere ~@40Sec, which is
not expected by any use-case.The solution here is to switch the input clock-source to PRCM
generated 32K clock-source during boot-time itself.
This is derived from AM33xx clock file.Signed-off-by: Lokesh Vutla
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The On-Chip 32K RC Osc clock is not an accurate clock-source as per
the design/spec. So try not to use this as a clock source.
For now adding a comment is helpful for others using this as a
clocksource.Signed-off-by: Lokesh Vutla
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The On-Chip 32K RC Osc clock is not an accurate clock-source as per
the design/spec. So try not to use this as a clock source.
For now adding a comment is helpful for others using this as a
clocksource.Signed-off-by: Lokesh Vutla