Eric Lee / linux-smarc-t335x-v3.2

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Commit ae25144ed1b608a16c69c5cf1c37e7c5ff7e210d

Authored by Hebbar Gururaja
1 parent 042c58a03f
Exists in v3.2_SMARCT335xPSP_04.06.00.11 and in 3 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN

Revert "ARM: OMAP: AM33XX: Add OPP table for PG2.1 AM335x" 

This reverts commit ee9dfd8d729d3e7b5ce9e404a0e87f27f6f79135.

This patch checks for the package type for checking the supported opp
bits & also if the bits are set, the opp table is updated.
However, checking package type bit is not required & also, the opp bit
checking must be reversed.

A fix for the same will follow after this commit

Showing 1 changed file with 4 additions and 123 deletions Inline Diff

arch/arm/mach-omap2/opp3xxx_data.c
Diff comments   View file @ ae25144
1 /* 1 /*
2 * OMAP3 OPP table definitions. 2 * OMAP3 OPP table definitions.
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Nishanth Menon 5 * Nishanth Menon
6 * Kevin Hilman 6 * Kevin Hilman
7 * Copyright (C) 2010-2011 Nokia Corporation. 7 * Copyright (C) 2010-2011 Nokia Corporation.
8 * Eduardo Valentin 8 * Eduardo Valentin
9 * Paul Walmsley 9 * Paul Walmsley
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 * 14 *
15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
16 * kind, whether express or implied; without even the implied warranty 16 * kind, whether express or implied; without even the implied warranty
17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 */ 19 */
20 #include <linux/module.h> 20 #include <linux/module.h>
21 #include <linux/io.h>
22 21
23 #include <plat/cpu.h> 22 #include <plat/cpu.h>
24 23
25 #include "control.h" 24 #include "control.h"
26 #include "omap_opp_data.h" 25 #include "omap_opp_data.h"
27 #include "pm.h" 26 #include "pm.h"
28 27
29 /* 34xx */ 28 /* 34xx */
30 29
31 /* VDD1 */ 30 /* VDD1 */
32 31
33 #define OMAP3430_VDD_MPU_OPP1_UV 975000 32 #define OMAP3430_VDD_MPU_OPP1_UV 975000
34 #define OMAP3430_VDD_MPU_OPP2_UV 1075000 33 #define OMAP3430_VDD_MPU_OPP2_UV 1075000
35 #define OMAP3430_VDD_MPU_OPP3_UV 1200000 34 #define OMAP3430_VDD_MPU_OPP3_UV 1200000
36 #define OMAP3430_VDD_MPU_OPP4_UV 1270000 35 #define OMAP3430_VDD_MPU_OPP4_UV 1270000
37 #define OMAP3430_VDD_MPU_OPP5_UV 1350000 36 #define OMAP3430_VDD_MPU_OPP5_UV 1350000
38 37
39 struct omap_volt_data omap34xx_vddmpu_volt_data[] = { 38 struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
40 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c), 39 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
41 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c), 40 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
42 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18), 41 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
43 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18), 42 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
44 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18), 43 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
45 VOLT_DATA_DEFINE(0, 0, 0, 0), 44 VOLT_DATA_DEFINE(0, 0, 0, 0),
46 }; 45 };
47 46
48 /* VDD2 */ 47 /* VDD2 */
49 48
50 #define OMAP3430_VDD_CORE_OPP1_UV 975000 49 #define OMAP3430_VDD_CORE_OPP1_UV 975000
51 #define OMAP3430_VDD_CORE_OPP2_UV 1050000 50 #define OMAP3430_VDD_CORE_OPP2_UV 1050000
52 #define OMAP3430_VDD_CORE_OPP3_UV 1150000 51 #define OMAP3430_VDD_CORE_OPP3_UV 1150000
53 52
54 struct omap_volt_data omap34xx_vddcore_volt_data[] = { 53 struct omap_volt_data omap34xx_vddcore_volt_data[] = {
55 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c), 54 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
56 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c), 55 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
57 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18), 56 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
58 VOLT_DATA_DEFINE(0, 0, 0, 0), 57 VOLT_DATA_DEFINE(0, 0, 0, 0),
59 }; 58 };
60 59
61 /* 36xx */ 60 /* 36xx */
62 61
63 /* VDD1 */ 62 /* VDD1 */
64 63
65 #define OMAP3630_VDD_MPU_OPP50_UV 1012500 64 #define OMAP3630_VDD_MPU_OPP50_UV 1012500
66 #define OMAP3630_VDD_MPU_OPP100_UV 1200000 65 #define OMAP3630_VDD_MPU_OPP100_UV 1200000
67 #define OMAP3630_VDD_MPU_OPP120_UV 1325000 66 #define OMAP3630_VDD_MPU_OPP120_UV 1325000
68 #define OMAP3630_VDD_MPU_OPP1G_UV 1375000 67 #define OMAP3630_VDD_MPU_OPP1G_UV 1375000
69 68
70 struct omap_volt_data omap36xx_vddmpu_volt_data[] = { 69 struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
71 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c), 70 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
72 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16), 71 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
73 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23), 72 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
74 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27), 73 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
75 VOLT_DATA_DEFINE(0, 0, 0, 0), 74 VOLT_DATA_DEFINE(0, 0, 0, 0),
76 }; 75 };
77 76
78 /* VDD2 */ 77 /* VDD2 */
79 78
80 #define OMAP3630_VDD_CORE_OPP50_UV 1000000 79 #define OMAP3630_VDD_CORE_OPP50_UV 1000000
81 #define OMAP3630_VDD_CORE_OPP100_UV 1200000 80 #define OMAP3630_VDD_CORE_OPP100_UV 1200000
82 81
83 struct omap_volt_data omap36xx_vddcore_volt_data[] = { 82 struct omap_volt_data omap36xx_vddcore_volt_data[] = {
84 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c), 83 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
85 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16), 84 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
86 VOLT_DATA_DEFINE(0, 0, 0, 0), 85 VOLT_DATA_DEFINE(0, 0, 0, 0),
87 }; 86 };
88 87
89 /* OPP data */ 88 /* OPP data */
90 89
91 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { 90 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
92 /* MPU OPP1 */ 91 /* MPU OPP1 */
93 OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV), 92 OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
94 /* MPU OPP2 */ 93 /* MPU OPP2 */
95 OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV), 94 OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
96 /* MPU OPP3 */ 95 /* MPU OPP3 */
97 OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV), 96 OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
98 /* MPU OPP4 */ 97 /* MPU OPP4 */
99 OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV), 98 OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
100 /* MPU OPP5 */ 99 /* MPU OPP5 */
101 OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV), 100 OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
102 101
103 /* 102 /*
104 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is 103 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
105 * almost the same than the one at 83MHz thus providing very little 104 * almost the same than the one at 83MHz thus providing very little
106 * gain for the power point of view. In term of energy it will even 105 * gain for the power point of view. In term of energy it will even
107 * increase the consumption due to the very negative performance 106 * increase the consumption due to the very negative performance
108 * impact that frequency will do to the MPU and the whole system in 107 * impact that frequency will do to the MPU and the whole system in
109 * general. 108 * general.
110 */ 109 */
111 OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV), 110 OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
112 /* L3 OPP2 */ 111 /* L3 OPP2 */
113 OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV), 112 OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
114 /* L3 OPP3 */ 113 /* L3 OPP3 */
115 OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV), 114 OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
116 115
117 /* DSP OPP1 */ 116 /* DSP OPP1 */
118 OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV), 117 OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
119 /* DSP OPP2 */ 118 /* DSP OPP2 */
120 OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV), 119 OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
121 /* DSP OPP3 */ 120 /* DSP OPP3 */
122 OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV), 121 OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
123 /* DSP OPP4 */ 122 /* DSP OPP4 */
124 OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV), 123 OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
125 /* DSP OPP5 */ 124 /* DSP OPP5 */
126 OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV), 125 OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
127 }; 126 };
128 127
129 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = { 128 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
130 /* MPU OPP1 - OPP50 */ 129 /* MPU OPP1 - OPP50 */
131 OPP_INITIALIZER("mpu", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV), 130 OPP_INITIALIZER("mpu", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV),
132 /* MPU OPP2 - OPP100 */ 131 /* MPU OPP2 - OPP100 */
133 OPP_INITIALIZER("mpu", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV), 132 OPP_INITIALIZER("mpu", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV),
134 /* MPU OPP3 - OPP-Turbo */ 133 /* MPU OPP3 - OPP-Turbo */
135 OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV), 134 OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
136 /* MPU OPP4 - OPP-SB */ 135 /* MPU OPP4 - OPP-SB */
137 OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV), 136 OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
138 137
139 /* L3 OPP1 - OPP50 */ 138 /* L3 OPP1 - OPP50 */
140 OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV), 139 OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
141 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ 140 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
142 OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV), 141 OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
143 142
144 /* DSP OPP1 - OPP50 */ 143 /* DSP OPP1 - OPP50 */
145 OPP_INITIALIZER("iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV), 144 OPP_INITIALIZER("iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV),
146 /* DSP OPP2 - OPP100 */ 145 /* DSP OPP2 - OPP100 */
147 OPP_INITIALIZER("iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV), 146 OPP_INITIALIZER("iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV),
148 /* DSP OPP3 - OPP-Turbo */ 147 /* DSP OPP3 - OPP-Turbo */
149 OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV), 148 OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
150 /* DSP OPP4 - OPP-SB */ 149 /* DSP OPP4 - OPP-SB */
151 OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV), 150 OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
152 }; 151 };
153 152
154 /* 33xx */ 153 /* 33xx */
155 154
156 /* VDD1 */ 155 /* VDD1 */
157 156
158 /* 157 /*
159 * Errata 1.0.15: OPP50 Operation on MPU Domain is Not Supported. 158 * Errata 1.0.15: OPP50 Operation on MPU Domain is Not Supported.
160 * 159 *
161 * To minimize power consumption, the ARM Cortex-A8 may be operated at 160 * To minimize power consumption, the ARM Cortex-A8 may be operated at
162 * the lower frequency defined by OPP50, but the respective voltage 161 * the lower frequency defined by OPP50, but the respective voltage
163 * domain VDD_MPU must be operated as defined by OPP100. So MPU OPP50 162 * domain VDD_MPU must be operated as defined by OPP100. So MPU OPP50
164 * definition is modified to 275MHz, 1.1V. 163 * definition is modified to 275MHz, 1.1V.
165 */ 164 */
166 #define AM33XX_VDD_MPU_OPP50_UV 1100000 165 #define AM33XX_VDD_MPU_OPP50_UV 1100000
167 #define AM33XX_VDD_MPU_OPP100_UV 1100000 166 #define AM33XX_VDD_MPU_OPP100_UV 1100000
168 #define AM33XX_VDD_MPU_OPP120_UV 1200000 167 #define AM33XX_VDD_MPU_OPP120_UV 1200000
169 #define AM33XX_VDD_MPU_OPPTURBO_UV 1260000 168 #define AM33XX_VDD_MPU_OPPTURBO_UV 1260000
170 169
171 static struct omap_opp_def __initdata am33xx_es1_0_opp_def_list[] = { 170 static struct omap_opp_def __initdata am33xx_es1_0_opp_def_list[] = {
172 /* MPU OPP1 - OPP50 */ 171 /* MPU OPP1 - OPP50 */
173 OPP_INITIALIZER("mpu", true, 275000000, AM33XX_VDD_MPU_OPP50_UV), 172 OPP_INITIALIZER("mpu", true, 275000000, AM33XX_VDD_MPU_OPP50_UV),
174 /* MPU OPP2 - OPP100 */ 173 /* MPU OPP2 - OPP100 */
175 OPP_INITIALIZER("mpu", true, 500000000, AM33XX_VDD_MPU_OPP100_UV), 174 OPP_INITIALIZER("mpu", true, 500000000, AM33XX_VDD_MPU_OPP100_UV),
176 /* MPU OPP3 - OPP120 */ 175 /* MPU OPP3 - OPP120 */
177 OPP_INITIALIZER("mpu", true, 600000000, AM33XX_VDD_MPU_OPP120_UV), 176 OPP_INITIALIZER("mpu", true, 600000000, AM33XX_VDD_MPU_OPP120_UV),
178 /* MPU OPP4 - OPPTurbo */ 177 /* MPU OPP4 - OPPTurbo */
179 OPP_INITIALIZER("mpu", true, 720000000, AM33XX_VDD_MPU_OPPTURBO_UV), 178 OPP_INITIALIZER("mpu", true, 720000000, AM33XX_VDD_MPU_OPPTURBO_UV),
180 }; 179 };
181 180
182 #define AM33XX_ES2_0_VDD_MPU_OPP50_UV 950000 181 #define AM33XX_ES2_0_VDD_MPU_OPP50_UV 950000
183 #define AM33XX_ES2_0_VDD_MPU_OPP100_UV 1100000 182 #define AM33XX_ES2_0_VDD_MPU_OPP100_UV 1100000
184 #define AM33XX_ES2_0_VDD_MPU_OPPTURBO_UV 1260000 183 #define AM33XX_ES2_0_VDD_MPU_OPPTURBO_UV 1260000
185 #define AM33XX_ES2_0_VDD_MPU_OPPNITRO_UV 1320000 184 #define AM33XX_ES2_0_VDD_MPU_OPPNITRO_UV 1320000
186 185
187 static struct omap_opp_def __initdata am33xx_es2_0_opp_def_list[] = { 186 static struct omap_opp_def __initdata am33xx_es2_0_opp_def_list[] = {
188 /* MPU OPP1 - OPP50 */ 187 /* MPU OPP1 - OPP50 */
189 OPP_INITIALIZER("mpu", true, 300000000, AM33XX_ES2_0_VDD_MPU_OPP50_UV), 188 OPP_INITIALIZER("mpu", true, 300000000, AM33XX_ES2_0_VDD_MPU_OPP50_UV),
190 /* MPU OPP2 - OPP100 */ 189 /* MPU OPP2 - OPP100 */
191 OPP_INITIALIZER("mpu", true, 600000000, 190 OPP_INITIALIZER("mpu", true, 600000000,
192 AM33XX_ES2_0_VDD_MPU_OPP100_UV), 191 AM33XX_ES2_0_VDD_MPU_OPP100_UV),
193 /* MPU OPP3 - OPPTurbo */ 192 /* MPU OPP3 - OPPTurbo */
194 OPP_INITIALIZER("mpu", true, 800000000, 193 OPP_INITIALIZER("mpu", true, 800000000,
195 AM33XX_ES2_0_VDD_MPU_OPPTURBO_UV), 194 AM33XX_ES2_0_VDD_MPU_OPPTURBO_UV),
196 /* MPU OPP4 - OPPNitro */ 195 /* MPU OPP4 - OPPNitro */
197 OPP_INITIALIZER("mpu", false, 1000000000, 196 OPP_INITIALIZER("mpu", false, 1000000000,
198 AM33XX_ES2_0_VDD_MPU_OPPNITRO_UV), 197 AM33XX_ES2_0_VDD_MPU_OPPNITRO_UV),
199 }; 198 };
200 199
201 #define AM33XX_ES2_1_VDD_MPU_OPP50_UV 950000
202 #define AM33XX_ES2_1_VDD_MPU_OPP100_UV 1100000
203 #define AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV 1260000
204 #define AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV 1350000
205
206 #define OPP_50_INDEX 0
207 #define OPP_100_INDEX 1
208 #define OPP_TURBO_INDEX 2
209 #define OPP_NITRO_INDEX 3
210
211
212 /* From AM335x TRM, SPRUH73H, Section 9.3.50 */
213 #define AM33XX_EFUSE_SMA_OFFSET 0x7fc
214
215 /*
216 * Bits [17-16] indicates package type
217 * 00 - reserved
218 * 01 - ZCZ
219 * 10 - ZCE
220 * 11 - reserved
221 */
222 #define PACKAGE_TYPE_MASK 0x3
223 #define PACKAGE_TYPE_SHFT 16
224
225 #define PACKAGE_TYPE_ZCZ 0x1
226 #define PACKAGE_TYPE_ZCE 0x2
227
228 /*
229 * Bits [12:0] are OPP Disabled bits,
230 * 1 = OPP is disabled and not available,
231 * 0 = OPP available.
232 */
233 #define MAX_FREQ_MASK 0x1fff
234 #define MAX_FREQ_SHFT 0
235
236 #define OPP_50_300MHZ_ZCZ_BIT 4
237 #define OPP_100_600MHZ_ZCZ_BIT 6
238 #define OPP_TURBO_800MHZ_ZCZ_BIT 8
239 #define OPP_NITRO_1GHZ_ZCZ_BIT 9
240
241 #define OPP_50_300MHZ_ZCE_BIT 5
242 #define OPP_100_600MHZ_ZCE_BIT 6
243
244
245 static struct omap_opp_def __initdata am33xx_es2_1_opp_list[] = {
246 /* MPU OPP1 - OPP50 */
247 OPP_INITIALIZER("mpu", false, 300000000,
248 AM33XX_ES2_1_VDD_MPU_OPP50_UV),
249 /* MPU OPP2 - OPP100 */
250 OPP_INITIALIZER("mpu", false, 600000000,
251 AM33XX_ES2_1_VDD_MPU_OPP100_UV),
252 /* MPU OPP3 - OPPTurbo */
253 OPP_INITIALIZER("mpu", false, 800000000,
254 AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV),
255 /* MPU OPP4 - OPPNitro */
256 OPP_INITIALIZER("mpu", false, 1000000000,
257 AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV),
258 };
259
260 /** 200 /**
261 * omap3_opp_init() - initialize omap3 opp table 201 * omap3_opp_init() - initialize omap3 opp table
262 */ 202 */
263 int __init omap3_opp_init(void) 203 int __init omap3_opp_init(void)
264 { 204 {
265 int r = -ENODEV; 205 int r = -ENODEV;
266 u32 rev, val, package_type, max_freq;
267 206
268 if (!cpu_is_omap34xx()) 207 if (!cpu_is_omap34xx())
269 return r; 208 return r;
270 209
271 if (cpu_is_omap3630()) 210 if (cpu_is_omap3630())
272 r = omap_init_opp_table(omap36xx_opp_def_list, 211 r = omap_init_opp_table(omap36xx_opp_def_list,
273 ARRAY_SIZE(omap36xx_opp_def_list)); 212 ARRAY_SIZE(omap36xx_opp_def_list));
274 else if (cpu_is_am33xx()) { 213 else if (cpu_is_am33xx()) {
275 rev = omap_rev(); 214 if (omap_rev() == AM335X_REV_ES1_0)
276 switch (rev) {
277 case AM335X_REV_ES1_0:
278 r = omap_init_opp_table(am33xx_es1_0_opp_def_list, 215 r = omap_init_opp_table(am33xx_es1_0_opp_def_list,
279 ARRAY_SIZE(am33xx_es1_0_opp_def_list)); 216 ARRAY_SIZE(am33xx_es1_0_opp_def_list));
280 break; 217 else
281
282 case AM335X_REV_ES2_1:
283 /*
284 * First read efuse sma reg to detect package type and
285 * supported frequency
286 */
287 val =
288 readl(AM33XX_CTRL_REGADDR(AM33XX_EFUSE_SMA_OFFSET));
289
290 package_type = (val >> PACKAGE_TYPE_SHFT) &
291 PACKAGE_TYPE_MASK;
292 max_freq = val & MAX_FREQ_MASK;
293
294 if (package_type == PACKAGE_TYPE_ZCZ) {
295 if (max_freq & OPP_50_300MHZ_ZCZ_BIT)
296 am33xx_es2_1_opp_list[OPP_50_INDEX].
297 default_available = true;
298
299 if (max_freq & OPP_100_600MHZ_ZCZ_BIT)
300 am33xx_es2_1_opp_list[OPP_100_INDEX].
301 default_available = true;
302
303 if (max_freq & OPP_TURBO_800MHZ_ZCZ_BIT)
304 am33xx_es2_1_opp_list[OPP_TURBO_INDEX].
305 default_available = true;
306
307 if (max_freq & OPP_NITRO_1GHZ_ZCZ_BIT)
308 am33xx_es2_1_opp_list[OPP_NITRO_INDEX].
309 default_available = true;
310 } else if (package_type == PACKAGE_TYPE_ZCE) {
311 if (max_freq & OPP_50_300MHZ_ZCE_BIT)
312 am33xx_es2_1_opp_list[OPP_50_INDEX].
313 default_available = true;
314
315 if (max_freq & OPP_100_600MHZ_ZCE_BIT)
316 am33xx_es2_1_opp_list[OPP_100_INDEX].
317 default_available = true;
318 } else {
319 /*
320 * if package type is not detected fall back to
321 * PG 2.0 OPP settings
322 */
323 r =
324 omap_init_opp_table(am33xx_es2_0_opp_def_list,
325 ARRAY_SIZE(am33xx_es2_0_opp_def_list));
326 break;
327 }
328
329 r = omap_init_opp_table(am33xx_es2_1_opp_list,
330 ARRAY_SIZE(am33xx_es2_1_opp_list));
331 break;
332
333 case AM335X_REV_ES2_0:
334 /* FALLTHROUGH */
335 default:
336 r = omap_init_opp_table(am33xx_es2_0_opp_def_list, 218 r = omap_init_opp_table(am33xx_es2_0_opp_def_list,
337 ARRAY_SIZE(am33xx_es2_0_opp_def_list)); 219 ARRAY_SIZE(am33xx_es2_0_opp_def_list));
338 } 220 }
339 } else { 221 else
340 r = omap_init_opp_table(omap34xx_opp_def_list, 222 r = omap_init_opp_table(omap34xx_opp_def_list,
341 ARRAY_SIZE(omap34xx_opp_def_list)); 223 ARRAY_SIZE(omap34xx_opp_def_list));
342 }
343 224
344 return r; 225 return r;
345 } 226 }
346 device_initcall(omap3_opp_init); 227 device_initcall(omap3_opp_init);
347 228