Blame view
include/fsl_ddr.h
4.74 KB
83d290c56 SPDX: Convert all... |
1 |
/* SPDX-License-Identifier: GPL-2.0 */ |
58e5e9aff FSL DDR: Rewrite ... |
2 |
/* |
34e026f9b driver/ddr/fsl: A... |
3 |
* Copyright 2008-2014 Freescale Semiconductor, Inc. |
58e5e9aff FSL DDR: Rewrite ... |
4 5 6 7 |
*/ #ifndef FSL_DDR_MAIN_H #define FSL_DDR_MAIN_H |
34e026f9b driver/ddr/fsl: A... |
8 |
#include <fsl_ddrc_version.h> |
5614e71b4 Driver/DDR: Movin... |
9 10 |
#include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> |
58e5e9aff FSL DDR: Rewrite ... |
11 |
|
5614e71b4 Driver/DDR: Movin... |
12 |
#include <common_timing_params.h> |
58e5e9aff FSL DDR: Rewrite ... |
13 |
|
1d71efbb0 driver/ddr: Restr... |
14 15 |
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS /* All controllers are for main memory */ |
51370d561 ddr: fsl: Merge m... |
16 |
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS |
1d71efbb0 driver/ddr: Restr... |
17 |
#endif |
4e5b1bd0d driver/ddr: Chang... |
18 19 20 |
#ifdef CONFIG_SYS_FSL_DDR_LE #define ddr_in32(a) in_le32(a) #define ddr_out32(a, v) out_le32(a, v) |
dda3b610e arm/ls1021a: Add ... |
21 22 23 |
#define ddr_setbits32(a, v) setbits_le32(a, v) #define ddr_clrbits32(a, v) clrbits_le32(a, v) #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) |
4e5b1bd0d driver/ddr: Chang... |
24 25 26 |
#else #define ddr_in32(a) in_be32(a) #define ddr_out32(a, v) out_be32(a, v) |
dda3b610e arm/ls1021a: Add ... |
27 28 29 |
#define ddr_setbits32(a, v) setbits_be32(a, v) #define ddr_clrbits32(a, v) clrbits_be32(a, v) #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) |
4e5b1bd0d driver/ddr: Chang... |
30 |
#endif |
66869f955 drivers/ddr/fsl: ... |
31 |
u32 fsl_ddr_get_version(unsigned int ctrl_num); |
34e026f9b driver/ddr/fsl: A... |
32 |
|
1b3e3c4f2 powerpc/mpc8xxx: ... |
33 |
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
58e5e9aff FSL DDR: Rewrite ... |
34 35 36 37 38 |
/* * Bind the main DDR setup driver's generic names * to this specific DDR technology. */ static __inline__ int |
03e664d8f driver/ddr/fsl: A... |
39 40 |
compute_dimm_parameters(const unsigned int ctrl_num, const generic_spd_eeprom_t *spd, |
58e5e9aff FSL DDR: Rewrite ... |
41 42 43 |
dimm_params_t *pdimm, unsigned int dimm_number) { |
03e664d8f driver/ddr/fsl: A... |
44 |
return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); |
58e5e9aff FSL DDR: Rewrite ... |
45 |
} |
1b3e3c4f2 powerpc/mpc8xxx: ... |
46 |
#endif |
58e5e9aff FSL DDR: Rewrite ... |
47 48 49 50 51 52 |
/* * Data Structures * * All data structures have to be on the stack */ |
6d0f6bcf3 rename CFG_ macro... |
53 |
#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR |
58e5e9aff FSL DDR: Rewrite ... |
54 55 56 |
typedef struct { generic_spd_eeprom_t |
6d0f6bcf3 rename CFG_ macro... |
57 |
spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; |
58e5e9aff FSL DDR: Rewrite ... |
58 |
struct dimm_params_s |
6d0f6bcf3 rename CFG_ macro... |
59 60 61 62 |
dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; |
1d71efbb0 driver/ddr: Restr... |
63 64 65 66 67 68 69 |
unsigned int first_ctrl; unsigned int num_ctrls; unsigned long long mem_base; unsigned int dimm_slots_per_ctrl; int (*board_need_mem_reset)(void); void (*board_mem_reset)(void); void (*board_mem_de_reset)(void); |
58e5e9aff FSL DDR: Rewrite ... |
70 71 72 73 74 75 76 77 78 79 80 |
} fsl_ddr_info_t; /* Compute steps */ #define STEP_GET_SPD (1 << 0) #define STEP_COMPUTE_DIMM_PARMS (1 << 1) #define STEP_COMPUTE_COMMON_PARMS (1 << 2) #define STEP_GATHER_OPTS (1 << 3) #define STEP_ASSIGN_ADDRESSES (1 << 4) #define STEP_COMPUTE_REGS (1 << 5) #define STEP_PROGRAM_REGS (1 << 6) #define STEP_ALL 0xFFF |
6f5e1dc53 powerpc/8xxx: Add... |
81 |
unsigned long long |
fc0c2b6fc 8xxx/ddr: add sup... |
82 83 |
fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only); |
6f5e1dc53 powerpc/8xxx: Add... |
84 |
const char *step_to_string(unsigned int step); |
58e5e9aff FSL DDR: Rewrite ... |
85 |
|
03e664d8f driver/ddr/fsl: A... |
86 87 |
unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, const memctl_options_t *popts, |
58e5e9aff FSL DDR: Rewrite ... |
88 89 90 |
fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, |
fc0c2b6fc 8xxx/ddr: add sup... |
91 92 |
unsigned int dbw_capacity_adjust, unsigned int size_only); |
6f5e1dc53 powerpc/8xxx: Add... |
93 |
unsigned int compute_lowest_common_dimm_parameters( |
03e664d8f driver/ddr/fsl: A... |
94 |
const unsigned int ctrl_num, |
6f5e1dc53 powerpc/8xxx: Add... |
95 96 97 |
const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms); |
56848428a drivers/ddr/fsl: ... |
98 |
unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, |
58e5e9aff FSL DDR: Rewrite ... |
99 |
memctl_options_t *popts, |
dfb49108e Pass dimm paramet... |
100 |
dimm_params_t *pdimm, |
58e5e9aff FSL DDR: Rewrite ... |
101 |
unsigned int ctrl_num); |
6f5e1dc53 powerpc/8xxx: Add... |
102 |
void check_interleaving_options(fsl_ddr_info_t *pinfo); |
58e5e9aff FSL DDR: Rewrite ... |
103 |
|
03e664d8f driver/ddr/fsl: A... |
104 105 106 |
unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); |
6f5e1dc53 powerpc/8xxx: Add... |
107 108 109 110 |
void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); |
e32d59a2f driver/ddr/fsl: A... |
111 112 |
void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, unsigned int last_ctrl); |
6f5e1dc53 powerpc/8xxx: Add... |
113 |
|
e8ba6c503 powerpc/mpc8xxxx:... |
114 115 |
int fsl_ddr_interactive_env_var_exists(void); unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); |
6f5e1dc53 powerpc/8xxx: Add... |
116 |
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
1d71efbb0 driver/ddr: Restr... |
117 |
unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); |
6f5e1dc53 powerpc/8xxx: Add... |
118 119 120 |
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); |
4e5b1bd0d driver/ddr: Chang... |
121 |
void board_add_ram_info(int use_default); |
6f5e1dc53 powerpc/8xxx: Add... |
122 123 124 |
/* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |
c63e13701 powerpc/mpc8xxx: ... |
125 |
unsigned int ctrl_num, int step); |
61bd2f75f drivers/ddr/fsl: ... |
126 |
void remove_unused_controllers(fsl_ddr_info_t *info); |
1b3e3c4f2 powerpc/mpc8xxx: ... |
127 128 129 130 131 |
/* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number); |
b92557cd3 driver/ddr/fsl: A... |
132 133 134 |
void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr); |
02fb27615 fsl/ddr: Add erra... |
135 136 |
void erratum_a009942_check_cpo(void); |
58e5e9aff FSL DDR: Rewrite ... |
137 |
#endif |