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include/fsl_ddr.h
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/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright 2008-2014 Freescale Semiconductor, Inc. |
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*/ #ifndef FSL_DDR_MAIN_H #define FSL_DDR_MAIN_H |
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#include <fsl_ddrc_version.h> |
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#include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> |
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#include <common_timing_params.h> |
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#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS /* All controllers are for main memory */ |
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS |
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#endif |
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#ifdef CONFIG_SYS_FSL_DDR_LE #define ddr_in32(a) in_le32(a) #define ddr_out32(a, v) out_le32(a, v) |
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#define ddr_setbits32(a, v) setbits_le32(a, v) #define ddr_clrbits32(a, v) clrbits_le32(a, v) #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) |
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#else #define ddr_in32(a) in_be32(a) #define ddr_out32(a, v) out_be32(a, v) |
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#define ddr_setbits32(a, v) setbits_be32(a, v) #define ddr_clrbits32(a, v) clrbits_be32(a, v) #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) |
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#endif |
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u32 fsl_ddr_get_version(unsigned int ctrl_num); |
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#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
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/* * Bind the main DDR setup driver's generic names * to this specific DDR technology. */ static __inline__ int |
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compute_dimm_parameters(const unsigned int ctrl_num, const generic_spd_eeprom_t *spd, |
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dimm_params_t *pdimm, unsigned int dimm_number) { |
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return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); |
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} |
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#endif |
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/* * Data Structures * * All data structures have to be on the stack */ |
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#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR |
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typedef struct { generic_spd_eeprom_t |
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spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; |
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struct dimm_params_s |
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dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; |
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unsigned int first_ctrl; unsigned int num_ctrls; unsigned long long mem_base; unsigned int dimm_slots_per_ctrl; int (*board_need_mem_reset)(void); void (*board_mem_reset)(void); void (*board_mem_de_reset)(void); |
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} fsl_ddr_info_t; /* Compute steps */ #define STEP_GET_SPD (1 << 0) #define STEP_COMPUTE_DIMM_PARMS (1 << 1) #define STEP_COMPUTE_COMMON_PARMS (1 << 2) #define STEP_GATHER_OPTS (1 << 3) #define STEP_ASSIGN_ADDRESSES (1 << 4) #define STEP_COMPUTE_REGS (1 << 5) #define STEP_PROGRAM_REGS (1 << 6) #define STEP_ALL 0xFFF |
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unsigned long long |
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fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only); |
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const char *step_to_string(unsigned int step); |
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unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, const memctl_options_t *popts, |
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fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, |
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unsigned int dbw_capacity_adjust, unsigned int size_only); |
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unsigned int compute_lowest_common_dimm_parameters( |
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const unsigned int ctrl_num, |
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const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms); |
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unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, |
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memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num); |
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void check_interleaving_options(fsl_ddr_info_t *pinfo); |
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unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); |
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void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); |
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void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, unsigned int last_ctrl); |
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int fsl_ddr_interactive_env_var_exists(void); unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); |
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
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unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); |
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); |
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void board_add_ram_info(int use_default); |
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/* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |
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unsigned int ctrl_num, int step); |
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void remove_unused_controllers(fsl_ddr_info_t *info); |
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/* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number); |
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void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr); |
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void erratum_a009942_check_cpo(void); |
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#endif |