Blame view
drivers/mtd/spi/sf_ops.c
9.43 KB
4d5e29a68 sf: Divide spi_fl... |
1 2 3 4 5 6 7 |
/* * SPI flash operations * * Copyright (C) 2008 Atmel Corporation * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. * |
0c88a84ac sf: Add GPL-2.0+ ... |
8 |
* SPDX-License-Identifier: GPL-2.0+ |
4d5e29a68 sf: Divide spi_fl... |
9 10 11 |
*/ #include <common.h> |
ff063ed48 sf: Discover read... |
12 |
#include <malloc.h> |
4d5e29a68 sf: Divide spi_fl... |
13 14 15 |
#include <spi.h> #include <spi_flash.h> #include <watchdog.h> |
898e76c93 sf: Rename spi_fl... |
16 |
#include "sf_internal.h" |
4d5e29a68 sf: Divide spi_fl... |
17 18 19 20 21 22 23 24 |
static void spi_flash_addr(u32 addr, u8 *cmd) { /* cmd[0] is actual command */ cmd[1] = addr >> 16; cmd[2] = addr >> 8; cmd[3] = addr >> 0; } |
9f4322fd2 sf: Divide flash ... |
25 |
int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) |
4d5e29a68 sf: Divide spi_fl... |
26 |
{ |
4d5e29a68 sf: Divide spi_fl... |
27 |
int ret; |
9f4322fd2 sf: Divide flash ... |
28 |
u8 cmd; |
4d5e29a68 sf: Divide spi_fl... |
29 |
|
9f4322fd2 sf: Divide flash ... |
30 31 |
cmd = CMD_READ_STATUS; ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); |
4d5e29a68 sf: Divide spi_fl... |
32 |
if (ret < 0) { |
9f4322fd2 sf: Divide flash ... |
33 34 |
debug("SF: fail to read status register "); |
4d5e29a68 sf: Divide spi_fl... |
35 36 37 38 39 |
return ret; } return 0; } |
9f4322fd2 sf: Divide flash ... |
40 |
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) |
067951223 sf: Add macronix ... |
41 |
{ |
067951223 sf: Add macronix ... |
42 43 |
u8 cmd; int ret; |
9f4322fd2 sf: Divide flash ... |
44 45 |
cmd = CMD_WRITE_STATUS; ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); |
067951223 sf: Add macronix ... |
46 |
if (ret < 0) { |
9f4322fd2 sf: Divide flash ... |
47 48 |
debug("SF: fail to write status register "); |
067951223 sf: Add macronix ... |
49 50 |
return ret; } |
9f4322fd2 sf: Divide flash ... |
51 |
return 0; |
067951223 sf: Add macronix ... |
52 |
} |
067951223 sf: Add macronix ... |
53 |
|
d08a1baf6 sf: Set quad enab... |
54 |
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) |
9f4322fd2 sf: Divide flash ... |
55 |
int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc) |
6cba6fdf9 sf: ops: Add conf... |
56 |
{ |
6cba6fdf9 sf: ops: Add conf... |
57 |
int ret; |
9f4322fd2 sf: Divide flash ... |
58 |
u8 cmd; |
6cba6fdf9 sf: ops: Add conf... |
59 |
|
9f4322fd2 sf: Divide flash ... |
60 61 |
cmd = CMD_READ_CONFIG; ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); |
6cba6fdf9 sf: ops: Add conf... |
62 |
if (ret < 0) { |
9f4322fd2 sf: Divide flash ... |
63 64 |
debug("SF: fail to read config register "); |
6cba6fdf9 sf: ops: Add conf... |
65 66 67 68 69 |
return ret; } return 0; } |
9f4322fd2 sf: Divide flash ... |
70 |
int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) |
d08a1baf6 sf: Set quad enab... |
71 |
{ |
9f4322fd2 sf: Divide flash ... |
72 |
u8 data[2]; |
d08a1baf6 sf: Set quad enab... |
73 74 |
u8 cmd; int ret; |
9f4322fd2 sf: Divide flash ... |
75 76 |
ret = spi_flash_cmd_read_status(flash, &data[0]); if (ret < 0) |
d08a1baf6 sf: Set quad enab... |
77 |
return ret; |
d08a1baf6 sf: Set quad enab... |
78 |
|
9f4322fd2 sf: Divide flash ... |
79 80 81 82 83 84 85 |
cmd = CMD_WRITE_STATUS; data[1] = wc; ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); if (ret) { debug("SF: fail to write config register "); return ret; |
d08a1baf6 sf: Set quad enab... |
86 |
} |
9f4322fd2 sf: Divide flash ... |
87 |
return 0; |
d08a1baf6 sf: Set quad enab... |
88 89 |
} #endif |
4d5e29a68 sf: Divide spi_fl... |
90 |
#ifdef CONFIG_SPI_FLASH_BAR |
532f2f111 sf: ops: Add stat... |
91 |
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) |
4d5e29a68 sf: Divide spi_fl... |
92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 |
{ u8 cmd; int ret; if (flash->bank_curr == bank_sel) { debug("SF: not require to enable bank%d ", bank_sel); return 0; } cmd = flash->bank_write_cmd; ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); if (ret < 0) { debug("SF: fail to write bank register "); return ret; } flash->bank_curr = bank_sel; return 0; } |
6152dd152 sf_ops: Unify ban... |
113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 |
static int spi_flash_bank(struct spi_flash *flash, u32 offset) { u8 bank_sel; int ret; bank_sel = offset / SPI_FLASH_16MB_BOUN; ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); if (ret) { debug("SF: fail to set bank%d ", bank_sel); return ret; } return 0; } |
4d5e29a68 sf: Divide spi_fl... |
130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 |
#endif int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { struct spi_slave *spi = flash->spi; unsigned long timebase; int ret; u8 status; u8 check_status = 0x0; u8 poll_bit = STATUS_WIP; u8 cmd = flash->poll_cmd; if (cmd == CMD_FLAG_STATUS) { poll_bit = STATUS_PEC; check_status = poll_bit; } ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); if (ret) { debug("SF: fail to read %s status register ", cmd == CMD_READ_STATUS ? "read" : "flag"); return ret; } timebase = get_timer(0); do { WATCHDOG_RESET(); ret = spi_xfer(spi, 8, NULL, &status, 0); if (ret) return -1; if ((status & poll_bit) == check_status) break; } while (get_timer(timebase) < timeout); spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); if ((status & poll_bit) == check_status) return 0; /* Timed out */ debug("SF: time out! "); return -1; } int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, size_t cmd_len, const void *buf, size_t buf_len) { struct spi_slave *spi = flash->spi; unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; int ret; if (buf == NULL) timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; ret = spi_claim_bus(flash->spi); if (ret) { debug("SF: unable to claim SPI bus "); return ret; } ret = spi_flash_cmd_write_enable(flash); if (ret < 0) { debug("SF: enabling write failed "); return ret; } ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); if (ret < 0) { debug("SF: write cmd failed "); return ret; } ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { debug("SF: write %s timed out ", timeout == SPI_FLASH_PROG_TIMEOUT ? "program" : "page erase"); return ret; } spi_release_bus(spi); return ret; } |
a5e8199a1 sf: spi_flash cle... |
223 |
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) |
4d5e29a68 sf: Divide spi_fl... |
224 225 |
{ u32 erase_size; |
ff063ed48 sf: Discover read... |
226 |
u8 cmd[SPI_FLASH_CMD_LEN]; |
4d5e29a68 sf: Divide spi_fl... |
227 |
int ret = -1; |
f4f51a8ff sf: probe: Add su... |
228 |
erase_size = flash->erase_size; |
4d5e29a68 sf: Divide spi_fl... |
229 230 231 232 233 |
if (offset % erase_size || len % erase_size) { debug("SF: Erase offset/length not multiple of erase size "); return -1; } |
f4f51a8ff sf: probe: Add su... |
234 |
cmd[0] = flash->erase_cmd; |
4d5e29a68 sf: Divide spi_fl... |
235 236 |
while (len) { #ifdef CONFIG_SPI_FLASH_BAR |
6152dd152 sf_ops: Unify ban... |
237 238 |
ret = spi_flash_bank(flash, offset); if (ret < 0) |
4d5e29a68 sf: Divide spi_fl... |
239 |
return ret; |
4d5e29a68 sf: Divide spi_fl... |
240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 |
#endif spi_flash_addr(offset, cmd); debug("SF: erase %2x %2x %2x %2x (%x) ", cmd[0], cmd[1], cmd[2], cmd[3], offset); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); if (ret < 0) { debug("SF: erase failed "); break; } offset += erase_size; len -= erase_size; } return ret; } |
a5e8199a1 sf: spi_flash cle... |
260 |
int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, |
4d5e29a68 sf: Divide spi_fl... |
261 262 263 264 |
size_t len, const void *buf) { unsigned long byte_addr, page_size; size_t chunk_len, actual; |
ff063ed48 sf: Discover read... |
265 |
u8 cmd[SPI_FLASH_CMD_LEN]; |
4d5e29a68 sf: Divide spi_fl... |
266 267 268 |
int ret = -1; page_size = flash->page_size; |
3163aaa63 sf: Add quad read... |
269 |
cmd[0] = flash->write_cmd; |
4d5e29a68 sf: Divide spi_fl... |
270 271 |
for (actual = 0; actual < len; actual += chunk_len) { #ifdef CONFIG_SPI_FLASH_BAR |
6152dd152 sf_ops: Unify ban... |
272 273 |
ret = spi_flash_bank(flash, offset); if (ret < 0) |
4d5e29a68 sf: Divide spi_fl... |
274 |
return ret; |
4d5e29a68 sf: Divide spi_fl... |
275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 |
#endif byte_addr = offset % page_size; chunk_len = min(len - actual, page_size - byte_addr); if (flash->spi->max_write_size) chunk_len = min(chunk_len, flash->spi->max_write_size); spi_flash_addr(offset, cmd); debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu ", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { debug("SF: write failed "); break; } offset += chunk_len; } return ret; } int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, size_t cmd_len, void *data, size_t data_len) { struct spi_slave *spi = flash->spi; int ret; ret = spi_claim_bus(flash->spi); if (ret) { debug("SF: unable to claim SPI bus "); return ret; } ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); if (ret < 0) { debug("SF: read cmd failed "); return ret; } spi_release_bus(spi); return ret; } |
a5e8199a1 sf: spi_flash cle... |
326 |
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, |
4d5e29a68 sf: Divide spi_fl... |
327 328 |
size_t len, void *data) { |
ff063ed48 sf: Discover read... |
329 |
u8 *cmd, cmdsz, bank_sel = 0; |
4d5e29a68 sf: Divide spi_fl... |
330 331 332 333 334 |
u32 remain_len, read_len; int ret = -1; /* Handle memory-mapped SPI */ if (flash->memory_map) { |
ac5cce38d driver: mtd: sf_o... |
335 336 337 338 339 340 |
ret = spi_claim_bus(flash->spi); if (ret) { debug("SF: unable to claim SPI bus "); return ret; } |
004f15b60 sf: Add memory ma... |
341 |
spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP); |
4d5e29a68 sf: Divide spi_fl... |
342 |
memcpy(data, flash->memory_map + offset, len); |
004f15b60 sf: Add memory ma... |
343 |
spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END); |
ac5cce38d driver: mtd: sf_o... |
344 |
spi_release_bus(flash->spi); |
4d5e29a68 sf: Divide spi_fl... |
345 346 |
return 0; } |
ff063ed48 sf: Discover read... |
347 348 349 |
cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; cmd = malloc(cmdsz); memset(cmd, 0, cmdsz); |
4d5e29a68 sf: Divide spi_fl... |
350 |
|
ff063ed48 sf: Discover read... |
351 |
cmd[0] = flash->read_cmd; |
4d5e29a68 sf: Divide spi_fl... |
352 353 354 355 356 357 358 359 360 361 362 |
while (len) { #ifdef CONFIG_SPI_FLASH_BAR bank_sel = offset / SPI_FLASH_16MB_BOUN; ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); if (ret) { debug("SF: fail to set bank%d ", bank_sel); return ret; } #endif |
469146c09 sf: Minor cleanups. |
363 |
remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; |
4d5e29a68 sf: Divide spi_fl... |
364 365 366 367 368 369 |
if (len < remain_len) read_len = len; else read_len = remain_len; spi_flash_addr(offset, cmd); |
ff063ed48 sf: Discover read... |
370 |
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); |
4d5e29a68 sf: Divide spi_fl... |
371 372 373 374 375 376 377 378 379 380 381 382 383 |
if (ret < 0) { debug("SF: read failed "); break; } offset += read_len; len -= read_len; data += read_len; } return ret; } |
10ca45d00 sf: probe: Add su... |
384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 |
#ifdef CONFIG_SPI_FLASH_SST static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) { int ret; u8 cmd[4] = { CMD_SST_BP, offset >> 16, offset >> 8, offset, }; debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x } ", spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); ret = spi_flash_cmd_write_enable(flash); if (ret) return ret; ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); if (ret) return ret; return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); } int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { size_t actual, cmd_len; int ret; u8 cmd[4]; ret = spi_claim_bus(flash->spi); if (ret) { debug("SF: Unable to claim SPI bus "); return ret; } /* If the data is not word aligned, write out leading single byte */ actual = offset % 2; if (actual) { ret = sst_byte_write(flash, offset, buf); if (ret) goto done; } offset += actual; ret = spi_flash_cmd_write_enable(flash); if (ret) goto done; cmd_len = 4; cmd[0] = CMD_SST_AAI_WP; cmd[1] = offset >> 16; cmd[2] = offset >> 8; cmd[3] = offset; for (; actual < len - 1; actual += 2) { debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x } ", spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0], offset); ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf + actual, 2); if (ret) { debug("SF: sst word program failed "); break; } ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); if (ret) break; cmd_len = 1; offset += 2; } if (!ret) ret = spi_flash_cmd_write_disable(flash); /* If there is a single trailing byte, write it out */ if (!ret && actual != len) ret = sst_byte_write(flash, offset, buf + actual); done: debug("SF: sst: program %s %zu bytes @ 0x%zx ", ret ? "failure" : "success", len, offset - actual); spi_release_bus(flash->spi); return ret; } #endif |