Blame view
include/spartan2.h
3.21 KB
c609719b8
|
1 2 3 4 |
/* * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * |
1a4596601
|
5 |
* SPDX-License-Identifier: GPL-2.0+ |
c609719b8
|
6 7 8 9 10 11 |
*/ #ifndef _SPARTAN2_H_ #define _SPARTAN2_H_ #include <xilinx.h> |
c609719b8
|
12 13 |
/* Slave Parallel Implementation function table */ typedef struct { |
2df9d5c43
|
14 15 16 17 18 19 20 21 22 23 24 25 26 |
xilinx_pre_fn pre; xilinx_pgm_fn pgm; xilinx_init_fn init; xilinx_err_fn err; xilinx_done_fn done; xilinx_clk_fn clk; xilinx_cs_fn cs; xilinx_wr_fn wr; xilinx_rdata_fn rdata; xilinx_wdata_fn wdata; xilinx_busy_fn busy; xilinx_abort_fn abort; xilinx_post_fn post; |
b625b9aef
|
27 |
} xilinx_spartan2_slave_parallel_fns; |
c609719b8
|
28 29 30 |
/* Slave Serial Implementation function table */ typedef struct { |
2df9d5c43
|
31 32 33 34 35 36 37 |
xilinx_pre_fn pre; xilinx_pgm_fn pgm; xilinx_clk_fn clk; xilinx_init_fn init; xilinx_done_fn done; xilinx_wr_fn wr; xilinx_post_fn post; |
b625b9aef
|
38 |
} xilinx_spartan2_slave_serial_fns; |
c609719b8
|
39 |
|
4e9acc16f
|
40 |
#if defined(CONFIG_FPGA_SPARTAN2) |
14cfc4f37
|
41 |
extern struct xilinx_fpga_op spartan2_op; |
4e9acc16f
|
42 43 44 45 |
# define FPGA_SPARTAN2_OPS &spartan2_op #else # define FPGA_SPARTAN2_OPS NULL #endif |
14cfc4f37
|
46 |
|
c609719b8
|
47 48 49 |
/* Device Image Sizes *********************************************************************/ /* Spartan-II (2.5V) */ |
53677ef18
|
50 51 52 53 54 55 |
#define XILINX_XC2S15_SIZE 197728/8 #define XILINX_XC2S30_SIZE 336800/8 #define XILINX_XC2S50_SIZE 559232/8 #define XILINX_XC2S100_SIZE 781248/8 #define XILINX_XC2S150_SIZE 1040128/8 #define XILINX_XC2S200_SIZE 1335872/8 |
c609719b8
|
56 |
|
9dd611b8c
|
57 58 59 60 61 62 |
/* Spartan-IIE (1.8V) */ #define XILINX_XC2S50E_SIZE 630048/8 #define XILINX_XC2S100E_SIZE 863840/8 #define XILINX_XC2S150E_SIZE 1134496/8 #define XILINX_XC2S200E_SIZE 1442016/8 #define XILINX_XC2S300E_SIZE 1875648/8 |
c609719b8
|
63 64 65 66 |
/* Descriptor Macros *********************************************************************/ /* Spartan-II devices */ #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
67 68 |
{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
c609719b8
|
69 70 |
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
71 72 |
{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
c609719b8
|
73 74 |
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
75 76 |
{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
c609719b8
|
77 78 |
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
79 80 |
{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
c609719b8
|
81 82 |
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
83 84 |
{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
c609719b8
|
85 |
|
3bff4ffa3
|
86 |
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
87 88 |
{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
3bff4ffa3
|
89 |
|
9dd611b8c
|
90 |
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
91 92 |
{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
9dd611b8c
|
93 94 |
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
95 96 |
{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
9dd611b8c
|
97 98 |
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
99 100 |
{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
9dd611b8c
|
101 102 |
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
103 104 |
{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
9dd611b8c
|
105 106 |
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ |
4e9acc16f
|
107 108 |
{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \ FPGA_SPARTAN2_OPS } |
9dd611b8c
|
109 |
|
c609719b8
|
110 |
#endif /* _SPARTAN2_H_ */ |