Eric Lee / smarc-uboot

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Commit 42f01aacfd508ddaab5fbc21dd1d3c04dcf61990

Authored by Patrick Delaunay
1 parent d46c22b3fd
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

power: rename stpmu1 to official name stpmic1 

Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>

Showing 15 changed files with 446 additions and 444 deletions Side-by-side Diff

... ... @@ -295,7 +295,9 @@
295 295 F: drivers/mmc/stm32_sdmmc2.c
296 296 F: drivers/phy/phy-stm32-usbphyc.c
297 297 F: drivers/pinctrl/pinctrl_stm32.c
  298 +F: drivers/power/pmic/stpmic1.c
298 299 F: drivers/power/regulator/stm32-vrefbuf.c
  300 +F: drivers/power/regulator/stpmic1.c
299 301 F: drivers/ram/stm32mp1/
300 302 F: drivers/misc/stm32_rcc.c
301 303 F: drivers/reset/stm32-reset.c
arch/arm/dts/stm32mp157c-ed1.dts
Diff comments   View file @ 42f01aa
... ... @@ -54,8 +54,8 @@
54 54 i2c-scl-falling-time-ns = <20>;
55 55 status = "okay";
56 56  
57   - pmic: stpmu1@33 {
58   - compatible = "st,stpmu1";
  57 + pmic: stpmic1@33 {
  58 + compatible = "st,stpmic1";
59 59 reg = <0x33>;
60 60 interrupts = <0 2>;
61 61 interrupt-parent = <&gpioa>;
... ... @@ -68,7 +68,7 @@
68 68 st,usb_control_register = <0x30>;
69 69  
70 70 regulators {
71   - compatible = "st,stpmu1-regulators";
  71 + compatible = "st,stpmic1-regulators";
72 72  
73 73 ldo1-supply = <&v3v3>;
74 74 ldo2-supply = <&v3v3>;
board/st/stm32mp1/README
Diff comments   View file @ 42f01aa
... ... @@ -28,7 +28,7 @@
28 28  
29 29 And the necessary drivers
30 30 1. I2C
31   -2. STPMU1 (PMIC and regulator)
  31 +2. STPMIC1 (PMIC and regulator)
32 32 3. Clock, Reset, Sysreset
33 33 4. Fuse
34 34  
35 35  
... ... @@ -70,10 +70,10 @@
70 70 You need to select the appropriate device tree for your board,
71 71 the supported device trees for stm32mp157 are:
72 72  
73   -+ ev1: eval board with pmic stpmu1 (ev1 = mother board + daughter ed1)
  73 ++ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
74 74 dts: stm32mp157c-ev1
75 75  
76   -+ ed1: daughter board with pmic stpmu1
  76 ++ ed1: daughter board with pmic stpmic1
77 77 dts: stm32mp157c-ed1
78 78  
79 79 5. Build Procedure
board/st/stm32mp1/board.c
Diff comments   View file @ 42f01aa
... ... @@ -37,64 +37,65 @@
37 37 }
38 38 #endif
39 39  
40   -#ifdef CONFIG_PMIC_STPMU1
  40 +#ifdef CONFIG_PMIC_STPMIC1
41 41 int board_ddr_power_init(void)
42 42 {
43 43 struct udevice *dev;
44 44 int ret;
45 45  
46 46 ret = uclass_get_device_by_driver(UCLASS_PMIC,
47   - DM_GET_DRIVER(pmic_stpmu1), &dev);
  47 + DM_GET_DRIVER(pmic_stpmic1), &dev);
48 48 if (ret)
49 49 /* No PMIC on board */
50 50 return 0;
51 51  
52   - /* Set LDO3 to sync mode */
53   - ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
  52 + /* VTT = Set LDO3 to sync mode */
  53 + ret = pmic_reg_read(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3));
54 54 if (ret < 0)
55 55 return ret;
56 56  
57   - ret &= ~STPMU1_LDO3_MODE;
58   - ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
59   - ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
  57 + ret &= ~STPMIC1_LDO3_MODE;
  58 + ret &= ~STPMIC1_LDO12356_OUTPUT_MASK;
  59 + ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_OUTPUT_SHIFT;
60 60  
61   - ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
  61 + ret = pmic_reg_write(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
62 62 ret);
63 63 if (ret < 0)
64 64 return ret;
65 65  
66   - /* Set BUCK2 to 1.35V */
  66 + /* VDD_DDR = Set BUCK2 to 1.35V */
67 67 ret = pmic_clrsetbits(dev,
68   - STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
69   - STPMU1_BUCK_OUTPUT_MASK,
70   - STPMU1_BUCK2_1350000V);
  68 + STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
  69 + STPMIC1_BUCK_OUTPUT_MASK,
  70 + STPMIC1_BUCK2_1350000V);
71 71 if (ret < 0)
72 72 return ret;
73 73  
74   - /* Enable BUCK2 and VREF */
  74 + /* Enable VDD_DDR = BUCK2 */
75 75 ret = pmic_clrsetbits(dev,
76   - STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
77   - STPMU1_BUCK_EN, STPMU1_BUCK_EN);
  76 + STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
  77 + STPMIC1_BUCK_EN, STPMIC1_BUCK_EN);
78 78 if (ret < 0)
79 79 return ret;
80 80  
81   - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
  81 + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
82 82  
83   - ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
84   - STPMU1_VREF_EN, STPMU1_VREF_EN);
  83 + /* Enable VREF */
  84 + ret = pmic_clrsetbits(dev, STPMIC1_VREF_CTRL_REG,
  85 + STPMIC1_VREF_EN, STPMIC1_VREF_EN);
85 86 if (ret < 0)
86 87 return ret;
87 88  
88   - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
  89 + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
89 90  
90 91 /* Enable LDO3 */
91 92 ret = pmic_clrsetbits(dev,
92   - STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
93   - STPMU1_LDO_EN, STPMU1_LDO_EN);
  93 + STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
  94 + STPMIC1_LDO_EN, STPMIC1_LDO_EN);
94 95 if (ret < 0)
95 96 return ret;
96 97  
97   - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
  98 + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
98 99  
99 100 return 0;
100 101 }
board/st/stm32mp1/spl.c
Diff comments   View file @ 42f01aa
... ... @@ -17,17 +17,17 @@
17 17 void spl_board_init(void)
18 18 {
19 19 /* Keep vdd on during the reset cycle */
20   -#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT)
  20 +#if defined(CONFIG_PMIC_STPMIC1) && defined(CONFIG_SPL_POWER_SUPPORT)
21 21 struct udevice *dev;
22 22 int ret;
23 23  
24 24 ret = uclass_get_device_by_driver(UCLASS_PMIC,
25   - DM_GET_DRIVER(pmic_stpmu1), &dev);
  25 + DM_GET_DRIVER(pmic_stpmic1), &dev);
26 26 if (!ret)
27 27 pmic_clrsetbits(dev,
28   - STPMU1_MASK_RESET_BUCK,
29   - STPMU1_MASK_RESET_BUCK3,
30   - STPMU1_MASK_RESET_BUCK3);
  28 + STPMIC1_MASK_RESET_BUCK,
  29 + STPMIC1_MASK_RESET_BUCK3,
  30 + STPMIC1_MASK_RESET_BUCK3);
31 31 #endif
32 32 }
configs/stm32mp15_basic_defconfig
Diff comments   View file @ 42f01aa
... ... @@ -59,11 +59,11 @@
59 59 # CONFIG_SPL_PINCTRL_FULL is not set
60 60 CONFIG_DM_PMIC=y
61 61 # CONFIG_SPL_PMIC_CHILDREN is not set
62   -CONFIG_PMIC_STPMU1=y
  62 +CONFIG_PMIC_STPMIC1=y
63 63 CONFIG_DM_REGULATOR_FIXED=y
64 64 CONFIG_DM_REGULATOR_GPIO=y
65 65 CONFIG_DM_REGULATOR_STM32_VREFBUF=y
66   -CONFIG_DM_REGULATOR_STPMU1=y
  66 +CONFIG_DM_REGULATOR_STPMIC1=y
67 67 CONFIG_SERIAL_RX_BUFFER=y
68 68 CONFIG_STM32_SERIAL=y
69 69 CONFIG_USB=y
configs/stm32mp15_trusted_defconfig
Diff comments   View file @ 42f01aa
... ... @@ -50,11 +50,11 @@
50 50 CONFIG_PHY_STM32_USBPHYC=y
51 51 # CONFIG_PINCTRL_FULL is not set
52 52 CONFIG_DM_PMIC=y
53   -CONFIG_PMIC_STPMU1=y
  53 +CONFIG_PMIC_STPMIC1=y
54 54 CONFIG_DM_REGULATOR_FIXED=y
55 55 CONFIG_DM_REGULATOR_GPIO=y
56 56 CONFIG_DM_REGULATOR_STM32_VREFBUF=y
57   -CONFIG_DM_REGULATOR_STPMU1=y
  57 +CONFIG_DM_REGULATOR_STPMIC1=y
58 58 CONFIG_SERIAL_RX_BUFFER=y
59 59 CONFIG_STM32_SERIAL=y
60 60 CONFIG_USB=y
drivers/power/pmic/Kconfig
Diff comments   View file @ 42f01aa
... ... @@ -231,11 +231,11 @@
231 231 DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
232 232 pmic children.
233 233  
234   -config PMIC_STPMU1
235   - bool "Enable support for STMicroelectronics STPMU1 PMIC"
  234 +config PMIC_STPMIC1
  235 + bool "Enable support for STMicroelectronics STPMIC1 PMIC"
236 236 depends on DM_PMIC && DM_I2C
237 237 ---help---
238   - The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
  238 + The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
239 239 It is accessed via an I2C interface. The device is used with STM32MP1
240 240 SoCs. This driver implements register read/write operations.
drivers/power/pmic/Makefile
Diff comments   View file @ 42f01aa
... ... @@ -23,7 +23,7 @@
23 23 obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
24 24 obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
25 25 obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
26   -obj-$(CONFIG_PMIC_STPMU1) += stpmic1.o
  26 +obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
27 27  
28 28 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
29 29 obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
drivers/power/pmic/stpmic1.c
Diff comments   View file @ 42f01aa
... ... @@ -10,26 +10,26 @@
10 10 #include <power/pmic.h>
11 11 #include <power/stpmic1.h>
12 12  
13   -#define STMPU1_NUM_OF_REGS 0x100
  13 +#define STPMIC1_NUM_OF_REGS 0x100
14 14  
15   -#ifndef CONFIG_SPL_BUILD
16   -static const struct pmic_child_info stpmu1_children_info[] = {
17   - { .prefix = "ldo", .driver = "stpmu1_ldo" },
18   - { .prefix = "buck", .driver = "stpmu1_buck" },
19   - { .prefix = "vref_ddr", .driver = "stpmu1_vref_ddr" },
20   - { .prefix = "pwr_sw", .driver = "stpmu1_pwr_sw" },
21   - { .prefix = "boost", .driver = "stpmu1_boost" },
  15 +#if CONFIG_IS_ENABLED(DM_REGULATOR)
  16 +static const struct pmic_child_info stpmic1_children_info[] = {
  17 + { .prefix = "ldo", .driver = "stpmic1_ldo" },
  18 + { .prefix = "buck", .driver = "stpmic1_buck" },
  19 + { .prefix = "vref_ddr", .driver = "stpmic1_vref_ddr" },
  20 + { .prefix = "pwr_sw", .driver = "stpmic1_pwr_sw" },
  21 + { .prefix = "boost", .driver = "stpmic1_boost" },
22 22 { },
23 23 };
24   -#endif /* CONFIG_SPL_BUILD */
  24 +#endif /* DM_REGULATOR */
25 25  
26   -static int stpmu1_reg_count(struct udevice *dev)
  26 +static int stpmic1_reg_count(struct udevice *dev)
27 27 {
28   - return STMPU1_NUM_OF_REGS;
  28 + return STPMIC1_NUM_OF_REGS;
29 29 }
30 30  
31   -static int stpmu1_write(struct udevice *dev, uint reg, const uint8_t *buff,
32   - int len)
  31 +static int stpmic1_write(struct udevice *dev, uint reg, const uint8_t *buff,
  32 + int len)
33 33 {
34 34 int ret;
35 35  
... ... @@ -41,7 +41,7 @@
41 41 return ret;
42 42 }
43 43  
44   -static int stpmu1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
  44 +static int stpmic1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
45 45 {
46 46 int ret;
47 47  
48 48  
49 49  
50 50  
51 51  
52 52  
53 53  
54 54  
55 55  
... ... @@ -53,44 +53,44 @@
53 53 return ret;
54 54 }
55 55  
56   -static int stpmu1_bind(struct udevice *dev)
  56 +static int stpmic1_bind(struct udevice *dev)
57 57 {
58   -#ifndef CONFIG_SPL_BUILD
  58 +#if CONFIG_IS_ENABLED(DM_REGULATOR)
59 59 ofnode regulators_node;
60 60 int children;
61 61  
62 62 regulators_node = dev_read_subnode(dev, "regulators");
63 63 if (!ofnode_valid(regulators_node)) {
64   - dev_dbg(dev, "regulators subnode not found!\n");
  64 + dev_dbg(dev, "regulators subnode not found!");
65 65 return -ENXIO;
66 66 }
67 67 dev_dbg(dev, "found regulators subnode\n");
68 68  
69 69 children = pmic_bind_children(dev, regulators_node,
70   - stpmu1_children_info);
  70 + stpmic1_children_info);
71 71 if (!children)
72 72 dev_dbg(dev, "no child found\n");
73   -#endif /* CONFIG_SPL_BUILD */
  73 +#endif /* DM_REGULATOR */
74 74  
75 75 return 0;
76 76 }
77 77  
78   -static struct dm_pmic_ops stpmu1_ops = {
79   - .reg_count = stpmu1_reg_count,
80   - .read = stpmu1_read,
81   - .write = stpmu1_write,
  78 +static struct dm_pmic_ops stpmic1_ops = {
  79 + .reg_count = stpmic1_reg_count,
  80 + .read = stpmic1_read,
  81 + .write = stpmic1_write,
82 82 };
83 83  
84   -static const struct udevice_id stpmu1_ids[] = {
85   - { .compatible = "st,stpmu1" },
  84 +static const struct udevice_id stpmic1_ids[] = {
  85 + { .compatible = "st,stpmic1" },
86 86 { }
87 87 };
88 88  
89   -U_BOOT_DRIVER(pmic_stpmu1) = {
90   - .name = "stpmu1_pmic",
  89 +U_BOOT_DRIVER(pmic_stpmic1) = {
  90 + .name = "stpmic1_pmic",
91 91 .id = UCLASS_PMIC,
92   - .of_match = stpmu1_ids,
93   - .bind = stpmu1_bind,
94   - .ops = &stpmu1_ops,
  92 + .of_match = stpmic1_ids,
  93 + .bind = stpmic1_bind,
  94 + .ops = &stpmic1_ops,
95 95 };
drivers/power/regulator/Kconfig
Diff comments   View file @ 42f01aa
... ... @@ -244,12 +244,18 @@
244 244 regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements
245 245 the get/set api for value and enable.
246 246  
247   -config DM_REGULATOR_STPMU1
248   - bool "Enable driver for STPMU1 regulators"
249   - depends on DM_REGULATOR && PMIC_STPMU1
  247 +config DM_REGULATOR_STPMIC1
  248 + bool "Enable driver for STPMIC1 regulators"
  249 + depends on DM_REGULATOR && PMIC_STPMIC1
250 250 ---help---
251   - Enable support for the regulator functions of the STPMU1 PMIC. The
  251 + Enable support for the regulator functions of the STPMIC1 PMIC. The
252 252 driver implements get/set api for the various BUCKS and LDOs supported
253 253 by the PMIC device. This driver is controlled by a device tree node
254 254 which includes voltage limits.
  255 +
  256 +config SPL_DM_REGULATOR_STPMIC1
  257 + bool "Enable driver for STPMIC1 regulators in SPL"
  258 + depends on SPL_DM_REGULATOR && PMIC_STPMIC1
  259 + help
  260 + Enable support for the regulator functions of the STPMIC1 PMIC in SPL.
drivers/power/regulator/Makefile
Diff comments   View file @ 42f01aa
... ... @@ -24,5 +24,5 @@
24 24 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
25 25 obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
26 26 obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
27   -obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMU1) += stpmic1.o
  27 +obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o
drivers/power/regulator/stpmic1.c
Diff comments   View file @ 42f01aa
... ... @@ -11,44 +11,44 @@
11 11 #include <power/regulator.h>
12 12 #include <power/stpmic1.h>
13 13  
14   -struct stpmu1_range {
  14 +struct stpmic1_range {
15 15 int min_uv;
16 16 int min_sel;
17 17 int max_sel;
18 18 int step;
19 19 };
20 20  
21   -struct stpmu1_output_range {
22   - const struct stpmu1_range *ranges;
  21 +struct stpmic1_output {
  22 + const struct stpmic1_range *ranges;
23 23 int nbranges;
24 24 };
25 25  
26   -#define STPMU1_MODE(_id, _val, _name) { \
  26 +#define STPMIC1_MODE(_id, _val, _name) { \
27 27 .id = _id, \
28 28 .register_value = _val, \
29 29 .name = _name, \
30 30 }
31 31  
32   -#define STPMU1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \
  32 +#define STPMIC1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \
33 33 .min_uv = _min_uv, \
34 34 .min_sel = _min_sel, \
35 35 .max_sel = _max_sel, \
36 36 .step = _step, \
37 37 }
38 38  
39   -#define STPMU1_OUTPUT_RANGE(_ranges, _nbranges) { \
  39 +#define STPMIC1_OUTPUT(_ranges, _nbranges) { \
40 40 .ranges = _ranges, \
41 41 .nbranges = _nbranges, \
42 42 }
43 43  
44   -static int stpmu1_output_find_uv(int sel,
45   - const struct stpmu1_output_range *output_range)
  44 +static int stpmic1_output_find_uv(int sel,
  45 + const struct stpmic1_output *output)
46 46 {
47   - const struct stpmu1_range *range;
  47 + const struct stpmic1_range *range;
48 48 int i;
49 49  
50   - for (i = 0, range = output_range->ranges;
51   - i < output_range->nbranges; i++, range++) {
  50 + for (i = 0, range = output->ranges;
  51 + i < output->nbranges; i++, range++) {
52 52 if (sel >= range->min_sel && sel <= range->max_sel)
53 53 return range->min_uv +
54 54 (sel - range->min_sel) * range->step;
55 55  
56 56  
... ... @@ -57,14 +57,14 @@
57 57 return -EINVAL;
58 58 }
59 59  
60   -static int stpmu1_output_find_sel(int uv,
61   - const struct stpmu1_output_range *output_range)
  60 +static int stpmic1_output_find_sel(int uv,
  61 + const struct stpmic1_output *output)
62 62 {
63   - const struct stpmu1_range *range;
  63 + const struct stpmic1_range *range;
64 64 int i;
65 65  
66   - for (i = 0, range = output_range->ranges;
67   - i < output_range->nbranges; i++, range++) {
  66 + for (i = 0, range = output->ranges;
  67 + i < output->nbranges; i++, range++) {
68 68 if (uv == range->min_uv && !range->step)
69 69 return range->min_sel;
70 70  
71 71  
72 72  
73 73  
74 74  
75 75  
76 76  
77 77  
78 78  
79 79  
80 80  
81 81  
82 82  
83 83  
84 84  
85 85  
86 86  
87 87  
88 88  
89 89  
90 90  
91 91  
92 92  
93 93  
94 94  
95 95  
96 96  
97 97  
98 98  
99 99  
... ... @@ -82,157 +82,157 @@
82 82 * BUCK regulators
83 83 */
84 84  
85   -static const struct stpmu1_range buck1_ranges[] = {
86   - STPMU1_RANGE(725000, 0, 4, 0),
87   - STPMU1_RANGE(725000, 5, 36, 25000),
88   - STPMU1_RANGE(1500000, 37, 63, 0),
  85 +static const struct stpmic1_range buck1_ranges[] = {
  86 + STPMIC1_RANGE(725000, 0, 4, 0),
  87 + STPMIC1_RANGE(725000, 5, 36, 25000),
  88 + STPMIC1_RANGE(1500000, 37, 63, 0),
89 89 };
90 90  
91   -static const struct stpmu1_range buck2_ranges[] = {
92   - STPMU1_RANGE(1000000, 0, 17, 0),
93   - STPMU1_RANGE(1050000, 18, 19, 0),
94   - STPMU1_RANGE(1100000, 20, 21, 0),
95   - STPMU1_RANGE(1150000, 22, 23, 0),
96   - STPMU1_RANGE(1200000, 24, 25, 0),
97   - STPMU1_RANGE(1250000, 26, 27, 0),
98   - STPMU1_RANGE(1300000, 28, 29, 0),
99   - STPMU1_RANGE(1350000, 30, 31, 0),
100   - STPMU1_RANGE(1400000, 32, 33, 0),
101   - STPMU1_RANGE(1450000, 34, 35, 0),
102   - STPMU1_RANGE(1500000, 36, 63, 0),
  91 +static const struct stpmic1_range buck2_ranges[] = {
  92 + STPMIC1_RANGE(1000000, 0, 17, 0),
  93 + STPMIC1_RANGE(1050000, 18, 19, 0),
  94 + STPMIC1_RANGE(1100000, 20, 21, 0),
  95 + STPMIC1_RANGE(1150000, 22, 23, 0),
  96 + STPMIC1_RANGE(1200000, 24, 25, 0),
  97 + STPMIC1_RANGE(1250000, 26, 27, 0),
  98 + STPMIC1_RANGE(1300000, 28, 29, 0),
  99 + STPMIC1_RANGE(1350000, 30, 31, 0),
  100 + STPMIC1_RANGE(1400000, 32, 33, 0),
  101 + STPMIC1_RANGE(1450000, 34, 35, 0),
  102 + STPMIC1_RANGE(1500000, 36, 63, 0),
103 103 };
104 104  
105   -static const struct stpmu1_range buck3_ranges[] = {
106   - STPMU1_RANGE(1000000, 0, 19, 0),
107   - STPMU1_RANGE(1100000, 20, 23, 0),
108   - STPMU1_RANGE(1200000, 24, 27, 0),
109   - STPMU1_RANGE(1300000, 28, 31, 0),
110   - STPMU1_RANGE(1400000, 32, 35, 0),
111   - STPMU1_RANGE(1500000, 36, 55, 100000),
112   - STPMU1_RANGE(3400000, 56, 63, 0),
  105 +static const struct stpmic1_range buck3_ranges[] = {
  106 + STPMIC1_RANGE(1000000, 0, 19, 0),
  107 + STPMIC1_RANGE(1100000, 20, 23, 0),
  108 + STPMIC1_RANGE(1200000, 24, 27, 0),
  109 + STPMIC1_RANGE(1300000, 28, 31, 0),
  110 + STPMIC1_RANGE(1400000, 32, 35, 0),
  111 + STPMIC1_RANGE(1500000, 36, 55, 100000),
  112 + STPMIC1_RANGE(3400000, 56, 63, 0),
113 113 };
114 114  
115   -static const struct stpmu1_range buck4_ranges[] = {
116   - STPMU1_RANGE(600000, 0, 27, 25000),
117   - STPMU1_RANGE(1300000, 28, 29, 0),
118   - STPMU1_RANGE(1350000, 30, 31, 0),
119   - STPMU1_RANGE(1400000, 32, 33, 0),
120   - STPMU1_RANGE(1450000, 34, 35, 0),
121   - STPMU1_RANGE(1500000, 36, 60, 100000),
122   - STPMU1_RANGE(3900000, 61, 63, 0),
  115 +static const struct stpmic1_range buck4_ranges[] = {
  116 + STPMIC1_RANGE(600000, 0, 27, 25000),
  117 + STPMIC1_RANGE(1300000, 28, 29, 0),
  118 + STPMIC1_RANGE(1350000, 30, 31, 0),
  119 + STPMIC1_RANGE(1400000, 32, 33, 0),
  120 + STPMIC1_RANGE(1450000, 34, 35, 0),
  121 + STPMIC1_RANGE(1500000, 36, 60, 100000),
  122 + STPMIC1_RANGE(3900000, 61, 63, 0),
123 123 };
124 124  
125 125 /* BUCK: 1,2,3,4 - voltage ranges */
126   -static const struct stpmu1_output_range buck_voltage_range[] = {
127   - STPMU1_OUTPUT_RANGE(buck1_ranges, ARRAY_SIZE(buck1_ranges)),
128   - STPMU1_OUTPUT_RANGE(buck2_ranges, ARRAY_SIZE(buck2_ranges)),
129   - STPMU1_OUTPUT_RANGE(buck3_ranges, ARRAY_SIZE(buck3_ranges)),
130   - STPMU1_OUTPUT_RANGE(buck4_ranges, ARRAY_SIZE(buck4_ranges)),
  126 +static const struct stpmic1_output buck_voltage_range[] = {
  127 + STPMIC1_OUTPUT(buck1_ranges, ARRAY_SIZE(buck1_ranges)),
  128 + STPMIC1_OUTPUT(buck2_ranges, ARRAY_SIZE(buck2_ranges)),
  129 + STPMIC1_OUTPUT(buck3_ranges, ARRAY_SIZE(buck3_ranges)),
  130 + STPMIC1_OUTPUT(buck4_ranges, ARRAY_SIZE(buck4_ranges)),
131 131 };
132 132  
133 133 /* BUCK modes */
134 134 static const struct dm_regulator_mode buck_modes[] = {
135   - STPMU1_MODE(STPMU1_BUCK_MODE_HP, STPMU1_BUCK_MODE_HP, "HP"),
136   - STPMU1_MODE(STPMU1_BUCK_MODE_LP, STPMU1_BUCK_MODE_LP, "LP"),
  135 + STPMIC1_MODE(STPMIC1_BUCK_MODE_HP, STPMIC1_BUCK_MODE_HP, "HP"),
  136 + STPMIC1_MODE(STPMIC1_BUCK_MODE_LP, STPMIC1_BUCK_MODE_LP, "LP"),
137 137 };
138 138  
139   -static int stpmu1_buck_get_uv(struct udevice *dev, int buck)
  139 +static int stpmic1_buck_get_uv(struct udevice *dev, int buck)
140 140 {
141 141 int sel;
142 142  
143   - sel = pmic_reg_read(dev, STPMU1_BUCKX_CTRL_REG(buck));
  143 + sel = pmic_reg_read(dev, STPMIC1_BUCKX_CTRL_REG(buck));
144 144 if (sel < 0)
145 145 return sel;
146 146  
147   - sel &= STPMU1_BUCK_OUTPUT_MASK;
148   - sel >>= STPMU1_BUCK_OUTPUT_SHIFT;
  147 + sel &= STPMIC1_BUCK_OUTPUT_MASK;
  148 + sel >>= STPMIC1_BUCK_OUTPUT_SHIFT;
149 149  
150   - return stpmu1_output_find_uv(sel, &buck_voltage_range[buck]);
  150 + return stpmic1_output_find_uv(sel, &buck_voltage_range[buck]);
151 151 }
152 152  
153   -static int stpmu1_buck_get_value(struct udevice *dev)
  153 +static int stpmic1_buck_get_value(struct udevice *dev)
154 154 {
155   - return stpmu1_buck_get_uv(dev->parent, dev->driver_data - 1);
  155 + return stpmic1_buck_get_uv(dev->parent, dev->driver_data - 1);
156 156 }
157 157  
158   -static int stpmu1_buck_set_value(struct udevice *dev, int uv)
  158 +static int stpmic1_buck_set_value(struct udevice *dev, int uv)
159 159 {
160 160 int sel, buck = dev->driver_data - 1;
161 161  
162   - sel = stpmu1_output_find_sel(uv, &buck_voltage_range[buck]);
  162 + sel = stpmic1_output_find_sel(uv, &buck_voltage_range[buck]);
163 163 if (sel < 0)
164 164 return sel;
165 165  
166 166 return pmic_clrsetbits(dev->parent,
167   - STPMU1_BUCKX_CTRL_REG(buck),
168   - STPMU1_BUCK_OUTPUT_MASK,
169   - sel << STPMU1_BUCK_OUTPUT_SHIFT);
  167 + STPMIC1_BUCKX_CTRL_REG(buck),
  168 + STPMIC1_BUCK_OUTPUT_MASK,
  169 + sel << STPMIC1_BUCK_OUTPUT_SHIFT);
170 170 }
171 171  
172   -static int stpmu1_buck_get_enable(struct udevice *dev)
  172 +static int stpmic1_buck_get_enable(struct udevice *dev)
173 173 {
174 174 int ret;
175 175  
176 176 ret = pmic_reg_read(dev->parent,
177   - STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
  177 + STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1));
178 178 if (ret < 0)
179 179 return false;
180 180  
181   - return ret & STPMU1_BUCK_EN ? true : false;
  181 + return ret & STPMIC1_BUCK_EN ? true : false;
182 182 }
183 183  
184   -static int stpmu1_buck_set_enable(struct udevice *dev, bool enable)
  184 +static int stpmic1_buck_set_enable(struct udevice *dev, bool enable)
185 185 {
186 186 struct dm_regulator_uclass_platdata *uc_pdata;
187   - int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
188   - STPMU1_DEFAULT_STOP_DELAY_MS;
  187 + int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  188 + STPMIC1_DEFAULT_STOP_DELAY_MS;
189 189 int ret, uv;
190 190  
191 191 /* if regulator is already in the wanted state, nothing to do */
192   - if (stpmu1_buck_get_enable(dev) == enable)
  192 + if (stpmic1_buck_get_enable(dev) == enable)
193 193 return 0;
194 194  
195 195 if (enable) {
196 196 uc_pdata = dev_get_uclass_platdata(dev);
197   - uv = stpmu1_buck_get_value(dev);
198   - if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
199   - stpmu1_buck_set_value(dev, uc_pdata->min_uV);
  197 + uv = stpmic1_buck_get_value(dev);
  198 + if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV)
  199 + stpmic1_buck_set_value(dev, uc_pdata->min_uV);
200 200 }
201 201  
202 202 ret = pmic_clrsetbits(dev->parent,
203   - STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
204   - STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0);
  203 + STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1),
  204 + STPMIC1_BUCK_EN, enable ? STPMIC1_BUCK_EN : 0);
205 205 mdelay(delay);
206 206  
207 207 return ret;
208 208 }
209 209  
210   -static int stpmu1_buck_get_mode(struct udevice *dev)
  210 +static int stpmic1_buck_get_mode(struct udevice *dev)
211 211 {
212 212 int ret;
213 213  
214 214 ret = pmic_reg_read(dev->parent,
215   - STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
  215 + STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1));
216 216 if (ret < 0)
217 217 return ret;
218 218  
219   - return ret & STPMU1_BUCK_MODE ? STPMU1_BUCK_MODE_LP :
220   - STPMU1_BUCK_MODE_HP;
  219 + return ret & STPMIC1_BUCK_MODE ? STPMIC1_BUCK_MODE_LP :
  220 + STPMIC1_BUCK_MODE_HP;
221 221 }
222 222  
223   -static int stpmu1_buck_set_mode(struct udevice *dev, int mode)
  223 +static int stpmic1_buck_set_mode(struct udevice *dev, int mode)
224 224 {
225 225 return pmic_clrsetbits(dev->parent,
226   - STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
227   - STPMU1_BUCK_MODE,
228   - mode ? STPMU1_BUCK_MODE : 0);
  226 + STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1),
  227 + STPMIC1_BUCK_MODE,
  228 + mode ? STPMIC1_BUCK_MODE : 0);
229 229 }
230 230  
231   -static int stpmu1_buck_probe(struct udevice *dev)
  231 +static int stpmic1_buck_probe(struct udevice *dev)
232 232 {
233 233 struct dm_regulator_uclass_platdata *uc_pdata;
234 234  
235   - if (!dev->driver_data || dev->driver_data > STPMU1_MAX_BUCK)
  235 + if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_BUCK)
236 236 return -EINVAL;
237 237  
238 238 uc_pdata = dev_get_uclass_platdata(dev);
239 239  
240 240  
241 241  
242 242  
243 243  
244 244  
245 245  
246 246  
247 247  
248 248  
249 249  
250 250  
251 251  
252 252  
253 253  
254 254  
255 255  
256 256  
257 257  
258 258  
259 259  
260 260  
261 261  
262 262  
263 263  
264 264  
265 265  
266 266  
267 267  
268 268  
269 269  
270 270  
271 271  
272 272  
273 273  
274 274  
275 275  
276 276  
277 277  
278 278  
279 279  
... ... @@ -244,206 +244,206 @@
244 244 return 0;
245 245 }
246 246  
247   -static const struct dm_regulator_ops stpmu1_buck_ops = {
248   - .get_value = stpmu1_buck_get_value,
249   - .set_value = stpmu1_buck_set_value,
250   - .get_enable = stpmu1_buck_get_enable,
251   - .set_enable = stpmu1_buck_set_enable,
252   - .get_mode = stpmu1_buck_get_mode,
253   - .set_mode = stpmu1_buck_set_mode,
  247 +static const struct dm_regulator_ops stpmic1_buck_ops = {
  248 + .get_value = stpmic1_buck_get_value,
  249 + .set_value = stpmic1_buck_set_value,
  250 + .get_enable = stpmic1_buck_get_enable,
  251 + .set_enable = stpmic1_buck_set_enable,
  252 + .get_mode = stpmic1_buck_get_mode,
  253 + .set_mode = stpmic1_buck_set_mode,
254 254 };
255 255  
256   -U_BOOT_DRIVER(stpmu1_buck) = {
257   - .name = "stpmu1_buck",
  256 +U_BOOT_DRIVER(stpmic1_buck) = {
  257 + .name = "stpmic1_buck",
258 258 .id = UCLASS_REGULATOR,
259   - .ops = &stpmu1_buck_ops,
260   - .probe = stpmu1_buck_probe,
  259 + .ops = &stpmic1_buck_ops,
  260 + .probe = stpmic1_buck_probe,
261 261 };
262 262  
263 263 /*
264 264 * LDO regulators
265 265 */
266 266  
267   -static const struct stpmu1_range ldo12_ranges[] = {
268   - STPMU1_RANGE(1700000, 0, 7, 0),
269   - STPMU1_RANGE(1700000, 8, 24, 100000),
270   - STPMU1_RANGE(3300000, 25, 31, 0),
  267 +static const struct stpmic1_range ldo12_ranges[] = {
  268 + STPMIC1_RANGE(1700000, 0, 7, 0),
  269 + STPMIC1_RANGE(1700000, 8, 24, 100000),
  270 + STPMIC1_RANGE(3300000, 25, 31, 0),
271 271 };
272 272  
273   -static const struct stpmu1_range ldo3_ranges[] = {
274   - STPMU1_RANGE(1700000, 0, 7, 0),
275   - STPMU1_RANGE(1700000, 8, 24, 100000),
276   - STPMU1_RANGE(3300000, 25, 30, 0),
  273 +static const struct stpmic1_range ldo3_ranges[] = {
  274 + STPMIC1_RANGE(1700000, 0, 7, 0),
  275 + STPMIC1_RANGE(1700000, 8, 24, 100000),
  276 + STPMIC1_RANGE(3300000, 25, 30, 0),
277 277 /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */
278 278 };
279 279  
280   -static const struct stpmu1_range ldo5_ranges[] = {
281   - STPMU1_RANGE(1700000, 0, 7, 0),
282   - STPMU1_RANGE(1700000, 8, 30, 100000),
283   - STPMU1_RANGE(3900000, 31, 31, 0),
  280 +static const struct stpmic1_range ldo5_ranges[] = {
  281 + STPMIC1_RANGE(1700000, 0, 7, 0),
  282 + STPMIC1_RANGE(1700000, 8, 30, 100000),
  283 + STPMIC1_RANGE(3900000, 31, 31, 0),
284 284 };
285 285  
286   -static const struct stpmu1_range ldo6_ranges[] = {
287   - STPMU1_RANGE(900000, 0, 24, 100000),
288   - STPMU1_RANGE(3300000, 25, 31, 0),
  286 +static const struct stpmic1_range ldo6_ranges[] = {
  287 + STPMIC1_RANGE(900000, 0, 24, 100000),
  288 + STPMIC1_RANGE(3300000, 25, 31, 0),
289 289 };
290 290  
291 291 /* LDO: 1,2,3,4,5,6 - voltage ranges */
292   -static const struct stpmu1_output_range ldo_voltage_range[] = {
293   - STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
294   - STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
295   - STPMU1_OUTPUT_RANGE(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)),
296   - STPMU1_OUTPUT_RANGE(NULL, 0),
297   - STPMU1_OUTPUT_RANGE(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)),
298   - STPMU1_OUTPUT_RANGE(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)),
  292 +static const struct stpmic1_output ldo_voltage_range[] = {
  293 + STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
  294 + STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
  295 + STPMIC1_OUTPUT(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)),
  296 + STPMIC1_OUTPUT(NULL, 0),
  297 + STPMIC1_OUTPUT(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)),
  298 + STPMIC1_OUTPUT(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)),
299 299 };
300 300  
301 301 /* LDO modes */
302 302 static const struct dm_regulator_mode ldo_modes[] = {
303   - STPMU1_MODE(STPMU1_LDO_MODE_NORMAL,
304   - STPMU1_LDO_MODE_NORMAL, "NORMAL"),
305   - STPMU1_MODE(STPMU1_LDO_MODE_BYPASS,
306   - STPMU1_LDO_MODE_BYPASS, "BYPASS"),
307   - STPMU1_MODE(STPMU1_LDO_MODE_SINK_SOURCE,
308   - STPMU1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"),
  303 + STPMIC1_MODE(STPMIC1_LDO_MODE_NORMAL,
  304 + STPMIC1_LDO_MODE_NORMAL, "NORMAL"),
  305 + STPMIC1_MODE(STPMIC1_LDO_MODE_BYPASS,
  306 + STPMIC1_LDO_MODE_BYPASS, "BYPASS"),
  307 + STPMIC1_MODE(STPMIC1_LDO_MODE_SINK_SOURCE,
  308 + STPMIC1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"),
309 309 };
310 310  
311   -static int stpmu1_ldo_get_value(struct udevice *dev)
  311 +static int stpmic1_ldo_get_value(struct udevice *dev)
312 312 {
313 313 int sel, ldo = dev->driver_data - 1;
314 314  
315   - sel = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
  315 + sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
316 316 if (sel < 0)
317 317 return sel;
318 318  
319 319 /* ldo4 => 3,3V */
320   - if (ldo == STPMU1_LDO4)
321   - return STPMU1_LDO4_UV;
  320 + if (ldo == STPMIC1_LDO4)
  321 + return STPMIC1_LDO4_UV;
322 322  
323   - sel &= STPMU1_LDO12356_OUTPUT_MASK;
324   - sel >>= STPMU1_LDO12356_OUTPUT_SHIFT;
  323 + sel &= STPMIC1_LDO12356_OUTPUT_MASK;
  324 + sel >>= STPMIC1_LDO12356_OUTPUT_SHIFT;
325 325  
326 326 /* ldo3, sel = 31 => BUCK2/2 */
327   - if (ldo == STPMU1_LDO3 && sel == STPMU1_LDO3_DDR_SEL)
328   - return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
  327 + if (ldo == STPMIC1_LDO3 && sel == STPMIC1_LDO3_DDR_SEL)
  328 + return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2;
329 329  
330   - return stpmu1_output_find_uv(sel, &ldo_voltage_range[ldo]);
  330 + return stpmic1_output_find_uv(sel, &ldo_voltage_range[ldo]);
331 331 }
332 332  
333   -static int stpmu1_ldo_set_value(struct udevice *dev, int uv)
  333 +static int stpmic1_ldo_set_value(struct udevice *dev, int uv)
334 334 {
335 335 int sel, ldo = dev->driver_data - 1;
336 336  
337 337 /* ldo4 => not possible */
338   - if (ldo == STPMU1_LDO4)
  338 + if (ldo == STPMIC1_LDO4)
339 339 return -EINVAL;
340 340  
341   - sel = stpmu1_output_find_sel(uv, &ldo_voltage_range[ldo]);
  341 + sel = stpmic1_output_find_sel(uv, &ldo_voltage_range[ldo]);
342 342 if (sel < 0)
343 343 return sel;
344 344  
345 345 return pmic_clrsetbits(dev->parent,
346   - STPMU1_LDOX_CTRL_REG(ldo),
347   - STPMU1_LDO12356_OUTPUT_MASK,
348   - sel << STPMU1_LDO12356_OUTPUT_SHIFT);
  346 + STPMIC1_LDOX_CTRL_REG(ldo),
  347 + STPMIC1_LDO12356_OUTPUT_MASK,
  348 + sel << STPMIC1_LDO12356_OUTPUT_SHIFT);
349 349 }
350 350  
351   -static int stpmu1_ldo_get_enable(struct udevice *dev)
  351 +static int stpmic1_ldo_get_enable(struct udevice *dev)
352 352 {
353 353 int ret;
354 354  
355 355 ret = pmic_reg_read(dev->parent,
356   - STPMU1_LDOX_CTRL_REG(dev->driver_data - 1));
  356 + STPMIC1_LDOX_CTRL_REG(dev->driver_data - 1));
357 357 if (ret < 0)
358 358 return false;
359 359  
360   - return ret & STPMU1_LDO_EN ? true : false;
  360 + return ret & STPMIC1_LDO_EN ? true : false;
361 361 }
362 362  
363   -static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable)
  363 +static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable)
364 364 {
365 365 struct dm_regulator_uclass_platdata *uc_pdata;
366   - int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
367   - STPMU1_DEFAULT_STOP_DELAY_MS;
  366 + int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  367 + STPMIC1_DEFAULT_STOP_DELAY_MS;
368 368 int ret, uv;
369 369  
370 370 /* if regulator is already in the wanted state, nothing to do */
371   - if (stpmu1_ldo_get_enable(dev) == enable)
  371 + if (stpmic1_ldo_get_enable(dev) == enable)
372 372 return 0;
373 373  
374 374 if (enable) {
375 375 uc_pdata = dev_get_uclass_platdata(dev);
376   - uv = stpmu1_ldo_get_value(dev);
377   - if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
378   - stpmu1_ldo_set_value(dev, uc_pdata->min_uV);
  376 + uv = stpmic1_ldo_get_value(dev);
  377 + if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV)
  378 + stpmic1_ldo_set_value(dev, uc_pdata->min_uV);
379 379 }
380 380  
381 381 ret = pmic_clrsetbits(dev->parent,
382   - STPMU1_LDOX_CTRL_REG(dev->driver_data - 1),
383   - STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0);
  382 + STPMIC1_LDOX_CTRL_REG(dev->driver_data - 1),
  383 + STPMIC1_LDO_EN, enable ? STPMIC1_LDO_EN : 0);
384 384 mdelay(delay);
385 385  
386 386 return ret;
387 387 }
388 388  
389   -static int stpmu1_ldo_get_mode(struct udevice *dev)
  389 +static int stpmic1_ldo_get_mode(struct udevice *dev)
390 390 {
391 391 int ret, ldo = dev->driver_data - 1;
392 392  
393   - if (ldo != STPMU1_LDO3)
  393 + if (ldo != STPMIC1_LDO3)
394 394 return -EINVAL;
395 395  
396   - ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
  396 + ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
397 397 if (ret < 0)
398 398 return ret;
399 399  
400   - if (ret & STPMU1_LDO3_MODE)
401   - return STPMU1_LDO_MODE_BYPASS;
  400 + if (ret & STPMIC1_LDO3_MODE)
  401 + return STPMIC1_LDO_MODE_BYPASS;
402 402  
403   - ret &= STPMU1_LDO12356_OUTPUT_MASK;
404   - ret >>= STPMU1_LDO12356_OUTPUT_SHIFT;
  403 + ret &= STPMIC1_LDO12356_OUTPUT_MASK;
  404 + ret >>= STPMIC1_LDO12356_OUTPUT_SHIFT;
405 405  
406   - return ret == STPMU1_LDO3_DDR_SEL ? STPMU1_LDO_MODE_SINK_SOURCE :
407   - STPMU1_LDO_MODE_NORMAL;
  406 + return ret == STPMIC1_LDO3_DDR_SEL ? STPMIC1_LDO_MODE_SINK_SOURCE :
  407 + STPMIC1_LDO_MODE_NORMAL;
408 408 }
409 409  
410   -static int stpmu1_ldo_set_mode(struct udevice *dev, int mode)
  410 +static int stpmic1_ldo_set_mode(struct udevice *dev, int mode)
411 411 {
412 412 int ret, ldo = dev->driver_data - 1;
413 413  
414   - if (ldo != STPMU1_LDO3)
  414 + if (ldo != STPMIC1_LDO3)
415 415 return -EINVAL;
416 416  
417   - ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
  417 + ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
418 418 if (ret < 0)
419 419 return ret;
420 420  
421 421 switch (mode) {
422   - case STPMU1_LDO_MODE_SINK_SOURCE:
423   - ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
424   - ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
425   - case STPMU1_LDO_MODE_NORMAL:
426   - ret &= ~STPMU1_LDO3_MODE;
  422 + case STPMIC1_LDO_MODE_SINK_SOURCE:
  423 + ret &= ~STPMIC1_LDO12356_OUTPUT_MASK;
  424 + ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_OUTPUT_SHIFT;
  425 + case STPMIC1_LDO_MODE_NORMAL:
  426 + ret &= ~STPMIC1_LDO3_MODE;
427 427 break;
428   - case STPMU1_LDO_MODE_BYPASS:
429   - ret |= STPMU1_LDO3_MODE;
  428 + case STPMIC1_LDO_MODE_BYPASS:
  429 + ret |= STPMIC1_LDO3_MODE;
430 430 break;
431 431 }
432 432  
433   - return pmic_reg_write(dev->parent, STPMU1_LDOX_CTRL_REG(ldo), ret);
  433 + return pmic_reg_write(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo), ret);
434 434 }
435 435  
436   -static int stpmu1_ldo_probe(struct udevice *dev)
  436 +static int stpmic1_ldo_probe(struct udevice *dev)
437 437 {
438 438 struct dm_regulator_uclass_platdata *uc_pdata;
439 439  
440   - if (!dev->driver_data || dev->driver_data > STPMU1_MAX_LDO)
  440 + if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_LDO)
441 441 return -EINVAL;
442 442  
443 443 uc_pdata = dev_get_uclass_platdata(dev);
444 444  
445 445 uc_pdata->type = REGULATOR_TYPE_LDO;
446   - if (dev->driver_data - 1 == STPMU1_LDO3) {
  446 + if (dev->driver_data - 1 == STPMIC1_LDO3) {
447 447 uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes;
448 448 uc_pdata->mode_count = ARRAY_SIZE(ldo_modes);
449 449 } else {
450 450  
451 451  
452 452  
453 453  
454 454  
455 455  
456 456  
457 457  
458 458  
459 459  
460 460  
461 461  
... ... @@ -453,61 +453,61 @@
453 453 return 0;
454 454 }
455 455  
456   -static const struct dm_regulator_ops stpmu1_ldo_ops = {
457   - .get_value = stpmu1_ldo_get_value,
458   - .set_value = stpmu1_ldo_set_value,
459   - .get_enable = stpmu1_ldo_get_enable,
460   - .set_enable = stpmu1_ldo_set_enable,
461   - .get_mode = stpmu1_ldo_get_mode,
462   - .set_mode = stpmu1_ldo_set_mode,
  456 +static const struct dm_regulator_ops stpmic1_ldo_ops = {
  457 + .get_value = stpmic1_ldo_get_value,
  458 + .set_value = stpmic1_ldo_set_value,
  459 + .get_enable = stpmic1_ldo_get_enable,
  460 + .set_enable = stpmic1_ldo_set_enable,
  461 + .get_mode = stpmic1_ldo_get_mode,
  462 + .set_mode = stpmic1_ldo_set_mode,
463 463 };
464 464  
465   -U_BOOT_DRIVER(stpmu1_ldo) = {
466   - .name = "stpmu1_ldo",
  465 +U_BOOT_DRIVER(stpmic1_ldo) = {
  466 + .name = "stpmic1_ldo",
467 467 .id = UCLASS_REGULATOR,
468   - .ops = &stpmu1_ldo_ops,
469   - .probe = stpmu1_ldo_probe,
  468 + .ops = &stpmic1_ldo_ops,
  469 + .probe = stpmic1_ldo_probe,
470 470 };
471 471  
472 472 /*
473 473 * VREF DDR regulator
474 474 */
475 475  
476   -static int stpmu1_vref_ddr_get_value(struct udevice *dev)
  476 +static int stpmic1_vref_ddr_get_value(struct udevice *dev)
477 477 {
478 478 /* BUCK2/2 */
479   - return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
  479 + return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2;
480 480 }
481 481  
482   -static int stpmu1_vref_ddr_get_enable(struct udevice *dev)
  482 +static int stpmic1_vref_ddr_get_enable(struct udevice *dev)
483 483 {
484 484 int ret;
485 485  
486   - ret = pmic_reg_read(dev->parent, STPMU1_VREF_CTRL_REG);
  486 + ret = pmic_reg_read(dev->parent, STPMIC1_VREF_CTRL_REG);
487 487 if (ret < 0)
488 488 return false;
489 489  
490   - return ret & STPMU1_VREF_EN ? true : false;
  490 + return ret & STPMIC1_VREF_EN ? true : false;
491 491 }
492 492  
493   -static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable)
  493 +static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable)
494 494 {
495   - int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
496   - STPMU1_DEFAULT_STOP_DELAY_MS;
  495 + int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  496 + STPMIC1_DEFAULT_STOP_DELAY_MS;
497 497 int ret;
498 498  
499 499 /* if regulator is already in the wanted state, nothing to do */
500   - if (stpmu1_vref_ddr_get_enable(dev) == enable)
  500 + if (stpmic1_vref_ddr_get_enable(dev) == enable)
501 501 return 0;
502 502  
503   - ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG,
504   - STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0);
  503 + ret = pmic_clrsetbits(dev->parent, STPMIC1_VREF_CTRL_REG,
  504 + STPMIC1_VREF_EN, enable ? STPMIC1_VREF_EN : 0);
505 505 mdelay(delay);
506 506  
507 507 return ret;
508 508 }
509 509  
510   -static int stpmu1_vref_ddr_probe(struct udevice *dev)
  510 +static int stpmic1_vref_ddr_probe(struct udevice *dev)
511 511 {
512 512 struct dm_regulator_uclass_platdata *uc_pdata;
513 513  
514 514  
515 515  
516 516  
517 517  
518 518  
519 519  
520 520  
521 521  
522 522  
523 523  
524 524  
525 525  
... ... @@ -519,59 +519,59 @@
519 519 return 0;
520 520 }
521 521  
522   -static const struct dm_regulator_ops stpmu1_vref_ddr_ops = {
523   - .get_value = stpmu1_vref_ddr_get_value,
524   - .get_enable = stpmu1_vref_ddr_get_enable,
525   - .set_enable = stpmu1_vref_ddr_set_enable,
  522 +static const struct dm_regulator_ops stpmic1_vref_ddr_ops = {
  523 + .get_value = stpmic1_vref_ddr_get_value,
  524 + .get_enable = stpmic1_vref_ddr_get_enable,
  525 + .set_enable = stpmic1_vref_ddr_set_enable,
526 526 };
527 527  
528   -U_BOOT_DRIVER(stpmu1_vref_ddr) = {
529   - .name = "stpmu1_vref_ddr",
  528 +U_BOOT_DRIVER(stpmic1_vref_ddr) = {
  529 + .name = "stpmic1_vref_ddr",
530 530 .id = UCLASS_REGULATOR,
531   - .ops = &stpmu1_vref_ddr_ops,
532   - .probe = stpmu1_vref_ddr_probe,
  531 + .ops = &stpmic1_vref_ddr_ops,
  532 + .probe = stpmic1_vref_ddr_probe,
533 533 };
534 534  
535 535 /*
536 536 * BOOST regulator
537 537 */
538 538  
539   -static int stpmu1_boost_get_enable(struct udevice *dev)
  539 +static int stpmic1_boost_get_enable(struct udevice *dev)
540 540 {
541 541 int ret;
542 542  
543   - ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
  543 + ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
544 544 if (ret < 0)
545 545 return false;
546 546  
547   - return ret & STPMU1_USB_BOOST_EN ? true : false;
  547 + return ret & STPMIC1_USB_BOOST_EN ? true : false;
548 548 }
549 549  
550   -static int stpmu1_boost_set_enable(struct udevice *dev, bool enable)
  550 +static int stpmic1_boost_set_enable(struct udevice *dev, bool enable)
551 551 {
552 552 int ret;
553 553  
554   - ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
  554 + ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
555 555 if (ret < 0)
556 556 return ret;
557 557  
558   - if (!enable && ret & STPMU1_USB_PWR_SW_EN)
  558 + if (!enable && ret & STPMIC1_USB_PWR_SW_EN)
559 559 return -EINVAL;
560 560  
561 561 /* if regulator is already in the wanted state, nothing to do */
562   - if (!!(ret & STPMU1_USB_BOOST_EN) == enable)
  562 + if (!!(ret & STPMIC1_USB_BOOST_EN) == enable)
563 563 return 0;
564 564  
565   - ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
566   - STPMU1_USB_BOOST_EN,
567   - enable ? STPMU1_USB_BOOST_EN : 0);
  565 + ret = pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
  566 + STPMIC1_USB_BOOST_EN,
  567 + enable ? STPMIC1_USB_BOOST_EN : 0);
568 568 if (enable)
569   - mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
  569 + mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
570 570  
571 571 return ret;
572 572 }
573 573  
574   -static int stpmu1_boost_probe(struct udevice *dev)
  574 +static int stpmic1_boost_probe(struct udevice *dev)
575 575 {
576 576 struct dm_regulator_uclass_platdata *uc_pdata;
577 577  
578 578  
579 579  
580 580  
581 581  
582 582  
583 583  
584 584  
... ... @@ -583,42 +583,42 @@
583 583 return 0;
584 584 }
585 585  
586   -static const struct dm_regulator_ops stpmu1_boost_ops = {
587   - .get_enable = stpmu1_boost_get_enable,
588   - .set_enable = stpmu1_boost_set_enable,
  586 +static const struct dm_regulator_ops stpmic1_boost_ops = {
  587 + .get_enable = stpmic1_boost_get_enable,
  588 + .set_enable = stpmic1_boost_set_enable,
589 589 };
590 590  
591   -U_BOOT_DRIVER(stpmu1_boost) = {
592   - .name = "stpmu1_boost",
  591 +U_BOOT_DRIVER(stpmic1_boost) = {
  592 + .name = "stpmic1_boost",
593 593 .id = UCLASS_REGULATOR,
594   - .ops = &stpmu1_boost_ops,
595   - .probe = stpmu1_boost_probe,
  594 + .ops = &stpmic1_boost_ops,
  595 + .probe = stpmic1_boost_probe,
596 596 };
597 597  
598 598 /*
599 599 * USB power switch
600 600 */
601 601  
602   -static int stpmu1_pwr_sw_get_enable(struct udevice *dev)
  602 +static int stpmic1_pwr_sw_get_enable(struct udevice *dev)
603 603 {
604 604 uint mask = 1 << dev->driver_data;
605 605 int ret;
606 606  
607   - ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
  607 + ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
608 608 if (ret < 0)
609 609 return false;
610 610  
611 611 return ret & mask ? true : false;
612 612 }
613 613  
614   -static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable)
  614 +static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable)
615 615 {
616 616 uint mask = 1 << dev->driver_data;
617   - int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
618   - STPMU1_DEFAULT_STOP_DELAY_MS;
  617 + int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  618 + STPMIC1_DEFAULT_STOP_DELAY_MS;
619 619 int ret;
620 620  
621   - ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
  621 + ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
622 622 if (ret < 0)
623 623 return ret;
624 624  
625 625  
626 626  
627 627  
... ... @@ -627,28 +627,28 @@
627 627 return 0;
628 628  
629 629 /* Boost management */
630   - if (enable && !(ret & STPMU1_USB_BOOST_EN)) {
631   - pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
632   - STPMU1_USB_BOOST_EN, STPMU1_USB_BOOST_EN);
633   - mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
634   - } else if (!enable && ret & STPMU1_USB_BOOST_EN &&
635   - (ret & STPMU1_USB_PWR_SW_EN) != STPMU1_USB_PWR_SW_EN) {
636   - pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
637   - STPMU1_USB_BOOST_EN, 0);
  630 + if (enable && !(ret & STPMIC1_USB_BOOST_EN)) {
  631 + pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
  632 + STPMIC1_USB_BOOST_EN, STPMIC1_USB_BOOST_EN);
  633 + mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
  634 + } else if (!enable && ret & STPMIC1_USB_BOOST_EN &&
  635 + (ret & STPMIC1_USB_PWR_SW_EN) != STPMIC1_USB_PWR_SW_EN) {
  636 + pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
  637 + STPMIC1_USB_BOOST_EN, 0);
638 638 }
639 639  
640   - ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
  640 + ret = pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
641 641 mask, enable ? mask : 0);
642 642 mdelay(delay);
643 643  
644 644 return ret;
645 645 }
646 646  
647   -static int stpmu1_pwr_sw_probe(struct udevice *dev)
  647 +static int stpmic1_pwr_sw_probe(struct udevice *dev)
648 648 {
649 649 struct dm_regulator_uclass_platdata *uc_pdata;
650 650  
651   - if (!dev->driver_data || dev->driver_data > STPMU1_MAX_PWR_SW)
  651 + if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_PWR_SW)
652 652 return -EINVAL;
653 653  
654 654 uc_pdata = dev_get_uclass_platdata(dev);
655 655  
656 656  
... ... @@ -659,15 +659,15 @@
659 659 return 0;
660 660 }
661 661  
662   -static const struct dm_regulator_ops stpmu1_pwr_sw_ops = {
663   - .get_enable = stpmu1_pwr_sw_get_enable,
664   - .set_enable = stpmu1_pwr_sw_set_enable,
  662 +static const struct dm_regulator_ops stpmic1_pwr_sw_ops = {
  663 + .get_enable = stpmic1_pwr_sw_get_enable,
  664 + .set_enable = stpmic1_pwr_sw_set_enable,
665 665 };
666 666  
667   -U_BOOT_DRIVER(stpmu1_pwr_sw) = {
668   - .name = "stpmu1_pwr_sw",
  667 +U_BOOT_DRIVER(stpmic1_pwr_sw) = {
  668 + .name = "stpmic1_pwr_sw",
669 669 .id = UCLASS_REGULATOR,
670   - .ops = &stpmu1_pwr_sw_ops,
671   - .probe = stpmu1_pwr_sw_probe,
  670 + .ops = &stpmic1_pwr_sw_ops,
  671 + .probe = stpmic1_pwr_sw_probe,
672 672 };
include/dt-bindings/mfd/st,stpmic1.h
Diff comments   View file @ 42f01aa
  1 +/* SPDX-License-Identifier: GPL-2.0 */
1 2 /*
2   - * This file is part of stpmu1 pmic driver
3   - *
4   - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5   - * Author: Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
6   - *
7   - * License type: GPLv2
8   - *
9   - * This program is free software; you can redistribute it and/or modify it
10   - * under the terms of the GNU General Public License version 2 as published by
11   - * the Free Software Foundation.
12   - *
13   - * This program is distributed in the hope that it will be useful, but
14   - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15   - * or FITNESS FOR A PARTICULAR PURPOSE.
16   - * See the GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License along with
19   - * this program. If not, see <http://www.gnu.org/licenses/>.
  3 + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  4 + * Author: Philippe Peurichard <philippe.peurichard@st.com>,
  5 + * Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
20 6 */
21 7  
22   -#ifndef __DT_BINDINGS_STPMU1_H__
23   -#define __DT_BINDINGS_STPMU1_H__
  8 +#ifndef __DT_BINDINGS_STPMIC1_H__
  9 +#define __DT_BINDINGS_STPMIC1_H__
24 10  
25 11 /* IRQ definitions */
26   -#define IT_PONKEY_F 0
27   -#define IT_PONKEY_R 1
28   -#define IT_WAKEUP_F 2
29   -#define IT_WAKEUP_R 3
30   -#define IT_VBUS_OTG_F 4
31   -#define IT_VBUS_OTG_R 5
32   -#define IT_SWOUT_F 6
33   -#define IT_SWOUT_R 7
  12 +#define IT_PONKEY_F 0
  13 +#define IT_PONKEY_R 1
  14 +#define IT_WAKEUP_F 2
  15 +#define IT_WAKEUP_R 3
  16 +#define IT_VBUS_OTG_F 4
  17 +#define IT_VBUS_OTG_R 5
  18 +#define IT_SWOUT_F 6
  19 +#define IT_SWOUT_R 7
34 20  
35   -#define IT_CURLIM_BUCK1 8
36   -#define IT_CURLIM_BUCK2 9
37   -#define IT_CURLIM_BUCK3 10
38   -#define IT_CURLIM_BUCK4 11
39   -#define IT_OCP_OTG 12
40   -#define IT_OCP_SWOUT 13
41   -#define IT_OCP_BOOST 14
42   -#define IT_OVP_BOOST 15
  21 +#define IT_CURLIM_BUCK1 8
  22 +#define IT_CURLIM_BUCK2 9
  23 +#define IT_CURLIM_BUCK3 10
  24 +#define IT_CURLIM_BUCK4 11
  25 +#define IT_OCP_OTG 12
  26 +#define IT_OCP_SWOUT 13
  27 +#define IT_OCP_BOOST 14
  28 +#define IT_OVP_BOOST 15
43 29  
44   -#define IT_CURLIM_LDO1 16
45   -#define IT_CURLIM_LDO2 17
46   -#define IT_CURLIM_LDO3 18
47   -#define IT_CURLIM_LDO4 19
48   -#define IT_CURLIM_LDO5 20
49   -#define IT_CURLIM_LDO6 21
50   -#define IT_SHORT_SWOTG 22
51   -#define IT_SHORT_SWOUT 23
  30 +#define IT_CURLIM_LDO1 16
  31 +#define IT_CURLIM_LDO2 17
  32 +#define IT_CURLIM_LDO3 18
  33 +#define IT_CURLIM_LDO4 19
  34 +#define IT_CURLIM_LDO5 20
  35 +#define IT_CURLIM_LDO6 21
  36 +#define IT_SHORT_SWOTG 22
  37 +#define IT_SHORT_SWOUT 23
52 38  
53   -#define IT_TWARN_F 24
54   -#define IT_TWARN_R 25
55   -#define IT_VINLOW_F 26
56   -#define IT_VINLOW_R 27
57   -#define IT_SWIN_F 30
58   -#define IT_SWIN_R 31
  39 +#define IT_TWARN_F 24
  40 +#define IT_TWARN_R 25
  41 +#define IT_VINLOW_F 26
  42 +#define IT_VINLOW_R 27
  43 +#define IT_SWIN_F 30
  44 +#define IT_SWIN_R 31
59 45  
60   -#endif /* __DT_BINDINGS_STPMU1_H__ */
  46 +#endif /* __DT_BINDINGS_STPMIC1_H__ */
include/power/stpmic1.h
Diff comments   View file @ 42f01aa
... ... @@ -3,84 +3,91 @@
3 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 4 */
5 5  
6   -#ifndef __PMIC_STPMU1_H_
7   -#define __PMIC_STPMU1_H_
  6 +#ifndef __PMIC_STPMIC1_H_
  7 +#define __PMIC_STPMIC1_H_
8 8  
9   -#define STPMU1_MASK_RESET_BUCK 0x18
10   -#define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
11   -#define STPMU1_VREF_CTRL_REG 0x24
12   -#define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
13   -#define STPMU1_USB_CTRL_REG 0x40
14   -#define STPMU1_NVM_USER_STATUS_REG 0xb8
15   -#define STPMU1_NVM_USER_CONTROL_REG 0xb9
  9 +#define STPMIC1_MAIN_CONTROL_REG 0x10
  10 +#define STPMIC1_MASK_RESET_BUCK 0x18
  11 +#define STPMIC1_MASK_RESET_LDOS 0x1a
  12 +#define STPMIC1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
  13 +#define STPMIC1_VREF_CTRL_REG 0x24
  14 +#define STPMIC1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
  15 +#define STPMIC1_USB_CTRL_REG 0x40
  16 +#define STPMIC1_NVM_USER_STATUS_REG 0xb8
  17 +#define STPMIC1_NVM_USER_CONTROL_REG 0xb9
16 18  
17   -#define STPMU1_MASK_RESET_BUCK3 BIT(2)
  19 +/* Main PMIC Control Register (MAIN_CONTROL_REG) */
  20 +#define STPMIC1_CTRL_SWITCH_OFF BIT(0)
  21 +#define STPMIC1_CTRL_RESTART BIT(1)
18 22  
19   -#define STPMU1_BUCK_EN BIT(0)
20   -#define STPMU1_BUCK_MODE BIT(1)
21   -#define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2)
22   -#define STPMU1_BUCK_OUTPUT_SHIFT 2
23   -#define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT)
24   -#define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT)
25   -#define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT)
  23 +#define STPMIC1_MASK_RESET_BUCK3 BIT(2)
  24 +#define STPMIC1_MASK_RESET_BUCK_DBG GENMASK(3, 0)
  25 +#define STPMIC1_MASK_RESET_LDOS_DBG 0x6F
26 26  
27   -#define STPMU1_VREF_EN BIT(0)
  27 +#define STPMIC1_BUCK_EN BIT(0)
  28 +#define STPMIC1_BUCK_MODE BIT(1)
  29 +#define STPMIC1_BUCK_OUTPUT_MASK GENMASK(7, 2)
  30 +#define STPMIC1_BUCK_OUTPUT_SHIFT 2
  31 +#define STPMIC1_BUCK2_1200000V (24 << STPMIC1_BUCK_OUTPUT_SHIFT)
  32 +#define STPMIC1_BUCK2_1350000V (30 << STPMIC1_BUCK_OUTPUT_SHIFT)
  33 +#define STPMIC1_BUCK3_1800000V (39 << STPMIC1_BUCK_OUTPUT_SHIFT)
28 34  
29   -#define STPMU1_LDO_EN BIT(0)
30   -#define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
31   -#define STPMU1_LDO12356_OUTPUT_SHIFT 2
32   -#define STPMU1_LDO3_MODE BIT(7)
33   -#define STPMU1_LDO3_DDR_SEL 31
34   -#define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
35   -#define STPMU1_LDO4_UV 3300000
  35 +#define STPMIC1_VREF_EN BIT(0)
36 36  
37   -#define STPMU1_USB_BOOST_EN BIT(0)
38   -#define STPMU1_USB_PWR_SW_EN GENMASK(2, 1)
  37 +#define STPMIC1_LDO_EN BIT(0)
  38 +#define STPMIC1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
  39 +#define STPMIC1_LDO12356_OUTPUT_SHIFT 2
  40 +#define STPMIC1_LDO3_MODE BIT(7)
  41 +#define STPMIC1_LDO3_DDR_SEL 31
  42 +#define STPMIC1_LDO3_1800000 (9 << STPMIC1_LDO12356_OUTPUT_SHIFT)
  43 +#define STPMIC1_LDO4_UV 3300000
39 44  
40   -#define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0)
41   -#define STPMU1_NVM_USER_CONTROL_READ BIT(1)
  45 +#define STPMIC1_USB_BOOST_EN BIT(0)
  46 +#define STPMIC1_USB_PWR_SW_EN GENMASK(2, 1)
42 47  
43   -#define STPMU1_NVM_USER_STATUS_BUSY BIT(0)
44   -#define STPMU1_NVM_USER_STATUS_ERROR BIT(1)
  48 +#define STPMIC1_NVM_USER_CONTROL_PROGRAM BIT(0)
  49 +#define STPMIC1_NVM_USER_CONTROL_READ BIT(1)
45 50  
46   -#define STPMU1_DEFAULT_START_UP_DELAY_MS 1
47   -#define STPMU1_DEFAULT_STOP_DELAY_MS 5
48   -#define STPMU1_USB_BOOST_START_UP_DELAY_MS 10
  51 +#define STPMIC1_NVM_USER_STATUS_BUSY BIT(0)
  52 +#define STPMIC1_NVM_USER_STATUS_ERROR BIT(1)
49 53  
  54 +#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
  55 +#define STPMIC1_DEFAULT_STOP_DELAY_MS 5
  56 +#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
  57 +
50 58 enum {
51   - STPMU1_BUCK1,
52   - STPMU1_BUCK2,
53   - STPMU1_BUCK3,
54   - STPMU1_BUCK4,
55   - STPMU1_MAX_BUCK,
  59 + STPMIC1_BUCK1,
  60 + STPMIC1_BUCK2,
  61 + STPMIC1_BUCK3,
  62 + STPMIC1_BUCK4,
  63 + STPMIC1_MAX_BUCK,
56 64 };
57 65  
58 66 enum {
59   - STPMU1_BUCK_MODE_HP,
60   - STPMU1_BUCK_MODE_LP,
  67 + STPMIC1_BUCK_MODE_HP,
  68 + STPMIC1_BUCK_MODE_LP,
61 69 };
62 70  
63 71 enum {
64   - STPMU1_LDO1,
65   - STPMU1_LDO2,
66   - STPMU1_LDO3,
67   - STPMU1_LDO4,
68   - STPMU1_LDO5,
69   - STPMU1_LDO6,
70   - STPMU1_MAX_LDO,
  72 + STPMIC1_LDO1,
  73 + STPMIC1_LDO2,
  74 + STPMIC1_LDO3,
  75 + STPMIC1_LDO4,
  76 + STPMIC1_LDO5,
  77 + STPMIC1_LDO6,
  78 + STPMIC1_MAX_LDO,
71 79 };
72 80  
73 81 enum {
74   - STPMU1_LDO_MODE_NORMAL,
75   - STPMU1_LDO_MODE_BYPASS,
76   - STPMU1_LDO_MODE_SINK_SOURCE,
  82 + STPMIC1_LDO_MODE_NORMAL,
  83 + STPMIC1_LDO_MODE_BYPASS,
  84 + STPMIC1_LDO_MODE_SINK_SOURCE,
77 85 };
78 86  
79 87 enum {
80   - STPMU1_PWR_SW1,
81   - STPMU1_PWR_SW2,
82   - STPMU1_MAX_PWR_SW,
  88 + STPMIC1_PWR_SW1,
  89 + STPMIC1_PWR_SW2,
  90 + STPMIC1_MAX_PWR_SW,
83 91 };
84   -
85 92 #endif