Eric Lee / smarc-uboot

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Commit 5187303fc8ae3f5e266e725c5b526381d2b77236

Authored by Adrian Alonso
Committed by Ye Li
1 parent e384b64424
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-23928: board: freescale: imx8mn audio board 2.0 

Add support for imx8mn audio board 2.0 support
reuse common settings from imx8mn evk som
Rework for imx_v2020.04 defconfig, dts and SPL

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>

Showing 15 changed files with 4469 additions and 11 deletions Inline Diff

arch/arm/dts/Makefile
Diff comments   View file @ 5187303
1 # SPDX-License-Identifier: GPL-2.0+ 1 # SPDX-License-Identifier: GPL-2.0+
2 2
3 dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb 3 dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb
4 dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb 4 dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
5 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb 5 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
6 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb 6 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
7 7
8 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb 8 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
9 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb 9 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
10 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ 10 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
11 exynos4210-smdkv310.dtb \ 11 exynos4210-smdkv310.dtb \
12 exynos4210-universal_c210.dtb \ 12 exynos4210-universal_c210.dtb \
13 exynos4210-trats.dtb \ 13 exynos4210-trats.dtb \
14 exynos4412-trats2.dtb \ 14 exynos4412-trats2.dtb \
15 exynos4412-odroid.dtb 15 exynos4412-odroid.dtb
16 16
17 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb 17 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
18 dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb 18 dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
19 19
20 dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb 20 dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
21 21
22 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ 22 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
23 exynos5250-snow.dtb \ 23 exynos5250-snow.dtb \
24 exynos5250-spring.dtb \ 24 exynos5250-spring.dtb \
25 exynos5250-smdk5250.dtb \ 25 exynos5250-smdk5250.dtb \
26 exynos5420-smdk5420.dtb \ 26 exynos5420-smdk5420.dtb \
27 exynos5420-peach-pit.dtb \ 27 exynos5420-peach-pit.dtb \
28 exynos5800-peach-pi.dtb \ 28 exynos5800-peach-pi.dtb \
29 exynos5422-odroidxu3.dtb 29 exynos5422-odroidxu3.dtb
30 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb 30 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
31 31
32 dtb-$(CONFIG_ARCH_DAVINCI) += \ 32 dtb-$(CONFIG_ARCH_DAVINCI) += \
33 da850-evm.dtb \ 33 da850-evm.dtb \
34 da850-lcdk.dtb \ 34 da850-lcdk.dtb \
35 da850-lego-ev3.dtb 35 da850-lego-ev3.dtb
36 36
37 dtb-$(CONFIG_KIRKWOOD) += \ 37 dtb-$(CONFIG_KIRKWOOD) += \
38 kirkwood-atl-sbx81lifkw.dtb \ 38 kirkwood-atl-sbx81lifkw.dtb \
39 kirkwood-atl-sbx81lifxcat.dtb \ 39 kirkwood-atl-sbx81lifxcat.dtb \
40 kirkwood-blackarmor-nas220.dtb \ 40 kirkwood-blackarmor-nas220.dtb \
41 kirkwood-d2net.dtb \ 41 kirkwood-d2net.dtb \
42 kirkwood-db-88f6281.dtb \ 42 kirkwood-db-88f6281.dtb \
43 kirkwood-db-88f6281-spi.dtb \ 43 kirkwood-db-88f6281-spi.dtb \
44 kirkwood-dns325.dtb \ 44 kirkwood-dns325.dtb \
45 kirkwood-dockstar.dtb \ 45 kirkwood-dockstar.dtb \
46 kirkwood-dreamplug.dtb \ 46 kirkwood-dreamplug.dtb \
47 kirkwood-ds109.dtb \ 47 kirkwood-ds109.dtb \
48 kirkwood-goflexnet.dtb \ 48 kirkwood-goflexnet.dtb \
49 kirkwood-guruplug-server-plus.dtb \ 49 kirkwood-guruplug-server-plus.dtb \
50 kirkwood-ib62x0.dtb \ 50 kirkwood-ib62x0.dtb \
51 kirkwood-iconnect.dtb \ 51 kirkwood-iconnect.dtb \
52 kirkwood-is2.dtb \ 52 kirkwood-is2.dtb \
53 kirkwood-km_kirkwood.dtb \ 53 kirkwood-km_kirkwood.dtb \
54 kirkwood-lsxhl.dtb \ 54 kirkwood-lsxhl.dtb \
55 kirkwood-lschlv2.dtb \ 55 kirkwood-lschlv2.dtb \
56 kirkwood-net2big.dtb \ 56 kirkwood-net2big.dtb \
57 kirkwood-ns2.dtb \ 57 kirkwood-ns2.dtb \
58 kirkwood-ns2lite.dtb \ 58 kirkwood-ns2lite.dtb \
59 kirkwood-ns2max.dtb \ 59 kirkwood-ns2max.dtb \
60 kirkwood-ns2mini.dtb \ 60 kirkwood-ns2mini.dtb \
61 kirkwood-openrd-base.dtb \ 61 kirkwood-openrd-base.dtb \
62 kirkwood-openrd-client.dtb \ 62 kirkwood-openrd-client.dtb \
63 kirkwood-openrd-ultimate.dtb \ 63 kirkwood-openrd-ultimate.dtb \
64 kirkwood-pogo_e02.dtb \ 64 kirkwood-pogo_e02.dtb \
65 kirkwood-sheevaplug.dtb 65 kirkwood-sheevaplug.dtb
66 66
67 dtb-$(CONFIG_ARCH_OWL) += \ 67 dtb-$(CONFIG_ARCH_OWL) += \
68 bubblegum_96.dtb 68 bubblegum_96.dtb
69 69
70 dtb-$(CONFIG_ROCKCHIP_PX30) += \ 70 dtb-$(CONFIG_ROCKCHIP_PX30) += \
71 px30-evb.dtb \ 71 px30-evb.dtb \
72 px30-firefly.dtb 72 px30-firefly.dtb
73 73
74 dtb-$(CONFIG_ROCKCHIP_RK3036) += \ 74 dtb-$(CONFIG_ROCKCHIP_RK3036) += \
75 rk3036-sdk.dtb 75 rk3036-sdk.dtb
76 76
77 dtb-$(CONFIG_ROCKCHIP_RK3128) += \ 77 dtb-$(CONFIG_ROCKCHIP_RK3128) += \
78 rk3128-evb.dtb 78 rk3128-evb.dtb
79 79
80 dtb-$(CONFIG_ROCKCHIP_RK3188) += \ 80 dtb-$(CONFIG_ROCKCHIP_RK3188) += \
81 rk3188-radxarock.dtb 81 rk3188-radxarock.dtb
82 82
83 dtb-$(CONFIG_ROCKCHIP_RK322X) += \ 83 dtb-$(CONFIG_ROCKCHIP_RK322X) += \
84 rk3229-evb.dtb 84 rk3229-evb.dtb
85 85
86 dtb-$(CONFIG_ROCKCHIP_RK3288) += \ 86 dtb-$(CONFIG_ROCKCHIP_RK3288) += \
87 rk3288-evb.dtb \ 87 rk3288-evb.dtb \
88 rk3288-firefly.dtb \ 88 rk3288-firefly.dtb \
89 rk3288-miqi.dtb \ 89 rk3288-miqi.dtb \
90 rk3288-phycore-rdk.dtb \ 90 rk3288-phycore-rdk.dtb \
91 rk3288-popmetal.dtb \ 91 rk3288-popmetal.dtb \
92 rk3288-rock2-square.dtb \ 92 rk3288-rock2-square.dtb \
93 rk3288-tinker.dtb \ 93 rk3288-tinker.dtb \
94 rk3288-tinker-s.dtb \ 94 rk3288-tinker-s.dtb \
95 rk3288-veyron-jerry.dtb \ 95 rk3288-veyron-jerry.dtb \
96 rk3288-veyron-mickey.dtb \ 96 rk3288-veyron-mickey.dtb \
97 rk3288-veyron-minnie.dtb \ 97 rk3288-veyron-minnie.dtb \
98 rk3288-veyron-speedy.dtb \ 98 rk3288-veyron-speedy.dtb \
99 rk3288-vyasa.dtb 99 rk3288-vyasa.dtb
100 100
101 dtb-$(CONFIG_ROCKCHIP_RK3308) += \ 101 dtb-$(CONFIG_ROCKCHIP_RK3308) += \
102 rk3308-evb.dtb \ 102 rk3308-evb.dtb \
103 rk3308-roc-cc.dtb 103 rk3308-roc-cc.dtb
104 104
105 dtb-$(CONFIG_ROCKCHIP_RK3328) += \ 105 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
106 rk3328-evb.dtb \ 106 rk3328-evb.dtb \
107 rk3328-rock64.dtb 107 rk3328-rock64.dtb
108 108
109 dtb-$(CONFIG_ROCKCHIP_RK3368) += \ 109 dtb-$(CONFIG_ROCKCHIP_RK3368) += \
110 rk3368-lion.dtb \ 110 rk3368-lion.dtb \
111 rk3368-sheep.dtb \ 111 rk3368-sheep.dtb \
112 rk3368-geekbox.dtb \ 112 rk3368-geekbox.dtb \
113 rk3368-px5-evb.dtb \ 113 rk3368-px5-evb.dtb \
114 114
115 dtb-$(CONFIG_ROCKCHIP_RK3399) += \ 115 dtb-$(CONFIG_ROCKCHIP_RK3399) += \
116 rk3399-evb.dtb \ 116 rk3399-evb.dtb \
117 rk3399-ficus.dtb \ 117 rk3399-ficus.dtb \
118 rk3399-firefly.dtb \ 118 rk3399-firefly.dtb \
119 rk3399-gru-bob.dtb \ 119 rk3399-gru-bob.dtb \
120 rk3399-khadas-edge.dtb \ 120 rk3399-khadas-edge.dtb \
121 rk3399-khadas-edge-captain.dtb \ 121 rk3399-khadas-edge-captain.dtb \
122 rk3399-khadas-edge-v.dtb \ 122 rk3399-khadas-edge-v.dtb \
123 rk3399-leez-p710.dtb \ 123 rk3399-leez-p710.dtb \
124 rk3399-nanopc-t4.dtb \ 124 rk3399-nanopc-t4.dtb \
125 rk3399-nanopi-m4.dtb \ 125 rk3399-nanopi-m4.dtb \
126 rk3399-nanopi-neo4.dtb \ 126 rk3399-nanopi-neo4.dtb \
127 rk3399-orangepi.dtb \ 127 rk3399-orangepi.dtb \
128 rk3399-puma-ddr1333.dtb \ 128 rk3399-puma-ddr1333.dtb \
129 rk3399-puma-ddr1600.dtb \ 129 rk3399-puma-ddr1600.dtb \
130 rk3399-puma-ddr1866.dtb \ 130 rk3399-puma-ddr1866.dtb \
131 rk3399-roc-pc.dtb \ 131 rk3399-roc-pc.dtb \
132 rk3399-rock-pi-4.dtb \ 132 rk3399-rock-pi-4.dtb \
133 rk3399-rock960.dtb \ 133 rk3399-rock960.dtb \
134 rk3399-rockpro64.dtb 134 rk3399-rockpro64.dtb
135 135
136 dtb-$(CONFIG_ROCKCHIP_RV1108) += \ 136 dtb-$(CONFIG_ROCKCHIP_RV1108) += \
137 rv1108-elgin-r1.dtb \ 137 rv1108-elgin-r1.dtb \
138 rv1108-evb.dtb 138 rv1108-evb.dtb
139 139
140 dtb-$(CONFIG_ARCH_MESON) += \ 140 dtb-$(CONFIG_ARCH_MESON) += \
141 meson-gxbb-nanopi-k2.dtb \ 141 meson-gxbb-nanopi-k2.dtb \
142 meson-gxbb-odroidc2.dtb \ 142 meson-gxbb-odroidc2.dtb \
143 meson-gxbb-nanopi-k2.dtb \ 143 meson-gxbb-nanopi-k2.dtb \
144 meson-gxbb-p200.dtb \ 144 meson-gxbb-p200.dtb \
145 meson-gxbb-p201.dtb \ 145 meson-gxbb-p201.dtb \
146 meson-gxl-s905x-p212.dtb \ 146 meson-gxl-s905x-p212.dtb \
147 meson-gxl-s805x-libretech-ac.dtb \ 147 meson-gxl-s805x-libretech-ac.dtb \
148 meson-gxl-s905x-libretech-cc.dtb \ 148 meson-gxl-s905x-libretech-cc.dtb \
149 meson-gxl-s905x-khadas-vim.dtb \ 149 meson-gxl-s905x-khadas-vim.dtb \
150 meson-gxm-khadas-vim2.dtb \ 150 meson-gxm-khadas-vim2.dtb \
151 meson-axg-s400.dtb \ 151 meson-axg-s400.dtb \
152 meson-g12a-u200.dtb \ 152 meson-g12a-u200.dtb \
153 meson-g12a-sei510.dtb \ 153 meson-g12a-sei510.dtb \
154 meson-g12b-odroid-n2.dtb \ 154 meson-g12b-odroid-n2.dtb \
155 meson-g12b-a311d-khadas-vim3.dtb \ 155 meson-g12b-a311d-khadas-vim3.dtb \
156 meson-sm1-khadas-vim3l.dtb \ 156 meson-sm1-khadas-vim3l.dtb \
157 meson-sm1-sei610.dtb 157 meson-sm1-sei610.dtb
158 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ 158 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
159 tegra20-medcom-wide.dtb \ 159 tegra20-medcom-wide.dtb \
160 tegra20-paz00.dtb \ 160 tegra20-paz00.dtb \
161 tegra20-plutux.dtb \ 161 tegra20-plutux.dtb \
162 tegra20-seaboard.dtb \ 162 tegra20-seaboard.dtb \
163 tegra20-tec.dtb \ 163 tegra20-tec.dtb \
164 tegra20-trimslice.dtb \ 164 tegra20-trimslice.dtb \
165 tegra20-ventana.dtb \ 165 tegra20-ventana.dtb \
166 tegra20-colibri.dtb \ 166 tegra20-colibri.dtb \
167 tegra30-apalis.dtb \ 167 tegra30-apalis.dtb \
168 tegra30-beaver.dtb \ 168 tegra30-beaver.dtb \
169 tegra30-cardhu.dtb \ 169 tegra30-cardhu.dtb \
170 tegra30-colibri.dtb \ 170 tegra30-colibri.dtb \
171 tegra30-tec-ng.dtb \ 171 tegra30-tec-ng.dtb \
172 tegra114-dalmore.dtb \ 172 tegra114-dalmore.dtb \
173 tegra124-apalis.dtb \ 173 tegra124-apalis.dtb \
174 tegra124-jetson-tk1.dtb \ 174 tegra124-jetson-tk1.dtb \
175 tegra124-nyan-big.dtb \ 175 tegra124-nyan-big.dtb \
176 tegra124-cei-tk1-som.dtb \ 176 tegra124-cei-tk1-som.dtb \
177 tegra124-venice2.dtb \ 177 tegra124-venice2.dtb \
178 tegra186-p2771-0000-000.dtb \ 178 tegra186-p2771-0000-000.dtb \
179 tegra186-p2771-0000-500.dtb \ 179 tegra186-p2771-0000-500.dtb \
180 tegra210-e2220-1170.dtb \ 180 tegra210-e2220-1170.dtb \
181 tegra210-p2371-0000.dtb \ 181 tegra210-p2371-0000.dtb \
182 tegra210-p2371-2180.dtb \ 182 tegra210-p2371-2180.dtb \
183 tegra210-p2571.dtb \ 183 tegra210-p2571.dtb \
184 tegra210-p3450-0000.dtb 184 tegra210-p3450-0000.dtb
185 185
186 dtb-$(CONFIG_ARCH_MVEBU) += \ 186 dtb-$(CONFIG_ARCH_MVEBU) += \
187 armada-3720-db.dtb \ 187 armada-3720-db.dtb \
188 armada-3720-espressobin.dtb \ 188 armada-3720-espressobin.dtb \
189 armada-3720-turris-mox.dtb \ 189 armada-3720-turris-mox.dtb \
190 armada-3720-uDPU.dtb \ 190 armada-3720-uDPU.dtb \
191 armada-375-db.dtb \ 191 armada-375-db.dtb \
192 armada-388-clearfog.dtb \ 192 armada-388-clearfog.dtb \
193 armada-388-gp.dtb \ 193 armada-388-gp.dtb \
194 armada-388-helios4.dtb \ 194 armada-388-helios4.dtb \
195 armada-385-db-88f6820-amc.dtb \ 195 armada-385-db-88f6820-amc.dtb \
196 armada-385-turris-omnia.dtb \ 196 armada-385-turris-omnia.dtb \
197 armada-7040-db.dtb \ 197 armada-7040-db.dtb \
198 armada-7040-db-nand.dtb \ 198 armada-7040-db-nand.dtb \
199 armada-8040-db.dtb \ 199 armada-8040-db.dtb \
200 armada-8040-mcbin.dtb \ 200 armada-8040-mcbin.dtb \
201 armada-8040-clearfog-gt-8k.dtb \ 201 armada-8040-clearfog-gt-8k.dtb \
202 armada-xp-gp.dtb \ 202 armada-xp-gp.dtb \
203 armada-xp-maxbcm.dtb \ 203 armada-xp-maxbcm.dtb \
204 armada-xp-synology-ds414.dtb \ 204 armada-xp-synology-ds414.dtb \
205 armada-xp-theadorable.dtb \ 205 armada-xp-theadorable.dtb \
206 armada-38x-controlcenterdc.dtb \ 206 armada-38x-controlcenterdc.dtb \
207 armada-385-atl-x530.dtb \ 207 armada-385-atl-x530.dtb \
208 armada-385-atl-x530DP.dtb \ 208 armada-385-atl-x530DP.dtb \
209 armada-xp-db-xc3-24g4xg.dtb \ 209 armada-xp-db-xc3-24g4xg.dtb \
210 armada-xp-crs305-1g-4s.dtb 210 armada-xp-crs305-1g-4s.dtb
211 211
212 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ 212 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
213 uniphier-ld11-global.dtb \ 213 uniphier-ld11-global.dtb \
214 uniphier-ld11-ref.dtb 214 uniphier-ld11-ref.dtb
215 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \ 215 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
216 uniphier-ld20-global.dtb \ 216 uniphier-ld20-global.dtb \
217 uniphier-ld20-ref.dtb 217 uniphier-ld20-ref.dtb
218 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \ 218 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
219 uniphier-ld4-ref.dtb 219 uniphier-ld4-ref.dtb
220 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \ 220 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \
221 uniphier-ld6b-ref.dtb 221 uniphier-ld6b-ref.dtb
222 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \ 222 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \
223 uniphier-pro4-ace.dtb \ 223 uniphier-pro4-ace.dtb \
224 uniphier-pro4-ref.dtb \ 224 uniphier-pro4-ref.dtb \
225 uniphier-pro4-sanji.dtb 225 uniphier-pro4-sanji.dtb
226 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \ 226 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \
227 uniphier-pro5-4kbox.dtb 227 uniphier-pro5-4kbox.dtb
228 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ 228 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
229 uniphier-pxs2-gentil.dtb \ 229 uniphier-pxs2-gentil.dtb \
230 uniphier-pxs2-vodka.dtb 230 uniphier-pxs2-vodka.dtb
231 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ 231 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
232 uniphier-pxs3-ref.dtb 232 uniphier-pxs3-ref.dtb
233 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ 233 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
234 uniphier-sld8-ref.dtb 234 uniphier-sld8-ref.dtb
235 235
236 dtb-$(CONFIG_ARCH_ZYNQ) += \ 236 dtb-$(CONFIG_ARCH_ZYNQ) += \
237 bitmain-antminer-s9.dtb \ 237 bitmain-antminer-s9.dtb \
238 zynq-cc108.dtb \ 238 zynq-cc108.dtb \
239 zynq-cse-nand.dtb \ 239 zynq-cse-nand.dtb \
240 zynq-cse-nor.dtb \ 240 zynq-cse-nor.dtb \
241 zynq-cse-qspi-single.dtb \ 241 zynq-cse-qspi-single.dtb \
242 zynq-dlc20-rev1.0.dtb \ 242 zynq-dlc20-rev1.0.dtb \
243 zynq-microzed.dtb \ 243 zynq-microzed.dtb \
244 zynq-minized.dtb \ 244 zynq-minized.dtb \
245 zynq-picozed.dtb \ 245 zynq-picozed.dtb \
246 zynq-syzygy-hub.dtb \ 246 zynq-syzygy-hub.dtb \
247 zynq-topic-miami.dtb \ 247 zynq-topic-miami.dtb \
248 zynq-topic-miamilite.dtb \ 248 zynq-topic-miamilite.dtb \
249 zynq-topic-miamiplus.dtb \ 249 zynq-topic-miamiplus.dtb \
250 zynq-zc702.dtb \ 250 zynq-zc702.dtb \
251 zynq-zc706.dtb \ 251 zynq-zc706.dtb \
252 zynq-zc770-xm010.dtb \ 252 zynq-zc770-xm010.dtb \
253 zynq-zc770-xm011.dtb \ 253 zynq-zc770-xm011.dtb \
254 zynq-zc770-xm011-x16.dtb \ 254 zynq-zc770-xm011-x16.dtb \
255 zynq-zc770-xm012.dtb \ 255 zynq-zc770-xm012.dtb \
256 zynq-zc770-xm013.dtb \ 256 zynq-zc770-xm013.dtb \
257 zynq-zed.dtb \ 257 zynq-zed.dtb \
258 zynq-zturn.dtb \ 258 zynq-zturn.dtb \
259 zynq-zybo.dtb \ 259 zynq-zybo.dtb \
260 zynq-zybo-z7.dtb 260 zynq-zybo-z7.dtb
261 dtb-$(CONFIG_ARCH_ZYNQMP) += \ 261 dtb-$(CONFIG_ARCH_ZYNQMP) += \
262 avnet-ultra96-rev1.dtb \ 262 avnet-ultra96-rev1.dtb \
263 avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ 263 avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
264 zynqmp-a2197-revA.dtb \ 264 zynqmp-a2197-revA.dtb \
265 zynqmp-e-a2197-00-revA.dtb \ 265 zynqmp-e-a2197-00-revA.dtb \
266 zynqmp-g-a2197-00-revA.dtb \ 266 zynqmp-g-a2197-00-revA.dtb \
267 zynqmp-m-a2197-01-revA.dtb \ 267 zynqmp-m-a2197-01-revA.dtb \
268 zynqmp-m-a2197-02-revA.dtb \ 268 zynqmp-m-a2197-02-revA.dtb \
269 zynqmp-m-a2197-03-revA.dtb \ 269 zynqmp-m-a2197-03-revA.dtb \
270 zynqmp-p-a2197-00-revA.dtb \ 270 zynqmp-p-a2197-00-revA.dtb \
271 zynqmp-mini.dtb \ 271 zynqmp-mini.dtb \
272 zynqmp-mini-emmc0.dtb \ 272 zynqmp-mini-emmc0.dtb \
273 zynqmp-mini-emmc1.dtb \ 273 zynqmp-mini-emmc1.dtb \
274 zynqmp-mini-nand.dtb \ 274 zynqmp-mini-nand.dtb \
275 zynqmp-mini-qspi.dtb \ 275 zynqmp-mini-qspi.dtb \
276 zynqmp-zcu100-revC.dtb \ 276 zynqmp-zcu100-revC.dtb \
277 zynqmp-zcu102-revA.dtb \ 277 zynqmp-zcu102-revA.dtb \
278 zynqmp-zcu102-revB.dtb \ 278 zynqmp-zcu102-revB.dtb \
279 zynqmp-zcu102-rev1.0.dtb \ 279 zynqmp-zcu102-rev1.0.dtb \
280 zynqmp-zcu104-revA.dtb \ 280 zynqmp-zcu104-revA.dtb \
281 zynqmp-zcu104-revC.dtb \ 281 zynqmp-zcu104-revC.dtb \
282 zynqmp-zcu106-revA.dtb \ 282 zynqmp-zcu106-revA.dtb \
283 zynqmp-zcu111-revA.dtb \ 283 zynqmp-zcu111-revA.dtb \
284 zynqmp-zcu1275-revA.dtb \ 284 zynqmp-zcu1275-revA.dtb \
285 zynqmp-zcu1275-revB.dtb \ 285 zynqmp-zcu1275-revB.dtb \
286 zynqmp-zcu1285-revA.dtb \ 286 zynqmp-zcu1285-revA.dtb \
287 zynqmp-zcu208-revA.dtb \ 287 zynqmp-zcu208-revA.dtb \
288 zynqmp-zcu216-revA.dtb \ 288 zynqmp-zcu216-revA.dtb \
289 zynqmp-zc1232-revA.dtb \ 289 zynqmp-zc1232-revA.dtb \
290 zynqmp-zc1254-revA.dtb \ 290 zynqmp-zc1254-revA.dtb \
291 zynqmp-zc1751-xm015-dc1.dtb \ 291 zynqmp-zc1751-xm015-dc1.dtb \
292 zynqmp-zc1751-xm016-dc2.dtb \ 292 zynqmp-zc1751-xm016-dc2.dtb \
293 zynqmp-zc1751-xm017-dc3.dtb \ 293 zynqmp-zc1751-xm017-dc3.dtb \
294 zynqmp-zc1751-xm018-dc4.dtb \ 294 zynqmp-zc1751-xm018-dc4.dtb \
295 zynqmp-zc1751-xm019-dc5.dtb 295 zynqmp-zc1751-xm019-dc5.dtb
296 dtb-$(CONFIG_ARCH_VERSAL) += \ 296 dtb-$(CONFIG_ARCH_VERSAL) += \
297 versal-mini.dtb \ 297 versal-mini.dtb \
298 versal-mini-emmc0.dtb \ 298 versal-mini-emmc0.dtb \
299 versal-mini-emmc1.dtb 299 versal-mini-emmc1.dtb
300 dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ 300 dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
301 zynqmp-r5.dtb 301 zynqmp-r5.dtb
302 dtb-$(CONFIG_AM33XX) += \ 302 dtb-$(CONFIG_AM33XX) += \
303 am335x-baltos.dtb \ 303 am335x-baltos.dtb \
304 am335x-bone.dtb \ 304 am335x-bone.dtb \
305 am335x-boneblack.dtb \ 305 am335x-boneblack.dtb \
306 am335x-brppt1-mmc.dtb \ 306 am335x-brppt1-mmc.dtb \
307 am335x-brppt1-nand.dtb \ 307 am335x-brppt1-nand.dtb \
308 am335x-brppt1-spi.dtb \ 308 am335x-brppt1-spi.dtb \
309 am335x-brxre1.dtb \ 309 am335x-brxre1.dtb \
310 am335x-brsmarc1.dtb \ 310 am335x-brsmarc1.dtb \
311 am335x-draco.dtb \ 311 am335x-draco.dtb \
312 am335x-evm.dtb \ 312 am335x-evm.dtb \
313 am335x-evmsk.dtb \ 313 am335x-evmsk.dtb \
314 am335x-bonegreen.dtb \ 314 am335x-bonegreen.dtb \
315 am335x-icev2.dtb \ 315 am335x-icev2.dtb \
316 am335x-pocketbeagle.dtb \ 316 am335x-pocketbeagle.dtb \
317 am335x-pxm50.dtb \ 317 am335x-pxm50.dtb \
318 am335x-rut.dtb \ 318 am335x-rut.dtb \
319 am335x-shc.dtb \ 319 am335x-shc.dtb \
320 am335x-pdu001.dtb \ 320 am335x-pdu001.dtb \
321 am335x-chiliboard.dtb \ 321 am335x-chiliboard.dtb \
322 am335x-sl50.dtb \ 322 am335x-sl50.dtb \
323 am335x-base0033.dtb \ 323 am335x-base0033.dtb \
324 am335x-guardian.dtb \ 324 am335x-guardian.dtb \
325 am335x-wega-rdk.dtb 325 am335x-wega-rdk.dtb
326 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ 326 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
327 am43x-epos-evm.dtb \ 327 am43x-epos-evm.dtb \
328 am437x-idk-evm.dtb \ 328 am437x-idk-evm.dtb \
329 am4372-generic.dtb \ 329 am4372-generic.dtb \
330 am437x-cm-t43.dtb 330 am437x-cm-t43.dtb
331 dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb 331 dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
332 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb 332 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
333 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb 333 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
334 334
335 dtb-$(CONFIG_ARCH_SOCFPGA) += \ 335 dtb-$(CONFIG_ARCH_SOCFPGA) += \
336 socfpga_agilex_socdk.dtb \ 336 socfpga_agilex_socdk.dtb \
337 socfpga_arria5_secu1.dtb \ 337 socfpga_arria5_secu1.dtb \
338 socfpga_arria5_socdk.dtb \ 338 socfpga_arria5_socdk.dtb \
339 socfpga_arria10_socdk_sdmmc.dtb \ 339 socfpga_arria10_socdk_sdmmc.dtb \
340 socfpga_cyclone5_mcvevk.dtb \ 340 socfpga_cyclone5_mcvevk.dtb \
341 socfpga_cyclone5_is1.dtb \ 341 socfpga_cyclone5_is1.dtb \
342 socfpga_cyclone5_socdk.dtb \ 342 socfpga_cyclone5_socdk.dtb \
343 socfpga_cyclone5_dbm_soc1.dtb \ 343 socfpga_cyclone5_dbm_soc1.dtb \
344 socfpga_cyclone5_de0_nano_soc.dtb \ 344 socfpga_cyclone5_de0_nano_soc.dtb \
345 socfpga_cyclone5_de1_soc.dtb \ 345 socfpga_cyclone5_de1_soc.dtb \
346 socfpga_cyclone5_de10_nano.dtb \ 346 socfpga_cyclone5_de10_nano.dtb \
347 socfpga_cyclone5_sockit.dtb \ 347 socfpga_cyclone5_sockit.dtb \
348 socfpga_cyclone5_socrates.dtb \ 348 socfpga_cyclone5_socrates.dtb \
349 socfpga_cyclone5_sr1500.dtb \ 349 socfpga_cyclone5_sr1500.dtb \
350 socfpga_cyclone5_vining_fpga.dtb \ 350 socfpga_cyclone5_vining_fpga.dtb \
351 socfpga_stratix10_socdk.dtb 351 socfpga_stratix10_socdk.dtb
352 352
353 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ 353 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
354 dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb 354 dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
355 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ 355 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
356 am57xx-beagle-x15-revb1.dtb \ 356 am57xx-beagle-x15-revb1.dtb \
357 am57xx-beagle-x15-revc.dtb \ 357 am57xx-beagle-x15-revc.dtb \
358 am5729-beagleboneai.dtb \ 358 am5729-beagleboneai.dtb \
359 am574x-idk.dtb \ 359 am574x-idk.dtb \
360 am572x-idk.dtb \ 360 am572x-idk.dtb \
361 am571x-idk.dtb 361 am571x-idk.dtb
362 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb 362 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
363 363
364 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ 364 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
365 ls1021a-qds-lpuart.dtb \ 365 ls1021a-qds-lpuart.dtb \
366 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ 366 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
367 ls1021a-iot-duart.dtb ls1021a-tsn.dtb 367 ls1021a-iot-duart.dtb ls1021a-tsn.dtb
368 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ 368 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
369 fsl-ls2080a-rdb.dtb \ 369 fsl-ls2080a-rdb.dtb \
370 fsl-ls2081a-rdb.dtb \ 370 fsl-ls2081a-rdb.dtb \
371 fsl-ls2088a-rdb-qspi.dtb \ 371 fsl-ls2088a-rdb-qspi.dtb \
372 fsl-ls1088a-rdb.dtb \ 372 fsl-ls1088a-rdb.dtb \
373 fsl-ls1088a-qds.dtb \ 373 fsl-ls1088a-qds.dtb \
374 fsl-ls1028a-rdb.dtb \ 374 fsl-ls1028a-rdb.dtb \
375 fsl-ls1028a-qds.dtb \ 375 fsl-ls1028a-qds.dtb \
376 fsl-lx2160a-rdb.dtb \ 376 fsl-lx2160a-rdb.dtb \
377 fsl-lx2160a-qds.dtb 377 fsl-lx2160a-qds.dtb
378 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ 378 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
379 fsl-ls1043a-qds-lpuart.dtb \ 379 fsl-ls1043a-qds-lpuart.dtb \
380 fsl-ls1043a-rdb.dtb \ 380 fsl-ls1043a-rdb.dtb \
381 fsl-ls1046a-qds-duart.dtb \ 381 fsl-ls1046a-qds-duart.dtb \
382 fsl-ls1046a-qds-lpuart.dtb \ 382 fsl-ls1046a-qds-lpuart.dtb \
383 fsl-ls1046a-rdb.dtb \ 383 fsl-ls1046a-rdb.dtb \
384 fsl-ls1046a-frwy.dtb \ 384 fsl-ls1046a-frwy.dtb \
385 fsl-ls1012a-qds.dtb \ 385 fsl-ls1012a-qds.dtb \
386 fsl-ls1012a-rdb.dtb \ 386 fsl-ls1012a-rdb.dtb \
387 fsl-ls1012a-2g5rdb.dtb \ 387 fsl-ls1012a-2g5rdb.dtb \
388 fsl-ls1012a-frdm.dtb \ 388 fsl-ls1012a-frdm.dtb \
389 fsl-ls1012a-frwy.dtb 389 fsl-ls1012a-frwy.dtb
390 390
391 dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb 391 dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
392 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb 392 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
393 393
394 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb 394 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
395 395
396 dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ 396 dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
397 stm32429i-eval.dtb \ 397 stm32429i-eval.dtb \
398 stm32f469-disco.dtb 398 stm32f469-disco.dtb
399 399
400 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ 400 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
401 stm32f769-disco.dtb \ 401 stm32f769-disco.dtb \
402 stm32746g-eval.dtb 402 stm32746g-eval.dtb
403 dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ 403 dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
404 stm32h743i-eval.dtb 404 stm32h743i-eval.dtb
405 405
406 dtb-$(CONFIG_MACH_SUN4I) += \ 406 dtb-$(CONFIG_MACH_SUN4I) += \
407 sun4i-a10-a1000.dtb \ 407 sun4i-a10-a1000.dtb \
408 sun4i-a10-ba10-tvbox.dtb \ 408 sun4i-a10-ba10-tvbox.dtb \
409 sun4i-a10-chuwi-v7-cw0825.dtb \ 409 sun4i-a10-chuwi-v7-cw0825.dtb \
410 sun4i-a10-cubieboard.dtb \ 410 sun4i-a10-cubieboard.dtb \
411 sun4i-a10-dserve-dsrv9703c.dtb \ 411 sun4i-a10-dserve-dsrv9703c.dtb \
412 sun4i-a10-gemei-g9.dtb \ 412 sun4i-a10-gemei-g9.dtb \
413 sun4i-a10-hackberry.dtb \ 413 sun4i-a10-hackberry.dtb \
414 sun4i-a10-hyundai-a7hd.dtb \ 414 sun4i-a10-hyundai-a7hd.dtb \
415 sun4i-a10-inet1.dtb \ 415 sun4i-a10-inet1.dtb \
416 sun4i-a10-inet-3f.dtb \ 416 sun4i-a10-inet-3f.dtb \
417 sun4i-a10-inet-3w.dtb \ 417 sun4i-a10-inet-3w.dtb \
418 sun4i-a10-inet97fv2.dtb \ 418 sun4i-a10-inet97fv2.dtb \
419 sun4i-a10-inet9f-rev03.dtb \ 419 sun4i-a10-inet9f-rev03.dtb \
420 sun4i-a10-itead-iteaduino-plus.dtb \ 420 sun4i-a10-itead-iteaduino-plus.dtb \
421 sun4i-a10-jesurun-q5.dtb \ 421 sun4i-a10-jesurun-q5.dtb \
422 sun4i-a10-marsboard.dtb \ 422 sun4i-a10-marsboard.dtb \
423 sun4i-a10-mini-xplus.dtb \ 423 sun4i-a10-mini-xplus.dtb \
424 sun4i-a10-mk802.dtb \ 424 sun4i-a10-mk802.dtb \
425 sun4i-a10-mk802ii.dtb \ 425 sun4i-a10-mk802ii.dtb \
426 sun4i-a10-olinuxino-lime.dtb \ 426 sun4i-a10-olinuxino-lime.dtb \
427 sun4i-a10-pcduino.dtb \ 427 sun4i-a10-pcduino.dtb \
428 sun4i-a10-pcduino2.dtb \ 428 sun4i-a10-pcduino2.dtb \
429 sun4i-a10-pov-protab2-ips9.dtb 429 sun4i-a10-pov-protab2-ips9.dtb
430 dtb-$(CONFIG_MACH_SUN5I) += \ 430 dtb-$(CONFIG_MACH_SUN5I) += \
431 sun5i-a10s-auxtek-t003.dtb \ 431 sun5i-a10s-auxtek-t003.dtb \
432 sun5i-a10s-auxtek-t004.dtb \ 432 sun5i-a10s-auxtek-t004.dtb \
433 sun5i-a10s-mk802.dtb \ 433 sun5i-a10s-mk802.dtb \
434 sun5i-a10s-olinuxino-micro.dtb \ 434 sun5i-a10s-olinuxino-micro.dtb \
435 sun5i-a10s-r7-tv-dongle.dtb \ 435 sun5i-a10s-r7-tv-dongle.dtb \
436 sun5i-a10s-wobo-i5.dtb \ 436 sun5i-a10s-wobo-i5.dtb \
437 sun5i-a13-ampe-a76.dtb \ 437 sun5i-a13-ampe-a76.dtb \
438 sun5i-a13-difrnce-dit4350.dtb \ 438 sun5i-a13-difrnce-dit4350.dtb \
439 sun5i-a13-empire-electronix-d709.dtb \ 439 sun5i-a13-empire-electronix-d709.dtb \
440 sun5i-a13-empire-electronix-m712.dtb \ 440 sun5i-a13-empire-electronix-m712.dtb \
441 sun5i-a13-hsg-h702.dtb \ 441 sun5i-a13-hsg-h702.dtb \
442 sun5i-a13-inet-86vs.dtb \ 442 sun5i-a13-inet-86vs.dtb \
443 sun5i-a13-inet-98v-rev2.dtb \ 443 sun5i-a13-inet-98v-rev2.dtb \
444 sun5i-a13-olinuxino.dtb \ 444 sun5i-a13-olinuxino.dtb \
445 sun5i-a13-olinuxino-micro.dtb \ 445 sun5i-a13-olinuxino-micro.dtb \
446 sun5i-a13-q8-tablet.dtb \ 446 sun5i-a13-q8-tablet.dtb \
447 sun5i-a13-utoo-p66.dtb \ 447 sun5i-a13-utoo-p66.dtb \
448 sun5i-gr8-chip-pro.dtb \ 448 sun5i-gr8-chip-pro.dtb \
449 sun5i-r8-chip.dtb 449 sun5i-r8-chip.dtb
450 dtb-$(CONFIG_MACH_SUN6I) += \ 450 dtb-$(CONFIG_MACH_SUN6I) += \
451 sun6i-a31-app4-evb1.dtb \ 451 sun6i-a31-app4-evb1.dtb \
452 sun6i-a31-colombus.dtb \ 452 sun6i-a31-colombus.dtb \
453 sun6i-a31-hummingbird.dtb \ 453 sun6i-a31-hummingbird.dtb \
454 sun6i-a31-i7.dtb \ 454 sun6i-a31-i7.dtb \
455 sun6i-a31-m9.dtb \ 455 sun6i-a31-m9.dtb \
456 sun6i-a31-mele-a1000g-quad.dtb \ 456 sun6i-a31-mele-a1000g-quad.dtb \
457 sun6i-a31-mixtile-loftq.dtb \ 457 sun6i-a31-mixtile-loftq.dtb \
458 sun6i-a31s-colorfly-e708-q1.dtb \ 458 sun6i-a31s-colorfly-e708-q1.dtb \
459 sun6i-a31s-cs908.dtb \ 459 sun6i-a31s-cs908.dtb \
460 sun6i-a31s-inet-q972.dtb \ 460 sun6i-a31s-inet-q972.dtb \
461 sun6i-a31s-primo81.dtb \ 461 sun6i-a31s-primo81.dtb \
462 sun6i-a31s-sina31s.dtb \ 462 sun6i-a31s-sina31s.dtb \
463 sun6i-a31s-sinovoip-bpi-m2.dtb \ 463 sun6i-a31s-sinovoip-bpi-m2.dtb \
464 sun6i-a31s-yones-toptech-bs1078-v2.dtb 464 sun6i-a31s-yones-toptech-bs1078-v2.dtb
465 dtb-$(CONFIG_MACH_SUN7I) += \ 465 dtb-$(CONFIG_MACH_SUN7I) += \
466 sun7i-a20-ainol-aw1.dtb \ 466 sun7i-a20-ainol-aw1.dtb \
467 sun7i-a20-bananapi.dtb \ 467 sun7i-a20-bananapi.dtb \
468 sun7i-a20-bananapi-m1-plus.dtb \ 468 sun7i-a20-bananapi-m1-plus.dtb \
469 sun7i-a20-bananapro.dtb \ 469 sun7i-a20-bananapro.dtb \
470 sun7i-a20-cubieboard2.dtb \ 470 sun7i-a20-cubieboard2.dtb \
471 sun7i-a20-cubietruck.dtb \ 471 sun7i-a20-cubietruck.dtb \
472 sun7i-a20-hummingbird.dtb \ 472 sun7i-a20-hummingbird.dtb \
473 sun7i-a20-i12-tvbox.dtb \ 473 sun7i-a20-i12-tvbox.dtb \
474 sun7i-a20-icnova-swac.dtb \ 474 sun7i-a20-icnova-swac.dtb \
475 sun7i-a20-itead-ibox.dtb \ 475 sun7i-a20-itead-ibox.dtb \
476 sun7i-a20-lamobo-r1.dtb \ 476 sun7i-a20-lamobo-r1.dtb \
477 sun7i-a20-m3.dtb \ 477 sun7i-a20-m3.dtb \
478 sun7i-a20-m5.dtb \ 478 sun7i-a20-m5.dtb \
479 sun7i-a20-mk808c.dtb \ 479 sun7i-a20-mk808c.dtb \
480 sun7i-a20-olimex-som-evb.dtb \ 480 sun7i-a20-olimex-som-evb.dtb \
481 sun7i-a20-olimex-som204-evb.dtb \ 481 sun7i-a20-olimex-som204-evb.dtb \
482 sun7i-a20-olimex-som204-evb-emmc.dtb \ 482 sun7i-a20-olimex-som204-evb-emmc.dtb \
483 sun7i-a20-olinuxino-lime.dtb \ 483 sun7i-a20-olinuxino-lime.dtb \
484 sun7i-a20-olinuxino-lime2.dtb \ 484 sun7i-a20-olinuxino-lime2.dtb \
485 sun7i-a20-olinuxino-lime2-emmc.dtb \ 485 sun7i-a20-olinuxino-lime2-emmc.dtb \
486 sun7i-a20-olinuxino-micro.dtb \ 486 sun7i-a20-olinuxino-micro.dtb \
487 sun7i-a20-olinuxino-micro-emmc.dtb \ 487 sun7i-a20-olinuxino-micro-emmc.dtb \
488 sun7i-a20-orangepi.dtb \ 488 sun7i-a20-orangepi.dtb \
489 sun7i-a20-orangepi-mini.dtb \ 489 sun7i-a20-orangepi-mini.dtb \
490 sun7i-a20-pcduino3.dtb \ 490 sun7i-a20-pcduino3.dtb \
491 sun7i-a20-pcduino3-nano.dtb \ 491 sun7i-a20-pcduino3-nano.dtb \
492 sun7i-a20-primo73.dtb \ 492 sun7i-a20-primo73.dtb \
493 sun7i-a20-wexler-tab7200.dtb \ 493 sun7i-a20-wexler-tab7200.dtb \
494 sun7i-a20-wits-pro-a20-dkt.dtb \ 494 sun7i-a20-wits-pro-a20-dkt.dtb \
495 sun7i-a20-yones-toptech-bd1078.dtb 495 sun7i-a20-yones-toptech-bd1078.dtb
496 dtb-$(CONFIG_MACH_SUN8I_A23) += \ 496 dtb-$(CONFIG_MACH_SUN8I_A23) += \
497 sun8i-a23-evb.dtb \ 497 sun8i-a23-evb.dtb \
498 sun8i-a23-gt90h-v4.dtb \ 498 sun8i-a23-gt90h-v4.dtb \
499 sun8i-a23-inet86dz.dtb \ 499 sun8i-a23-inet86dz.dtb \
500 sun8i-a23-polaroid-mid2407pxe03.dtb \ 500 sun8i-a23-polaroid-mid2407pxe03.dtb \
501 sun8i-a23-polaroid-mid2809pxe04.dtb \ 501 sun8i-a23-polaroid-mid2809pxe04.dtb \
502 sun8i-a23-q8-tablet.dtb 502 sun8i-a23-q8-tablet.dtb
503 dtb-$(CONFIG_MACH_SUN8I_A33) += \ 503 dtb-$(CONFIG_MACH_SUN8I_A33) += \
504 sun8i-a33-ga10h-v1.1.dtb \ 504 sun8i-a33-ga10h-v1.1.dtb \
505 sun8i-a33-inet-d978-rev2.dtb \ 505 sun8i-a33-inet-d978-rev2.dtb \
506 sun8i-a33-olinuxino.dtb \ 506 sun8i-a33-olinuxino.dtb \
507 sun8i-a33-q8-tablet.dtb \ 507 sun8i-a33-q8-tablet.dtb \
508 sun8i-a33-sinlinx-sina33.dtb \ 508 sun8i-a33-sinlinx-sina33.dtb \
509 sun8i-r16-bananapi-m2m.dtb \ 509 sun8i-r16-bananapi-m2m.dtb \
510 sun8i-r16-nintendo-nes-classic-edition.dtb \ 510 sun8i-r16-nintendo-nes-classic-edition.dtb \
511 sun8i-r16-parrot.dtb 511 sun8i-r16-parrot.dtb
512 dtb-$(CONFIG_MACH_SUN8I_A83T) += \ 512 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
513 sun8i-a83t-allwinner-h8homlet-v2.dtb \ 513 sun8i-a83t-allwinner-h8homlet-v2.dtb \
514 sun8i-a83t-bananapi-m3.dtb \ 514 sun8i-a83t-bananapi-m3.dtb \
515 sun8i-a83t-cubietruck-plus.dtb \ 515 sun8i-a83t-cubietruck-plus.dtb \
516 sun8i-a83t-tbs-a711.dtb 516 sun8i-a83t-tbs-a711.dtb
517 dtb-$(CONFIG_MACH_SUN8I_H3) += \ 517 dtb-$(CONFIG_MACH_SUN8I_H3) += \
518 sun8i-h2-plus-bananapi-m2-zero.dtb \ 518 sun8i-h2-plus-bananapi-m2-zero.dtb \
519 sun8i-h2-plus-libretech-all-h3-cc.dtb \ 519 sun8i-h2-plus-libretech-all-h3-cc.dtb \
520 sun8i-h2-plus-orangepi-r1.dtb \ 520 sun8i-h2-plus-orangepi-r1.dtb \
521 sun8i-h2-plus-orangepi-zero.dtb \ 521 sun8i-h2-plus-orangepi-zero.dtb \
522 sun8i-h3-bananapi-m2-plus.dtb \ 522 sun8i-h3-bananapi-m2-plus.dtb \
523 sun8i-h3-bananapi-m2-plus-v1.2.dtb \ 523 sun8i-h3-bananapi-m2-plus-v1.2.dtb \
524 sun8i-h3-beelink-x2.dtb \ 524 sun8i-h3-beelink-x2.dtb \
525 sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ 525 sun8i-h3-emlid-neutis-n5h3-devboard.dtb \
526 sun8i-h3-libretech-all-h3-cc.dtb \ 526 sun8i-h3-libretech-all-h3-cc.dtb \
527 sun8i-h3-mapleboard-mp130.dtb \ 527 sun8i-h3-mapleboard-mp130.dtb \
528 sun8i-h3-nanopi-duo2.dtb \ 528 sun8i-h3-nanopi-duo2.dtb \
529 sun8i-h3-nanopi-m1.dtb \ 529 sun8i-h3-nanopi-m1.dtb \
530 sun8i-h3-nanopi-m1-plus.dtb \ 530 sun8i-h3-nanopi-m1-plus.dtb \
531 sun8i-h3-nanopi-neo.dtb \ 531 sun8i-h3-nanopi-neo.dtb \
532 sun8i-h3-nanopi-neo-air.dtb \ 532 sun8i-h3-nanopi-neo-air.dtb \
533 sun8i-h3-orangepi-2.dtb \ 533 sun8i-h3-orangepi-2.dtb \
534 sun8i-h3-orangepi-lite.dtb \ 534 sun8i-h3-orangepi-lite.dtb \
535 sun8i-h3-orangepi-one.dtb \ 535 sun8i-h3-orangepi-one.dtb \
536 sun8i-h3-orangepi-pc.dtb \ 536 sun8i-h3-orangepi-pc.dtb \
537 sun8i-h3-orangepi-pc-plus.dtb \ 537 sun8i-h3-orangepi-pc-plus.dtb \
538 sun8i-h3-orangepi-plus.dtb \ 538 sun8i-h3-orangepi-plus.dtb \
539 sun8i-h3-orangepi-plus2e.dtb \ 539 sun8i-h3-orangepi-plus2e.dtb \
540 sun8i-h3-orangepi-zero-plus2.dtb \ 540 sun8i-h3-orangepi-zero-plus2.dtb \
541 sun8i-h3-rervision-dvk.dtb 541 sun8i-h3-rervision-dvk.dtb
542 dtb-$(CONFIG_MACH_SUN8I_R40) += \ 542 dtb-$(CONFIG_MACH_SUN8I_R40) += \
543 sun8i-r40-bananapi-m2-ultra.dtb \ 543 sun8i-r40-bananapi-m2-ultra.dtb \
544 sun8i-v40-bananapi-m2-berry.dtb 544 sun8i-v40-bananapi-m2-berry.dtb
545 dtb-$(CONFIG_MACH_SUN8I_V3S) += \ 545 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
546 sun8i-v3s-licheepi-zero.dtb 546 sun8i-v3s-licheepi-zero.dtb
547 dtb-$(CONFIG_MACH_SUN50I_H5) += \ 547 dtb-$(CONFIG_MACH_SUN50I_H5) += \
548 sun50i-h5-bananapi-m2-plus.dtb \ 548 sun50i-h5-bananapi-m2-plus.dtb \
549 sun50i-h5-emlid-neutis-n5-devboard.dtb \ 549 sun50i-h5-emlid-neutis-n5-devboard.dtb \
550 sun50i-h5-libretech-all-h3-cc.dtb \ 550 sun50i-h5-libretech-all-h3-cc.dtb \
551 sun50i-h5-libretech-all-h3-it.dtb \ 551 sun50i-h5-libretech-all-h3-it.dtb \
552 sun50i-h5-libretech-all-h5-cc.dtb \ 552 sun50i-h5-libretech-all-h5-cc.dtb \
553 sun50i-h5-nanopi-neo2.dtb \ 553 sun50i-h5-nanopi-neo2.dtb \
554 sun50i-h5-nanopi-neo-plus2.dtb \ 554 sun50i-h5-nanopi-neo-plus2.dtb \
555 sun50i-h5-orangepi-zero-plus.dtb \ 555 sun50i-h5-orangepi-zero-plus.dtb \
556 sun50i-h5-orangepi-pc2.dtb \ 556 sun50i-h5-orangepi-pc2.dtb \
557 sun50i-h5-orangepi-prime.dtb \ 557 sun50i-h5-orangepi-prime.dtb \
558 sun50i-h5-orangepi-zero-plus2.dtb 558 sun50i-h5-orangepi-zero-plus2.dtb
559 dtb-$(CONFIG_MACH_SUN50I_H6) += \ 559 dtb-$(CONFIG_MACH_SUN50I_H6) += \
560 sun50i-h6-beelink-gs1.dtb \ 560 sun50i-h6-beelink-gs1.dtb \
561 sun50i-h6-orangepi-lite2.dtb \ 561 sun50i-h6-orangepi-lite2.dtb \
562 sun50i-h6-orangepi-one-plus.dtb \ 562 sun50i-h6-orangepi-one-plus.dtb \
563 sun50i-h6-pine-h64.dtb 563 sun50i-h6-pine-h64.dtb
564 dtb-$(CONFIG_MACH_SUN50I) += \ 564 dtb-$(CONFIG_MACH_SUN50I) += \
565 sun50i-a64-amarula-relic.dtb \ 565 sun50i-a64-amarula-relic.dtb \
566 sun50i-a64-bananapi-m64.dtb \ 566 sun50i-a64-bananapi-m64.dtb \
567 sun50i-a64-nanopi-a64.dtb \ 567 sun50i-a64-nanopi-a64.dtb \
568 sun50i-a64-oceanic-5205-5inmfd.dtb \ 568 sun50i-a64-oceanic-5205-5inmfd.dtb \
569 sun50i-a64-olinuxino.dtb \ 569 sun50i-a64-olinuxino.dtb \
570 sun50i-a64-olinuxino-emmc.dtb \ 570 sun50i-a64-olinuxino-emmc.dtb \
571 sun50i-a64-orangepi-win.dtb \ 571 sun50i-a64-orangepi-win.dtb \
572 sun50i-a64-pine64-lts.dtb \ 572 sun50i-a64-pine64-lts.dtb \
573 sun50i-a64-pine64-plus.dtb \ 573 sun50i-a64-pine64-plus.dtb \
574 sun50i-a64-pine64.dtb \ 574 sun50i-a64-pine64.dtb \
575 sun50i-a64-pinebook.dtb \ 575 sun50i-a64-pinebook.dtb \
576 sun50i-a64-sopine-baseboard.dtb \ 576 sun50i-a64-sopine-baseboard.dtb \
577 sun50i-a64-teres-i.dtb 577 sun50i-a64-teres-i.dtb
578 dtb-$(CONFIG_MACH_SUN9I) += \ 578 dtb-$(CONFIG_MACH_SUN9I) += \
579 sun9i-a80-optimus.dtb \ 579 sun9i-a80-optimus.dtb \
580 sun9i-a80-cubieboard4.dtb \ 580 sun9i-a80-cubieboard4.dtb \
581 sun9i-a80-cx-a99.dtb 581 sun9i-a80-cx-a99.dtb
582 582
583 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ 583 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
584 vf610-colibri.dtb \ 584 vf610-colibri.dtb \
585 vf610-twr.dtb \ 585 vf610-twr.dtb \
586 vf610-pcm052.dtb \ 586 vf610-pcm052.dtb \
587 vf610-bk4r1.dtb 587 vf610-bk4r1.dtb
588 588
589 dtb-$(CONFIG_MX28) += \ 589 dtb-$(CONFIG_MX28) += \
590 imx28-xea.dtb 590 imx28-xea.dtb
591 591
592 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ 592 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
593 imx53-kp.dtb \ 593 imx53-kp.dtb \
594 imx53-m53menlo.dtb 594 imx53-m53menlo.dtb
595 595
596 ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) 596 ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
597 dtb-y += \ 597 dtb-y += \
598 imx6dl-aristainetos2_4.dtb \ 598 imx6dl-aristainetos2_4.dtb \
599 imx6dl-aristainetos2_7.dtb \ 599 imx6dl-aristainetos2_7.dtb \
600 imx6dl-aristainetos2b_4.dtb \ 600 imx6dl-aristainetos2b_4.dtb \
601 imx6dl-aristainetos2b_7.dtb \ 601 imx6dl-aristainetos2b_7.dtb \
602 imx6dl-aristainetos2b_csl_4.dtb \ 602 imx6dl-aristainetos2b_csl_4.dtb \
603 imx6dl-aristainetos2b_csl_7.dtb \ 603 imx6dl-aristainetos2b_csl_7.dtb \
604 imx6dl-aristainetos2c_4.dtb \ 604 imx6dl-aristainetos2c_4.dtb \
605 imx6dl-aristainetos2c_7.dtb \ 605 imx6dl-aristainetos2c_7.dtb \
606 imx6dl-brppt2.dtb \ 606 imx6dl-brppt2.dtb \
607 imx6dl-cubox-i.dtb \ 607 imx6dl-cubox-i.dtb \
608 imx6dl-cubox-i-emmc-som-v15.dtb \ 608 imx6dl-cubox-i-emmc-som-v15.dtb \
609 imx6dl-cubox-i-som-v15.dtb \ 609 imx6dl-cubox-i-som-v15.dtb \
610 imx6dl-dhcom-pdk2.dtb \ 610 imx6dl-dhcom-pdk2.dtb \
611 imx6dl-hummingboard2.dtb \ 611 imx6dl-hummingboard2.dtb \
612 imx6dl-hummingboard2-emmc-som-v15.dtb \ 612 imx6dl-hummingboard2-emmc-som-v15.dtb \
613 imx6dl-hummingboard2-som-v15.dtb \ 613 imx6dl-hummingboard2-som-v15.dtb \
614 imx6dl-hummingboard.dtb \ 614 imx6dl-hummingboard.dtb \
615 imx6dl-hummingboard-emmc-som-v15.dtb \ 615 imx6dl-hummingboard-emmc-som-v15.dtb \
616 imx6dl-hummingboard-som-v15.dtb \ 616 imx6dl-hummingboard-som-v15.dtb \
617 imx6dl-icore.dtb \ 617 imx6dl-icore.dtb \
618 imx6dl-icore-mipi.dtb \ 618 imx6dl-icore-mipi.dtb \
619 imx6dl-icore-rqs.dtb \ 619 imx6dl-icore-rqs.dtb \
620 imx6dl-mamoj.dtb \ 620 imx6dl-mamoj.dtb \
621 imx6dl-nitrogen6x.dtb \ 621 imx6dl-nitrogen6x.dtb \
622 imx6dl-pico.dtb \ 622 imx6dl-pico.dtb \
623 imx6dl-sabreauto.dtb \ 623 imx6dl-sabreauto.dtb \
624 imx6dl-sabreauto-ecspi.dtb \ 624 imx6dl-sabreauto-ecspi.dtb \
625 imx6dl-sabreauto-gpmi-weim.dtb \ 625 imx6dl-sabreauto-gpmi-weim.dtb \
626 imx6dl-sabresd.dtb \ 626 imx6dl-sabresd.dtb \
627 imx6dl-arm2.dtb \ 627 imx6dl-arm2.dtb \
628 imx6dl-wandboard-revb1.dtb \ 628 imx6dl-wandboard-revb1.dtb \
629 629
630 endif 630 endif
631 631
632 ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),) 632 ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
633 dtb-y += \ 633 dtb-y += \
634 imx6-apalis.dtb \ 634 imx6-apalis.dtb \
635 imx6q-cm-fx6.dtb \ 635 imx6q-cm-fx6.dtb \
636 imx6q-cubox-i.dtb \ 636 imx6q-cubox-i.dtb \
637 imx6q-cubox-i-emmc-som-v15.dtb \ 637 imx6q-cubox-i-emmc-som-v15.dtb \
638 imx6q-cubox-i-som-v15.dtb \ 638 imx6q-cubox-i-som-v15.dtb \
639 imx6q-dhcom-pdk2.dtb \ 639 imx6q-dhcom-pdk2.dtb \
640 imx6q-display5.dtb \ 640 imx6q-display5.dtb \
641 imx6q-hummingboard2.dtb \ 641 imx6q-hummingboard2.dtb \
642 imx6q-hummingboard2-emmc-som-v15.dtb \ 642 imx6q-hummingboard2-emmc-som-v15.dtb \
643 imx6q-hummingboard2-som-v15.dtb \ 643 imx6q-hummingboard2-som-v15.dtb \
644 imx6q-hummingboard.dtb \ 644 imx6q-hummingboard.dtb \
645 imx6q-hummingboard-emmc-som-v15.dtb \ 645 imx6q-hummingboard-emmc-som-v15.dtb \
646 imx6q-hummingboard-som-v15.dtb \ 646 imx6q-hummingboard-som-v15.dtb \
647 imx6q-icore.dtb \ 647 imx6q-icore.dtb \
648 imx6q-icore-mipi.dtb \ 648 imx6q-icore-mipi.dtb \
649 imx6q-icore-rqs.dtb \ 649 imx6q-icore-rqs.dtb \
650 imx6q-kp.dtb \ 650 imx6q-kp.dtb \
651 imx6q-logicpd.dtb \ 651 imx6q-logicpd.dtb \
652 imx6q-mccmon6.dtb\ 652 imx6q-mccmon6.dtb\
653 imx6q-nitrogen6x.dtb \ 653 imx6q-nitrogen6x.dtb \
654 imx6q-novena.dtb \ 654 imx6q-novena.dtb \
655 imx6q-pico.dtb \ 655 imx6q-pico.dtb \
656 imx6q-sabreauto.dtb \ 656 imx6q-sabreauto.dtb \
657 imx6q-sabreauto-ecspi.dtb \ 657 imx6q-sabreauto-ecspi.dtb \
658 imx6q-sabreauto-gpmi-weim.dtb \ 658 imx6q-sabreauto-gpmi-weim.dtb \
659 imx6q-sabrelite.dtb \ 659 imx6q-sabrelite.dtb \
660 imx6q-sabresd.dtb \ 660 imx6q-sabresd.dtb \
661 imx6q-arm2.dtb \ 661 imx6q-arm2.dtb \
662 imx6q-pop-arm2.dtb \ 662 imx6q-pop-arm2.dtb \
663 imx6q-tbs2910.dtb \ 663 imx6q-tbs2910.dtb \
664 imx6q-wandboard-revb1.dtb \ 664 imx6q-wandboard-revb1.dtb \
665 imx6qp-sabreauto.dtb \ 665 imx6qp-sabreauto.dtb \
666 imx6qp-sabreauto-ecspi.dtb \ 666 imx6qp-sabreauto-ecspi.dtb \
667 imx6qp-sabreauto-gpmi-weim.dtb \ 667 imx6qp-sabreauto-gpmi-weim.dtb \
668 imx6qp-sabresd.dtb \ 668 imx6qp-sabresd.dtb \
669 imx6qp-wandboard-revd1.dtb \ 669 imx6qp-wandboard-revd1.dtb \
670 670
671 endif 671 endif
672 672
673 dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb 673 dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
674 674
675 dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb \ 675 dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb \
676 imx6sll-lpddr2-val.dtb \ 676 imx6sll-lpddr2-val.dtb \
677 imx6sll-lpddr3-val.dtb \ 677 imx6sll-lpddr3-val.dtb \
678 imx6sll-lpddr3-val-ecspi.dtb 678 imx6sll-lpddr3-val-ecspi.dtb
679 679
680 dtb-$(CONFIG_MX6SX) += \ 680 dtb-$(CONFIG_MX6SX) += \
681 imx6sx-14x14-val.dtb \ 681 imx6sx-14x14-val.dtb \
682 imx6sx-17x17-val.dtb \ 682 imx6sx-17x17-val.dtb \
683 imx6sx-17x17-val-ecspi.dtb \ 683 imx6sx-17x17-val-ecspi.dtb \
684 imx6sx-17x17-val-gpmi-weim.dtb \ 684 imx6sx-17x17-val-gpmi-weim.dtb \
685 imx6sx-19x19-val.dtb \ 685 imx6sx-19x19-val.dtb \
686 imx6sx-19x19-val-ecspi.dtb \ 686 imx6sx-19x19-val-ecspi.dtb \
687 imx6sx-19x19-val-gpmi-weim.dtb \ 687 imx6sx-19x19-val-gpmi-weim.dtb \
688 imx6sx-sabreauto.dtb \ 688 imx6sx-sabreauto.dtb \
689 imx6sx-sdb.dtb \ 689 imx6sx-sdb.dtb \
690 imx6sx-sdb-emmc.dtb \ 690 imx6sx-sdb-emmc.dtb \
691 imx6sx-softing-vining-2000.dtb 691 imx6sx-softing-vining-2000.dtb
692 692
693 dtb-$(CONFIG_MX6UL) += \ 693 dtb-$(CONFIG_MX6UL) += \
694 imx6ul-geam.dtb \ 694 imx6ul-geam.dtb \
695 imx6ul-isiot-emmc.dtb \ 695 imx6ul-isiot-emmc.dtb \
696 imx6ul-isiot-nand.dtb \ 696 imx6ul-isiot-nand.dtb \
697 imx6ul-opos6uldev.dtb \ 697 imx6ul-opos6uldev.dtb \
698 imx6ul-14x14-ddr3-val.dtb \ 698 imx6ul-14x14-ddr3-val.dtb \
699 imx6ul-14x14-ddr3-val-emmc.dtb \ 699 imx6ul-14x14-ddr3-val-emmc.dtb \
700 imx6ul-14x14-ddr3-val-gpmi-weim.dtb \ 700 imx6ul-14x14-ddr3-val-gpmi-weim.dtb \
701 imx6ul-14x14-lpddr2-val.dtb \ 701 imx6ul-14x14-lpddr2-val.dtb \
702 imx6ul-14x14-evk.dtb \ 702 imx6ul-14x14-evk.dtb \
703 imx6ul-14x14-evk-emmc.dtb \ 703 imx6ul-14x14-evk-emmc.dtb \
704 imx6ul-14x14-evk-gpmi-weim.dtb \ 704 imx6ul-14x14-evk-gpmi-weim.dtb \
705 imx6ul-9x9-evk.dtb \ 705 imx6ul-9x9-evk.dtb \
706 imx6ul-liteboard.dtb \ 706 imx6ul-liteboard.dtb \
707 imx6ul-phytec-segin-ff-rdk-nand.dtb \ 707 imx6ul-phytec-segin-ff-rdk-nand.dtb \
708 imx6ul-pico-hobbit.dtb \ 708 imx6ul-pico-hobbit.dtb \
709 imx6ul-pico-pi.dtb 709 imx6ul-pico-pi.dtb
710 710
711 dtb-$(CONFIG_MX6ULL) += \ 711 dtb-$(CONFIG_MX6ULL) += \
712 imx6ull-14x14-ddr3-val.dtb \ 712 imx6ull-14x14-ddr3-val.dtb \
713 imx6ull-14x14-ddr3-val-epdc.dtb \ 713 imx6ull-14x14-ddr3-val-epdc.dtb \
714 imx6ull-14x14-ddr3-val-emmc.dtb \ 714 imx6ull-14x14-ddr3-val-emmc.dtb \
715 imx6ull-14x14-ddr3-val-gpmi-weim.dtb \ 715 imx6ull-14x14-ddr3-val-gpmi-weim.dtb \
716 imx6ull-14x14-ddr3-val-tsc.dtb \ 716 imx6ull-14x14-ddr3-val-tsc.dtb \
717 imx6ull-14x14-evk.dtb \ 717 imx6ull-14x14-evk.dtb \
718 imx6ull-14x14-evk-emmc.dtb \ 718 imx6ull-14x14-evk-emmc.dtb \
719 imx6ull-14x14-evk-gpmi-weim.dtb \ 719 imx6ull-14x14-evk-gpmi-weim.dtb \
720 imx6ull-9x9-evk.dtb \ 720 imx6ull-9x9-evk.dtb \
721 imx6ull-colibri.dtb \ 721 imx6ull-colibri.dtb \
722 imx6ull-phytec-segin-ff-rdk-emmc.dtb \ 722 imx6ull-phytec-segin-ff-rdk-emmc.dtb \
723 imx6ull-dart-6ul.dtb \ 723 imx6ull-dart-6ul.dtb \
724 imx6ull-somlabs-visionsom.dtb \ 724 imx6ull-somlabs-visionsom.dtb \
725 imx6ulz-14x14-evk.dtb \ 725 imx6ulz-14x14-evk.dtb \
726 imx6ulz-14x14-evk-emmc.dtb \ 726 imx6ulz-14x14-evk-emmc.dtb \
727 imx6ulz-14x14-evk-gpmi-weim.dtb 727 imx6ulz-14x14-evk-gpmi-weim.dtb
728 728
729 dtb-$(CONFIG_ARCH_MX6) += \ 729 dtb-$(CONFIG_ARCH_MX6) += \
730 imx6-apalis.dtb \ 730 imx6-apalis.dtb \
731 imx6-colibri.dtb 731 imx6-colibri.dtb
732 732
733 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ 733 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
734 imx7d-sdb-qspi.dtb \ 734 imx7d-sdb-qspi.dtb \
735 imx7d-sdb-epdc.dtb \ 735 imx7d-sdb-epdc.dtb \
736 imx7d-sdb-gpmi-weim.dtb \ 736 imx7d-sdb-gpmi-weim.dtb \
737 imx7d-sdb-reva.dtb \ 737 imx7d-sdb-reva.dtb \
738 imx7-colibri-emmc.dtb \ 738 imx7-colibri-emmc.dtb \
739 imx7-colibri-rawnand.dtb \ 739 imx7-colibri-rawnand.dtb \
740 imx7s-warp.dtb \ 740 imx7s-warp.dtb \
741 imx7d-meerkat96.dtb \ 741 imx7d-meerkat96.dtb \
742 imx7d-pico-pi.dtb \ 742 imx7d-pico-pi.dtb \
743 imx7d-pico-hobbit.dtb \ 743 imx7d-pico-hobbit.dtb \
744 imx7d-12x12-lpddr3-val.dtb \ 744 imx7d-12x12-lpddr3-val.dtb \
745 imx7d-12x12-lpddr3-val-ecspi.dtb \ 745 imx7d-12x12-lpddr3-val-ecspi.dtb \
746 imx7d-12x12-lpddr3-val-qspi.dtb \ 746 imx7d-12x12-lpddr3-val-qspi.dtb \
747 imx7d-12x12-ddr3-val.dtb \ 747 imx7d-12x12-ddr3-val.dtb \
748 imx7d-19x19-ddr3-val.dtb \ 748 imx7d-19x19-ddr3-val.dtb \
749 imx7d-19x19-lpddr2-val.dtb \ 749 imx7d-19x19-lpddr2-val.dtb \
750 imx7d-19x19-lpddr3-val.dtb 750 imx7d-19x19-lpddr3-val.dtb
751 751
752 752
753 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ 753 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
754 imx7ulp-10x10-val.dtb \ 754 imx7ulp-10x10-val.dtb \
755 imx7ulp-14x14-val.dtb \ 755 imx7ulp-14x14-val.dtb \
756 imx7ulp-evk.dtb \ 756 imx7ulp-evk.dtb \
757 imx7ulp-evk-emmc.dtb \ 757 imx7ulp-evk-emmc.dtb \
758 imx7ulp-evk-qspi.dtb 758 imx7ulp-evk-qspi.dtb
759 759
760 dtb-$(CONFIG_ARCH_IMX8) += \ 760 dtb-$(CONFIG_ARCH_IMX8) += \
761 fsl-imx8qm-apalis.dtb \ 761 fsl-imx8qm-apalis.dtb \
762 fsl-imx8qm-mek.dtb \ 762 fsl-imx8qm-mek.dtb \
763 fsl-imx8qm-ddr4-val.dtb \ 763 fsl-imx8qm-ddr4-val.dtb \
764 fsl-imx8qm-lpddr4-val.dtb \ 764 fsl-imx8qm-lpddr4-val.dtb \
765 imx8qm-rom7720-a1.dtb \ 765 imx8qm-rom7720-a1.dtb \
766 fsl-imx8qxp-ai_ml.dtb \ 766 fsl-imx8qxp-ai_ml.dtb \
767 fsl-imx8qxp-colibri.dtb \ 767 fsl-imx8qxp-colibri.dtb \
768 fsl-imx8qxp-mek.dtb \ 768 fsl-imx8qxp-mek.dtb \
769 fsl-imx8qxp-lpddr4-val.dtb \ 769 fsl-imx8qxp-lpddr4-val.dtb \
770 fsl-imx8qxp-lpddr4-val-gpmi-nand.dtb \ 770 fsl-imx8qxp-lpddr4-val-gpmi-nand.dtb \
771 fsl-imx8qxp-17x17-val.dtb \ 771 fsl-imx8qxp-17x17-val.dtb \
772 fsl-imx8dx-17x17-val.dtb \ 772 fsl-imx8dx-17x17-val.dtb \
773 fsl-imx8dx-mek.dtb \ 773 fsl-imx8dx-mek.dtb \
774 fsl-imx8dxl-phantom-mek.dtb \ 774 fsl-imx8dxl-phantom-mek.dtb \
775 fsl-imx8dxl-evk.dtb \ 775 fsl-imx8dxl-evk.dtb \
776 fsl-imx8dxl-ddr3-evk.dtb \ 776 fsl-imx8dxl-ddr3-evk.dtb \
777 imx8-deneb.dtb \ 777 imx8-deneb.dtb \
778 imx8-giedi.dtb 778 imx8-giedi.dtb
779 779
780 dtb-$(CONFIG_ARCH_IMX8M) += \ 780 dtb-$(CONFIG_ARCH_IMX8M) += \
781 imx8mm-evk.dtb \ 781 imx8mm-evk.dtb \
782 imx8mm-ddr4-evk.dtb \ 782 imx8mm-ddr4-evk.dtb \
783 imx8mm-ddr3l-val.dtb \ 783 imx8mm-ddr3l-val.dtb \
784 imx8mm-ddr4-val.dtb \ 784 imx8mm-ddr4-val.dtb \
785 imx8mm-verdin.dtb \ 785 imx8mm-verdin.dtb \
786 imx8mn-ddr4-evk.dtb \ 786 imx8mn-ddr4-evk.dtb \
787 imx8mn-evk.dtb \ 787 imx8mn-evk.dtb \
788 imx8mq-ddr3l-val.dtb \ 788 imx8mq-ddr3l-val.dtb \
789 imx8mq-ddr4-val.dtb \ 789 imx8mq-ddr4-val.dtb \
790 imx8mq-evk.dtb \ 790 imx8mq-evk.dtb \
791 imx8mp-evk.dtb \ 791 imx8mp-evk.dtb \
792 imx8mm-ab2.dtb 792 imx8mm-ab2.dtb \
793 imx8mn-ddr4-ab2.dtb \
794 imx8mn-ab2.dtb
793 795
794 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb 796 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
795 797
796 dtb-$(CONFIG_RCAR_GEN2) += \ 798 dtb-$(CONFIG_RCAR_GEN2) += \
797 r8a7790-lager-u-boot.dtb \ 799 r8a7790-lager-u-boot.dtb \
798 r8a7790-stout-u-boot.dtb \ 800 r8a7790-stout-u-boot.dtb \
799 r8a7791-koelsch-u-boot.dtb \ 801 r8a7791-koelsch-u-boot.dtb \
800 r8a7791-porter-u-boot.dtb \ 802 r8a7791-porter-u-boot.dtb \
801 r8a7792-blanche-u-boot.dtb \ 803 r8a7792-blanche-u-boot.dtb \
802 r8a7793-gose-u-boot.dtb \ 804 r8a7793-gose-u-boot.dtb \
803 r8a7794-alt-u-boot.dtb \ 805 r8a7794-alt-u-boot.dtb \
804 r8a7794-silk-u-boot.dtb 806 r8a7794-silk-u-boot.dtb
805 807
806 dtb-$(CONFIG_RCAR_GEN3) += \ 808 dtb-$(CONFIG_RCAR_GEN3) += \
807 r8a7795-h3ulcb-u-boot.dtb \ 809 r8a7795-h3ulcb-u-boot.dtb \
808 r8a7795-salvator-x-u-boot.dtb \ 810 r8a7795-salvator-x-u-boot.dtb \
809 r8a7796-m3ulcb-u-boot.dtb \ 811 r8a7796-m3ulcb-u-boot.dtb \
810 r8a7796-salvator-x-u-boot.dtb \ 812 r8a7796-salvator-x-u-boot.dtb \
811 r8a77965-m3nulcb-u-boot.dtb \ 813 r8a77965-m3nulcb-u-boot.dtb \
812 r8a77965-salvator-x-u-boot.dtb \ 814 r8a77965-salvator-x-u-boot.dtb \
813 r8a77970-eagle-u-boot.dtb \ 815 r8a77970-eagle-u-boot.dtb \
814 r8a77980-condor-u-boot.dtb \ 816 r8a77980-condor-u-boot.dtb \
815 r8a77990-ebisu-u-boot.dtb \ 817 r8a77990-ebisu-u-boot.dtb \
816 r8a77995-draak-u-boot.dtb 818 r8a77995-draak-u-boot.dtb
817 819
818 dtb-$(CONFIG_RZA1) += \ 820 dtb-$(CONFIG_RZA1) += \
819 r7s72100-gr-peach-u-boot.dtb 821 r7s72100-gr-peach-u-boot.dtb
820 822
821 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ 823 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
822 keystone-k2l-evm.dtb \ 824 keystone-k2l-evm.dtb \
823 keystone-k2e-evm.dtb \ 825 keystone-k2e-evm.dtb \
824 keystone-k2g-evm.dtb \ 826 keystone-k2g-evm.dtb \
825 keystone-k2g-generic.dtb \ 827 keystone-k2g-generic.dtb \
826 keystone-k2g-ice.dtb 828 keystone-k2g-ice.dtb
827 829
828 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb 830 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
829 831
830 dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb 832 dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
831 833
832 dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb 834 dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb
833 835
834 dtb-$(CONFIG_TARGET_MEESC) += at91sam9263ek.dtb 836 dtb-$(CONFIG_TARGET_MEESC) += at91sam9263ek.dtb
835 837
836 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb 838 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
837 839
838 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb 840 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb
839 841
840 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ 842 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
841 at91sam9260ek.dtb \ 843 at91sam9260ek.dtb \
842 at91sam9g20ek.dtb \ 844 at91sam9g20ek.dtb \
843 at91sam9g20ek_2mmc.dtb 845 at91sam9g20ek_2mmc.dtb
844 846
845 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb 847 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
846 848
847 dtb-$(CONFIG_TARGET_PM9G45) += at91sam9m10g45ek.dtb 849 dtb-$(CONFIG_TARGET_PM9G45) += at91sam9m10g45ek.dtb
848 850
849 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ 851 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
850 at91sam9g15ek.dtb \ 852 at91sam9g15ek.dtb \
851 at91sam9g25ek.dtb \ 853 at91sam9g25ek.dtb \
852 at91sam9g35ek.dtb \ 854 at91sam9g35ek.dtb \
853 at91sam9x25ek.dtb \ 855 at91sam9x25ek.dtb \
854 at91sam9x35ek.dtb 856 at91sam9x35ek.dtb
855 857
856 dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb 858 dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
857 859
858 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb 860 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
859 861
860 dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \ 862 dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
861 at91sam9g25-gardena-smart-gateway.dtb 863 at91sam9g25-gardena-smart-gateway.dtb
862 864
863 dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb 865 dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
864 866
865 dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb 867 dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb
866 868
867 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ 869 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
868 logicpd-som-lv-35xx-devkit.dtb \ 870 logicpd-som-lv-35xx-devkit.dtb \
869 logicpd-som-lv-37xx-devkit.dtb \ 871 logicpd-som-lv-37xx-devkit.dtb \
870 logicpd-torpedo-35xx-devkit.dtb \ 872 logicpd-torpedo-35xx-devkit.dtb \
871 logicpd-torpedo-37xx-devkit.dtb 873 logicpd-torpedo-37xx-devkit.dtb
872 874
873 dtb-$(CONFIG_TARGET_OMAP3_EVM) += \ 875 dtb-$(CONFIG_TARGET_OMAP3_EVM) += \
874 omap3-evm-37xx.dtb \ 876 omap3-evm-37xx.dtb \
875 omap3-evm.dtb 877 omap3-evm.dtb
876 878
877 dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \ 879 dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
878 omap3-beagle-xm-ab.dtb \ 880 omap3-beagle-xm-ab.dtb \
879 omap3-beagle-xm.dtb \ 881 omap3-beagle-xm.dtb \
880 omap3-beagle.dtb 882 omap3-beagle.dtb
881 883
882 dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \ 884 dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
883 omap3-igep0020.dtb 885 omap3-igep0020.dtb
884 886
885 dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ 887 dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
886 at91-sama5d2_ptc_ek.dtb 888 at91-sama5d2_ptc_ek.dtb
887 889
888 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ 890 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
889 at91-sama5d2_xplained.dtb 891 at91-sama5d2_xplained.dtb
890 892
891 dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ 893 dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
892 at91-sama5d27_som1_ek.dtb 894 at91-sama5d27_som1_ek.dtb
893 895
894 dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \ 896 dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
895 at91-sama5d27_wlsom1_ek.dtb 897 at91-sama5d27_wlsom1_ek.dtb
896 898
897 dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \ 899 dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \
898 at91-sama5d2_icp.dtb 900 at91-sama5d2_icp.dtb
899 901
900 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ 902 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
901 sama5d31ek.dtb \ 903 sama5d31ek.dtb \
902 sama5d33ek.dtb \ 904 sama5d33ek.dtb \
903 sama5d34ek.dtb \ 905 sama5d34ek.dtb \
904 sama5d35ek.dtb \ 906 sama5d35ek.dtb \
905 sama5d36ek.dtb \ 907 sama5d36ek.dtb \
906 sama5d36ek_cmp.dtb 908 sama5d36ek_cmp.dtb
907 909
908 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ 910 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
909 at91-sama5d3_xplained.dtb 911 at91-sama5d3_xplained.dtb
910 912
911 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ 913 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
912 at91-sama5d4ek.dtb 914 at91-sama5d4ek.dtb
913 915
914 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ 916 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
915 at91-sama5d4_xplained.dtb 917 at91-sama5d4_xplained.dtb
916 918
917 dtb-$(CONFIG_TARGET_VINCO) += \ 919 dtb-$(CONFIG_TARGET_VINCO) += \
918 at91-vinco.dtb 920 at91-vinco.dtb
919 921
920 dtb-$(CONFIG_ARCH_BCM283X) += \ 922 dtb-$(CONFIG_ARCH_BCM283X) += \
921 bcm2835-rpi-a.dtb \ 923 bcm2835-rpi-a.dtb \
922 bcm2835-rpi-a-plus.dtb \ 924 bcm2835-rpi-a-plus.dtb \
923 bcm2835-rpi-b.dtb \ 925 bcm2835-rpi-b.dtb \
924 bcm2835-rpi-b-plus.dtb \ 926 bcm2835-rpi-b-plus.dtb \
925 bcm2835-rpi-b-rev2.dtb \ 927 bcm2835-rpi-b-rev2.dtb \
926 bcm2835-rpi-cm1-io1.dtb \ 928 bcm2835-rpi-cm1-io1.dtb \
927 bcm2835-rpi-zero.dtb \ 929 bcm2835-rpi-zero.dtb \
928 bcm2835-rpi-zero-w.dtb\ 930 bcm2835-rpi-zero-w.dtb\
929 bcm2836-rpi-2-b.dtb \ 931 bcm2836-rpi-2-b.dtb \
930 bcm2837-rpi-3-a-plus.dtb \ 932 bcm2837-rpi-3-a-plus.dtb \
931 bcm2837-rpi-3-b.dtb \ 933 bcm2837-rpi-3-b.dtb \
932 bcm2837-rpi-3-b-plus.dtb \ 934 bcm2837-rpi-3-b-plus.dtb \
933 bcm2837-rpi-cm3-io3.dtb 935 bcm2837-rpi-cm3-io3.dtb
934 936
935 dtb-$(CONFIG_ARCH_BCM63158) += \ 937 dtb-$(CONFIG_ARCH_BCM63158) += \
936 bcm963158.dtb 938 bcm963158.dtb
937 939
938 dtb-$(CONFIG_ARCH_BCM68360) += \ 940 dtb-$(CONFIG_ARCH_BCM68360) += \
939 bcm968360bg.dtb 941 bcm968360bg.dtb
940 942
941 dtb-$(CONFIG_ARCH_BCM6858) += \ 943 dtb-$(CONFIG_ARCH_BCM6858) += \
942 bcm968580xref.dtb 944 bcm968580xref.dtb
943 945
944 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb 946 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
945 947
946 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb 948 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
947 949
948 dtb-$(CONFIG_STM32MP15x) += \ 950 dtb-$(CONFIG_STM32MP15x) += \
949 stm32mp157a-dk1.dtb \ 951 stm32mp157a-dk1.dtb \
950 stm32mp157a-avenger96.dtb \ 952 stm32mp157a-avenger96.dtb \
951 stm32mp157c-dk2.dtb \ 953 stm32mp157c-dk2.dtb \
952 stm32mp157c-ed1.dtb \ 954 stm32mp157c-ed1.dtb \
953 stm32mp157c-ev1.dtb \ 955 stm32mp157c-ev1.dtb \
954 stm32mp15xx-dhcom-pdk2.dtb 956 stm32mp15xx-dhcom-pdk2.dtb
955 957
956 dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb 958 dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
957 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ 959 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
958 k3-j721e-r5-common-proc-board.dtb 960 k3-j721e-r5-common-proc-board.dtb
959 961
960 dtb-$(CONFIG_ARCH_MEDIATEK) += \ 962 dtb-$(CONFIG_ARCH_MEDIATEK) += \
961 mt7622-rfb.dtb \ 963 mt7622-rfb.dtb \
962 mt7623n-bananapi-bpi-r2.dtb \ 964 mt7623n-bananapi-bpi-r2.dtb \
963 mt7629-rfb.dtb \ 965 mt7629-rfb.dtb \
964 mt8512-bm1-emmc.dtb \ 966 mt8512-bm1-emmc.dtb \
965 mt8516-pumpkin.dtb \ 967 mt8516-pumpkin.dtb \
966 mt8518-ap1-emmc.dtb 968 mt8518-ap1-emmc.dtb
967 969
968 dtb-$(CONFIG_TARGET_GE_BX50V3) += \ 970 dtb-$(CONFIG_TARGET_GE_BX50V3) += \
969 imx6q-bx50v3.dtb \ 971 imx6q-bx50v3.dtb \
970 imx6q-b850v3.dtb \ 972 imx6q-b850v3.dtb \
971 imx6q-b650v3.dtb \ 973 imx6q-b650v3.dtb \
972 imx6q-b450v3.dtb 974 imx6q-b450v3.dtb
973 975
974 dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb 976 dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
975 977
976 dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb 978 dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
977 dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb 979 dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
978 dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb 980 dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
979 981
980 dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb 982 dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
981 983
982 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb 984 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
983 985
984 targets += $(dtb-y) 986 targets += $(dtb-y)
985 987
986 # Add any required device tree compiler flags here 988 # Add any required device tree compiler flags here
987 DTC_FLAGS += 989 DTC_FLAGS +=
988 990
989 PHONY += dtbs 991 PHONY += dtbs
990 dtbs: $(addprefix $(obj)/, $(dtb-y)) 992 dtbs: $(addprefix $(obj)/, $(dtb-y))
991 @: 993 @:
992 994
993 clean-files := *.dtb *.dtbo *_HS 995 clean-files := *.dtb *.dtbo *_HS
994 996
arch/arm/dts/imx8mn-ab2-u-boot.dtsi
Diff comments   View file @ 5187303
File was created 1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 NXP
4 */
5
6 / {
7 firmware {
8 optee {
9 compatible = "linaro,optee-tz";
10 method = "smc";
11 };
12 };
13 };
14
15 &{/soc@0} {
16 u-boot,dm-pre-reloc;
17 u-boot,dm-spl;
18 };
19
20 &clk {
21 u-boot,dm-spl;
22 u-boot,dm-pre-reloc;
23 /delete-property/ assigned-clocks;
24 /delete-property/ assigned-clock-parents;
25 /delete-property/ assigned-clock-rates;
26 };
27
28 &osc_24m {
29 u-boot,dm-spl;
30 u-boot,dm-pre-reloc;
31 };
32
33 &aips1 {
34 u-boot,dm-spl;
35 u-boot,dm-pre-reloc;
36 };
37
38 &aips2 {
39 u-boot,dm-spl;
40 };
41
42 &aips3 {
43 u-boot,dm-spl;
44 };
45
46 &iomuxc {
47 u-boot,dm-spl;
48 };
49
50 &reg_usdhc2_vmmc {
51 u-boot,dm-spl;
52 };
53
54 &pinctrl_reg_usdhc2_vmmc {
55 u-boot,dm-spl;
56 };
57
58 &pinctrl_uart2 {
59 u-boot,dm-spl;
60 };
61
62 &pinctrl_usdhc2_gpio {
63 u-boot,dm-spl;
64 };
65
66 &pinctrl_usdhc2 {
67 u-boot,dm-spl;
68 };
69
70 &pinctrl_usdhc3 {
71 u-boot,dm-spl;
72 };
73
74 &gpio1 {
75 u-boot,dm-spl;
76 };
77
78 &gpio2 {
79 u-boot,dm-spl;
80 };
81
82 &gpio3 {
83 u-boot,dm-spl;
84 };
85
86 &gpio4 {
87 u-boot,dm-spl;
88 };
89
90 &gpio5 {
91 u-boot,dm-spl;
92 };
93
94 &uart2 {
95 u-boot,dm-spl;
96 };
97
98 &usdhc1 {
99 u-boot,dm-spl;
100 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
101 assigned-clock-rates = <400000000>;
102 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
103 };
104
105 &usdhc2 {
106 u-boot,dm-spl;
107 sd-uhs-sdr104;
108 sd-uhs-ddr50;
109 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
110 assigned-clock-rates = <400000000>;
111 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
112 };
113
114 &usdhc3 {
115 u-boot,dm-spl;
116 mmc-hs400-1_8v;
117 mmc-hs400-enhanced-strobe;
118 assigned-clocks = <&clk IMX8MN_CLK_USDHC3>;
119 assigned-clock-rates = <400000000>;
120 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
121 };
122
123 &flexspi {
124 assigned-clock-rates = <100000000>;
125 assigned-clocks = <&clk IMX8MN_CLK_QSPI>;
126 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
127 };
128
arch/arm/dts/imx8mn-ab2.dts
Diff comments   View file @ 5187303
File was created 1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 NXP
4 */
5
6 /dts-v1/;
7
8 #include "imx8mn.dtsi"
9
10 / {
11 model = "NXP i.MX8MNano LPDDR4 Audio board 2.0";
12 compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
13
14 chosen {
15 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
16 stdout-path = &uart2;
17 };
18
19 reg_usdhc2_vmmc: regulator-usdhc2 {
20 compatible = "regulator-fixed";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
23 regulator-name = "VSD_3V3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
27 enable-active-high;
28 startup-delay-us = <100>;
29 off-on-delay-us = <12000>;
30 };
31
32 reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
33 compatible = "regulator-fixed";
34 regulator-name = "ab2_ana_pwr";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
40 enable-active-high;
41 };
42
43 reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
44 compatible = "regulator-fixed";
45 regulator-name = "ab2_vdd_pwr_5v0";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
49 enable-active-high;
50 startup-delay-us = <100>;
51 u-boot,off-on-delay-us = <12000>;
52 };
53 };
54
55 &iomuxc {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_hog_1>;
58
59 imx8mn-evk {
60 pinctrl_hog_1: hoggrp-1 {
61 fsl,pins = <
62 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
63 >;
64 };
65
66 pinctrl_fec1: fec1grp {
67 fsl,pins = <
68 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
69 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
70 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
71 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
72 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
73 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
74 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
75 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
76 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
77 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
78 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
79 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
80 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
81 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
82 MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16
83 >;
84 };
85
86 pinctrl_flexspi0: flexspi0grp {
87 fsl,pins = <
88 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
89 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
90
91 MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084
92 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
93 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
94 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
95 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
96 >;
97 };
98
99 pinctrl_i2c1: i2c1grp {
100 fsl,pins = <
101 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
102 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
103 >;
104 };
105
106 pinctrl_i2c2: i2c2grp {
107 fsl,pins = <
108 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
109 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
110 >;
111 };
112
113 pinctrl_i2c3: i2c3grp {
114 fsl,pins = <
115 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
116 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
117 >;
118 };
119
120 pinctrl_i2c1_gpio: i2c1grp-gpio {
121 fsl,pins = <
122 MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
123 MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
124 >;
125 };
126
127 pinctrl_i2c2_gpio: i2c2grp-gpio {
128 fsl,pins = <
129 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
130 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
131 >;
132 };
133
134 pinctrl_i2c3_gpio: i2c3grp-gpio {
135 fsl,pins = <
136 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
137 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
138 >;
139 };
140
141 pinctrl_pmic: pmicirq {
142 fsl,pins = <
143 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
144 >;
145 };
146
147
148 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
149 fsl,pins = <
150 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
151 >;
152 };
153
154 pinctrl_ab2_ana_pwr: ab2anapwrgrp {
155 fsl,pins = <
156 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
157 >;
158 };
159
160 pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
161 fsl,pins = <
162 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
163 >;
164 };
165
166 pinctrl_uart2: uart1grp {
167 fsl,pins = <
168 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
169 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
170 >;
171 };
172
173 pinctrl_usdhc2_gpio: usdhc2grpgpio {
174 fsl,pins = <
175 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
176 >;
177 };
178
179 pinctrl_usdhc2: usdhc2grp {
180 fsl,pins = <
181 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
182 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
183 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
184 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
185 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
186 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
187 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
188 >;
189 };
190
191 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
192 fsl,pins = <
193 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
194 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
195 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
196 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
197 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
198 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
199 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
200 >;
201 };
202
203 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
204 fsl,pins = <
205 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
206 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
207 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
208 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
209 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
210 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
211 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
212 >;
213 };
214
215 pinctrl_usdhc3: usdhc3grp {
216 fsl,pins = <
217 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
218 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
219 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
220 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
221 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
222 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
223 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
224 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
225 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
226 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
227 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
228 >;
229 };
230
231 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
232 fsl,pins = <
233 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
234 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
235 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
236 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
237 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
238 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
239 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
240 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
241 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
242 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
243 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
244 >;
245 };
246
247 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
248 fsl,pins = <
249 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
250 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
251 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
252 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
253 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
254 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
255 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
256 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
257 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
258 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
259 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
260 >;
261 };
262
263 pinctrl_wdog: wdoggrp {
264 fsl,pins = <
265 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
266 >;
267 };
268
269 pinctrl_mipi_dsi_en: mipi_dsi_en {
270 fsl,pins = <
271 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
272 >;
273 };
274 };
275 };
276
277 &i2c1 {
278 clock-frequency = <400000>;
279 pinctrl-names = "default", "gpio";
280 pinctrl-0 = <&pinctrl_i2c1>;
281 pinctrl-1 = <&pinctrl_i2c1_gpio>;
282 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
283 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
284 status = "okay";
285
286 pmic: pca9450@25 {
287 reg = <0x25>;
288 compatible = "nxp,pca9450b";
289 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
290 pinctrl-0 = <&pinctrl_pmic>;
291 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
292
293 regulators {
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 pca9450,pmic-buck2-uses-i2c-dvs;
298 /* Run/Standby voltage */
299 pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
300
301 buck1_reg: regulator@0 {
302 reg = <0>;
303 regulator-compatible = "buck1";
304 regulator-min-microvolt = <600000>;
305 regulator-max-microvolt = <2187500>;
306 regulator-boot-on;
307 regulator-always-on;
308 regulator-ramp-delay = <3125>;
309 };
310
311 buck2_reg: regulator@1 {
312 reg = <1>;
313 regulator-compatible = "buck2";
314 regulator-min-microvolt = <600000>;
315 regulator-max-microvolt = <2187500>;
316 regulator-boot-on;
317 regulator-always-on;
318 regulator-ramp-delay = <3125>;
319 };
320
321 buck3_reg: regulator@2 {
322 reg = <2>;
323 regulator-compatible = "buck3";
324 regulator-min-microvolt = <600000>;
325 regulator-max-microvolt = <2187500>;
326 regulator-boot-on;
327 regulator-always-on;
328 };
329
330 buck4_reg: regulator@3 {
331 reg = <3>;
332 regulator-compatible = "buck4";
333 regulator-min-microvolt = <600000>;
334 regulator-max-microvolt = <3400000>;
335 regulator-boot-on;
336 regulator-always-on;
337 };
338
339 buck5_reg: regulator@4 {
340 reg = <4>;
341 regulator-compatible = "buck5";
342 regulator-min-microvolt = <600000>;
343 regulator-max-microvolt = <3400000>;
344 regulator-boot-on;
345 regulator-always-on;
346 };
347
348 buck6_reg: regulator@5 {
349 reg = <5>;
350 regulator-compatible = "buck6";
351 regulator-min-microvolt = <600000>;
352 regulator-max-microvolt = <3400000>;
353 regulator-boot-on;
354 regulator-always-on;
355 };
356
357 ldo1_reg: regulator@6 {
358 reg = <6>;
359 regulator-compatible = "ldo1";
360 regulator-min-microvolt = <1600000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-boot-on;
363 regulator-always-on;
364 };
365
366 ldo2_reg: regulator@7 {
367 reg = <7>;
368 regulator-compatible = "ldo2";
369 regulator-min-microvolt = <800000>;
370 regulator-max-microvolt = <1150000>;
371 regulator-boot-on;
372 regulator-always-on;
373 };
374
375 ldo3_reg: regulator@8 {
376 reg = <8>;
377 regulator-compatible = "ldo3";
378 regulator-min-microvolt = <800000>;
379 regulator-max-microvolt = <3300000>;
380 regulator-boot-on;
381 regulator-always-on;
382 };
383
384 ldo4_reg: regulator@9 {
385 reg = <9>;
386 regulator-compatible = "ldo4";
387 regulator-min-microvolt = <800000>;
388 regulator-max-microvolt = <3300000>;
389 regulator-boot-on;
390 regulator-always-on;
391 };
392
393 ldo5_reg: regulator@10 {
394 reg = <10>;
395 regulator-compatible = "ldo5";
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <3300000>;
398 };
399
400 };
401 };
402 };
403
404 &i2c2 {
405 clock-frequency = <400000>;
406 pinctrl-names = "default", "gpio";
407 pinctrl-0 = <&pinctrl_i2c2>;
408 pinctrl-1 = <&pinctrl_i2c2_gpio>;
409 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
410 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
411 status = "okay";
412 };
413
414 &i2c3 {
415 clock-frequency = <100000>;
416 pinctrl-names = "default", "gpio";
417 pinctrl-0 = <&pinctrl_i2c3>;
418 pinctrl-1 = <&pinctrl_i2c3_gpio>;
419 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
420 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
421 status = "okay";
422 };
423
424 &flexspi {
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_flexspi0>;
427 status = "okay";
428
429 flash0: mt25qu256aba@0 {
430 reg = <0>;
431 compatible = "jedec,spi-nor";
432 spi-max-frequency = <80000000>;
433 spi-tx-bus-width = <4>;
434 spi-rx-bus-width = <4>;
435 };
436 };
437
438 &fec1 {
439 pinctrl-names = "default";
440 pinctrl-0 = <&pinctrl_fec1>;
441 phy-mode = "rgmii-id";
442 phy-handle = <&ethphy0>;
443 phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
444 phy-reset-post-delay = <150>;
445 phy-reset-duration = <10>;
446 fsl,magic-packet;
447 status = "okay";
448
449 mdio {
450 #address-cells = <1>;
451 #size-cells = <0>;
452
453 ethphy0: ethernet-phy@0 {
454 compatible = "ethernet-phy-ieee802.3-c22";
455 reg = <1>;
456 eee-broken-1000t;
457 };
458 };
459 };
460
461 &snvs_pwrkey {
462 status = "okay";
463 };
464
465 &uart2 { /* console */
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_uart2>;
468 status = "okay";
469 };
470
471 &usdhc2 {
472 pinctrl-names = "default", "state_100mhz", "state_200mhz";
473 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
474 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
475 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
476 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
477 bus-width = <4>;
478 vmmc-supply = <&reg_usdhc2_vmmc>;
479 status = "okay";
480 };
481
482 &usdhc3 {
483 pinctrl-names = "default", "state_100mhz", "state_200mhz";
484 pinctrl-0 = <&pinctrl_usdhc3>;
485 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
486 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
487 bus-width = <8>;
488 non-removable;
489 status = "okay";
490 };
491
492 &wdog1 {
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_wdog>;
495 fsl,ext-reset-output;
496 status = "okay";
497 };
498
arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
Diff comments   View file @ 5187303
File was created 1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 NXP
4 */
5
6 / {
7 firmware {
8 optee {
9 compatible = "linaro,optee-tz";
10 method = "smc";
11 };
12 };
13 };
14
15 &{/soc@0} {
16 u-boot,dm-pre-reloc;
17 u-boot,dm-spl;
18 };
19
20 &clk {
21 u-boot,dm-spl;
22 u-boot,dm-pre-reloc;
23 /delete-property/ assigned-clocks;
24 /delete-property/ assigned-clock-parents;
25 /delete-property/ assigned-clock-rates;
26 };
27
28 &osc_24m {
29 u-boot,dm-spl;
30 u-boot,dm-pre-reloc;
31 };
32
33 &aips1 {
34 u-boot,dm-spl;
35 u-boot,dm-pre-reloc;
36 };
37
38 &aips2 {
39 u-boot,dm-spl;
40 };
41
42 &aips3 {
43 u-boot,dm-spl;
44 };
45
46 &iomuxc {
47 u-boot,dm-spl;
48 };
49
50 &reg_usdhc2_vmmc {
51 u-boot,dm-spl;
52 };
53
54 &pinctrl_reg_usdhc2_vmmc {
55 u-boot,dm-spl;
56 };
57
58 &pinctrl_uart2 {
59 u-boot,dm-spl;
60 };
61
62 &pinctrl_usdhc2_gpio {
63 u-boot,dm-spl;
64 };
65
66 &pinctrl_usdhc2 {
67 u-boot,dm-spl;
68 };
69
70 &pinctrl_usdhc3 {
71 u-boot,dm-spl;
72 };
73
74 &gpio1 {
75 u-boot,dm-spl;
76 };
77
78 &gpio2 {
79 u-boot,dm-spl;
80 };
81
82 &gpio3 {
83 u-boot,dm-spl;
84 };
85
86 &gpio4 {
87 u-boot,dm-spl;
88 };
89
90 &gpio5 {
91 u-boot,dm-spl;
92 };
93
94 &uart2 {
95 u-boot,dm-spl;
96 };
97
98 &usdhc1 {
99 u-boot,dm-spl;
100 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
101 assigned-clock-rates = <400000000>;
102 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
103 };
104
105 &usdhc2 {
106 u-boot,dm-spl;
107 sd-uhs-sdr104;
108 sd-uhs-ddr50;
109 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
110 assigned-clock-rates = <400000000>;
111 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
112 };
113
114 &usdhc3 {
115 u-boot,dm-spl;
116 mmc-hs400-1_8v;
117 mmc-hs400-enhanced-strobe;
118 assigned-clocks = <&clk IMX8MN_CLK_USDHC3>;
119 assigned-clock-rates = <400000000>;
120 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
121 };
122
123 &flexspi {
124 assigned-clock-rates = <100000000>;
125 assigned-clocks = <&clk IMX8MN_CLK_QSPI>;
126 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
127 };
128
arch/arm/dts/imx8mn-ddr4-ab2.dts
Diff comments   View file @ 5187303
File was created 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2020 NXP
4 */
5
6 /dts-v1/;
7
8 #include "imx8mn.dtsi"
9
10 / {
11 model = "NXP i.MX8MNano DDR4 Audio board 2.0";
12 compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
13
14 chosen {
15 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
16 stdout-path = &uart2;
17 };
18
19 reg_usdhc2_vmmc: regulator-usdhc2 {
20 compatible = "regulator-fixed";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
23 regulator-name = "VSD_3V3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
27 enable-active-high;
28 startup-delay-us = <100>;
29 off-on-delay-us = <12000>;
30 };
31
32 reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
33 compatible = "regulator-fixed";
34 regulator-name = "ab2_ana_pwr";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
40 enable-active-high;
41 };
42
43 reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
44 compatible = "regulator-fixed";
45 regulator-name = "ab2_vdd_pwr_5v0";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
49 enable-active-high;
50 startup-delay-us = <100>;
51 u-boot,off-on-delay-us = <12000>;
52 };
53 };
54
55 &iomuxc {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_hog_1>;
58
59 imx8mn-evk {
60 pinctrl_hog_1: hoggrp-1 {
61 fsl,pins = <
62 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
63 >;
64 };
65
66 pinctrl_fec1: fec1grp {
67 fsl,pins = <
68 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
69 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
70 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
71 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
72 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
73 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
74 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
75 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
76 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
77 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
78 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
79 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
80 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
81 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
82 MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16
83 >;
84 };
85
86 pinctrl_flexspi0: flexspi0grp {
87 fsl,pins = <
88 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
89 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
90
91 MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084
92 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
93 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
94 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
95 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
96 >;
97 };
98
99 pinctrl_i2c1: i2c1grp {
100 fsl,pins = <
101 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
102 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
103 >;
104 };
105
106 pinctrl_i2c2: i2c2grp {
107 fsl,pins = <
108 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
109 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
110 >;
111 };
112
113 pinctrl_i2c3: i2c3grp {
114 fsl,pins = <
115 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
116 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
117 >;
118 };
119
120 pinctrl_i2c1_gpio: i2c1grp-gpio {
121 fsl,pins = <
122 MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
123 MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
124 >;
125 };
126
127 pinctrl_i2c2_gpio: i2c2grp-gpio {
128 fsl,pins = <
129 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
130 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
131 >;
132 };
133
134 pinctrl_i2c3_gpio: i2c3grp-gpio {
135 fsl,pins = <
136 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
137 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
138 >;
139 };
140
141 pinctrl_pmic: pmicirq {
142 fsl,pins = <
143 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
144 >;
145 };
146
147 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
148 fsl,pins = <
149 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
150 >;
151 };
152
153 pinctrl_ab2_ana_pwr: ab2anapwrgrp {
154 fsl,pins = <
155 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
156 >;
157 };
158
159 pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
160 fsl,pins = <
161 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
162 >;
163 };
164
165 pinctrl_uart2: uart1grp {
166 fsl,pins = <
167 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
168 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
169 >;
170 };
171
172 pinctrl_usdhc2_gpio: usdhc2grpgpio {
173 fsl,pins = <
174 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
175 >;
176 };
177
178 pinctrl_usdhc2: usdhc2grp {
179 fsl,pins = <
180 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
181 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
182 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
183 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
184 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
185 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
186 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
187 >;
188 };
189
190 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
191 fsl,pins = <
192 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
193 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
194 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
195 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
196 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
197 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
198 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
199 >;
200 };
201
202 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
203 fsl,pins = <
204 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
205 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
206 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
207 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
208 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
209 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
210 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
211 >;
212 };
213
214 pinctrl_usdhc3: usdhc3grp {
215 fsl,pins = <
216 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
217 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
218 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
219 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
220 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
221 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
222 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
223 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
224 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
225 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
226 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
227 >;
228 };
229
230 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
231 fsl,pins = <
232 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
233 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
234 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
235 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
236 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
237 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
238 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
239 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
240 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
241 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
242 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
243 >;
244 };
245
246 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
247 fsl,pins = <
248 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
249 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
250 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
251 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
252 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
253 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
254 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
255 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
256 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
257 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
258 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
259 >;
260 };
261
262 pinctrl_wdog: wdoggrp {
263 fsl,pins = <
264 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
265 >;
266 };
267 };
268 };
269
270 &fec1 {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_fec1>;
273 phy-mode = "rgmii-id";
274 phy-handle = <&ethphy0>;
275 phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
276 phy-reset-post-delay = <150>;
277 phy-reset-duration = <10>;
278 fsl,magic-packet;
279 status = "okay";
280
281 mdio {
282 #address-cells = <1>;
283 #size-cells = <0>;
284
285 ethphy0: ethernet-phy@0 {
286 compatible = "ethernet-phy-ieee802.3-c22";
287 reg = <1>;
288 eee-broken-1000t;
289 };
290 };
291 };
292
293
294 &flexspi {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_flexspi0>;
297 status = "okay";
298
299 flash0: mt25qu256aba@0 {
300 reg = <0>;
301 compatible = "jedec,spi-nor";
302 spi-max-frequency = <80000000>;
303 spi-tx-bus-width = <4>;
304 spi-rx-bus-width = <4>;
305 };
306 };
307
308 &i2c1 {
309 clock-frequency = <400000>;
310 pinctrl-names = "default", "gpio";
311 pinctrl-0 = <&pinctrl_i2c1>;
312 pinctrl-1 = <&pinctrl_i2c1_gpio>;
313 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
314 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
315 status = "okay";
316
317 pmic@4b {
318 compatible = "rohm,bd71847";
319 reg = <0x4b>;
320 pinctrl-0 = <&pinctrl_pmic>;
321 interrupt-parent = <&gpio1>;
322 interrupts = <3 GPIO_ACTIVE_LOW>;
323 rohm,reset-snvs-powered;
324
325 regulators {
326 buck1_reg: BUCK1 {
327 regulator-name = "BUCK1";
328 regulator-min-microvolt = <700000>;
329 regulator-max-microvolt = <1300000>;
330 regulator-boot-on;
331 regulator-always-on;
332 regulator-ramp-delay = <1250>;
333 };
334
335 buck2_reg: BUCK2 {
336 regulator-name = "BUCK2";
337 regulator-min-microvolt = <700000>;
338 regulator-max-microvolt = <1300000>;
339 regulator-boot-on;
340 regulator-always-on;
341 regulator-ramp-delay = <1250>;
342 };
343
344 buck3_reg: BUCK3 {
345 // BUCK5 in datasheet
346 regulator-name = "BUCK3";
347 regulator-min-microvolt = <700000>;
348 regulator-max-microvolt = <1350000>;
349 };
350
351 buck4_reg: BUCK4 {
352 // BUCK6 in datasheet
353 regulator-name = "BUCK4";
354 regulator-min-microvolt = <3000000>;
355 regulator-max-microvolt = <3300000>;
356 regulator-boot-on;
357 regulator-always-on;
358 };
359
360 buck5_reg: BUCK5 {
361 // BUCK7 in datasheet
362 regulator-name = "BUCK5";
363 regulator-min-microvolt = <1605000>;
364 regulator-max-microvolt = <1995000>;
365 regulator-boot-on;
366 regulator-always-on;
367 };
368
369 buck6_reg: BUCK6 {
370 // BUCK8 in datasheet
371 regulator-name = "BUCK6";
372 regulator-min-microvolt = <800000>;
373 regulator-max-microvolt = <1400000>;
374 regulator-boot-on;
375 regulator-always-on;
376 };
377
378 ldo1_reg: LDO1 {
379 regulator-name = "LDO1";
380 regulator-min-microvolt = <3000000>;
381 regulator-max-microvolt = <3300000>;
382 regulator-boot-on;
383 regulator-always-on;
384 };
385
386 ldo2_reg: LDO2 {
387 regulator-name = "LDO2";
388 regulator-min-microvolt = <900000>;
389 regulator-max-microvolt = <900000>;
390 regulator-boot-on;
391 regulator-always-on;
392 };
393
394 ldo3_reg: LDO3 {
395 regulator-name = "LDO3";
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <3300000>;
398 regulator-boot-on;
399 regulator-always-on;
400 };
401
402 ldo4_reg: LDO4 {
403 regulator-name = "LDO4";
404 regulator-min-microvolt = <900000>;
405 regulator-max-microvolt = <1800000>;
406 regulator-boot-on;
407 regulator-always-on;
408 };
409
410 ldo6_reg: LDO6 {
411 regulator-name = "LDO6";
412 regulator-min-microvolt = <900000>;
413 regulator-max-microvolt = <1800000>;
414 regulator-boot-on;
415 regulator-always-on;
416 };
417 };
418 };
419 };
420
421 &i2c2 {
422 clock-frequency = <400000>;
423 pinctrl-names = "default", "gpio";
424 pinctrl-0 = <&pinctrl_i2c2>;
425 pinctrl-1 = <&pinctrl_i2c2_gpio>;
426 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
427 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
428 status = "okay";
429 };
430
431 &i2c3 {
432 clock-frequency = <100000>;
433 pinctrl-names = "default", "gpio";
434 pinctrl-0 = <&pinctrl_i2c3>;
435 pinctrl-1 = <&pinctrl_i2c3_gpio>;
436 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
437 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
438 status = "okay";
439 };
440
441 &snvs_pwrkey {
442 status = "okay";
443 };
444
445 &uart2 { /* console */
446 pinctrl-names = "default";
447 pinctrl-0 = <&pinctrl_uart2>;
448 status = "okay";
449 };
450
451 &usdhc2 {
452 pinctrl-names = "default", "state_100mhz", "state_200mhz";
453 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
454 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
455 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
456 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
457 bus-width = <4>;
458 vmmc-supply = <&reg_usdhc2_vmmc>;
459 status = "okay";
460 };
461
462 &usdhc3 {
463 pinctrl-names = "default", "state_100mhz", "state_200mhz";
464 pinctrl-0 = <&pinctrl_usdhc3>;
465 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
466 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
467 bus-width = <8>;
468 non-removable;
469 status = "okay";
470 };
471
472 &wdog1 {
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_wdog>;
475 fsl,ext-reset-output;
476 status = "okay";
477 };
478
arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ 5187303
1 if ARCH_IMX8M 1 if ARCH_IMX8M
2 2
3 config IMX8M 3 config IMX8M
4 bool 4 bool
5 select HAS_CAAM 5 select HAS_CAAM
6 select ROM_UNIFIED_SECTIONS 6 select ROM_UNIFIED_SECTIONS
7 7
8 config IMX8MQ 8 config IMX8MQ
9 bool 9 bool
10 select IMX8M 10 select IMX8M
11 select ARMV8_SPL_EXCEPTION_VECTORS 11 select ARMV8_SPL_EXCEPTION_VECTORS
12 12
13 config IMX8MM 13 config IMX8MM
14 bool 14 bool
15 select IMX8M 15 select IMX8M
16 select ARMV8_SPL_EXCEPTION_VECTORS 16 select ARMV8_SPL_EXCEPTION_VECTORS
17 17
18 config IMX8MN 18 config IMX8MN
19 bool 19 bool
20 select IMX8M 20 select IMX8M
21 select ARMV8_SPL_EXCEPTION_VECTORS 21 select ARMV8_SPL_EXCEPTION_VECTORS
22 22
23 config IMX8MP 23 config IMX8MP
24 bool 24 bool
25 select IMX8M 25 select IMX8M
26 26
27 config SYS_SOC 27 config SYS_SOC
28 default "imx8m" 28 default "imx8m"
29 29
30 config SECURE_STICKY_BITS_LOCKUP 30 config SECURE_STICKY_BITS_LOCKUP
31 bool "Enable workaround to fix sticky bits lock up issue" 31 bool "Enable workaround to fix sticky bits lock up issue"
32 depends on IMX8MQ && IMX_HAB 32 depends on IMX8MQ && IMX_HAB
33 default y 33 default y
34 34
35 config IMX_UNIQUE_ID 35 config IMX_UNIQUE_ID
36 hex "Enable workaround to fix sticky bits lock up issue" 36 hex "Enable workaround to fix sticky bits lock up issue"
37 depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP 37 depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP
38 default 0x0 38 default 0x0
39 39
40 choice 40 choice
41 prompt "NXP i.MX8M board select" 41 prompt "NXP i.MX8M board select"
42 optional 42 optional
43 43
44 config TARGET_IMX8MQ_EVK 44 config TARGET_IMX8MQ_EVK
45 bool "imx8mq_evk" 45 bool "imx8mq_evk"
46 select IMX8MQ 46 select IMX8MQ
47 select IMX8M_LPDDR4 47 select IMX8M_LPDDR4
48 48
49 config TARGET_IMX8MQ_DDR3L_VAL 49 config TARGET_IMX8MQ_DDR3L_VAL
50 bool "imx8mq_ddr3l_val" 50 bool "imx8mq_ddr3l_val"
51 select IMX8MQ 51 select IMX8MQ
52 52
53 config TARGET_IMX8MQ_DDR4_VAL 53 config TARGET_IMX8MQ_DDR4_VAL
54 bool "imx8mq_ddr4_val" 54 bool "imx8mq_ddr4_val"
55 select IMX8MQ 55 select IMX8MQ
56 56
57 config TARGET_IMX8MM_DDR4_VAL 57 config TARGET_IMX8MM_DDR4_VAL
58 bool "imx8mm DDR4 validation board" 58 bool "imx8mm DDR4 validation board"
59 select IMX8MM 59 select IMX8MM
60 select SUPPORT_SPL 60 select SUPPORT_SPL
61 select IMX8M_DDR4 61 select IMX8M_DDR4
62 62
63 config TARGET_IMX8MM_DDR3L_VAL 63 config TARGET_IMX8MM_DDR3L_VAL
64 bool "imx8mm DDR3L validation board" 64 bool "imx8mm DDR3L validation board"
65 select IMX8MM 65 select IMX8MM
66 select SUPPORT_SPL 66 select SUPPORT_SPL
67 select IMX8M_DDR3L 67 select IMX8M_DDR3L
68 68
69 config TARGET_IMX8MM_EVK 69 config TARGET_IMX8MM_EVK
70 bool "imx8mm LPDDR4 EVK board" 70 bool "imx8mm LPDDR4 EVK board"
71 select IMX8MM 71 select IMX8MM
72 select SUPPORT_SPL 72 select SUPPORT_SPL
73 select IMX8M_LPDDR4 73 select IMX8M_LPDDR4
74 74
75 config TARGET_IMX8MM_DDR4_EVK 75 config TARGET_IMX8MM_DDR4_EVK
76 bool "imx8mm DDR4 EVK board" 76 bool "imx8mm DDR4 EVK board"
77 select IMX8MM 77 select IMX8MM
78 select SUPPORT_SPL 78 select SUPPORT_SPL
79 select IMX8M_DDR4 79 select IMX8M_DDR4
80 80
81 config TARGET_IMX8MN_EVK 81 config TARGET_IMX8MN_EVK
82 bool "imx8mn LPDDR4 EVK board" 82 bool "imx8mn LPDDR4 EVK board"
83 select IMX8MN 83 select IMX8MN
84 select SUPPORT_SPL 84 select SUPPORT_SPL
85 select IMX8M_LPDDR4 85 select IMX8M_LPDDR4
86 86
87 config TARGET_IMX8MN_DDR4_EVK 87 config TARGET_IMX8MN_DDR4_EVK
88 bool "imx8mn DDR4 EVK board" 88 bool "imx8mn DDR4 EVK board"
89 select IMX8MN 89 select IMX8MN
90 select SUPPORT_SPL 90 select SUPPORT_SPL
91 select IMX8M_DDR4 91 select IMX8M_DDR4
92 92
93 config TARGET_IMX8MP_EVK 93 config TARGET_IMX8MP_EVK
94 bool "imx8mp LPDDR4 EVK board" 94 bool "imx8mp LPDDR4 EVK board"
95 select IMX8MP 95 select IMX8MP
96 select SUPPORT_SPL 96 select SUPPORT_SPL
97 select IMX8M_LPDDR4 97 select IMX8M_LPDDR4
98 98
99 config TARGET_IMX8MM_AB2 99 config TARGET_IMX8MM_AB2
100 bool "imx8mm LPDDR4 Audio board 2.0" 100 bool "imx8mm LPDDR4 Audio board 2.0"
101 select IMX8MM 101 select IMX8MM
102 select SUPPORT_SPL 102 select SUPPORT_SPL
103 select IMX8M_LPDDR4 103 select IMX8M_LPDDR4
104 104
105 config TARGET_IMX8MN_AB2
106 bool "imx8mn LPDDR4 Audio board 2.0"
107 select IMX8MN
108 select SUPPORT_SPL
109 select IMX8M_LPDDR4
110
111 config TARGET_IMX8MN_DDR4_AB2
112 bool "imx8mn DDR4 Audio board 2.0"
113 select IMX8MN
114 select SUPPORT_SPL
115 select IMX8M_DDR4
116
105 config TARGET_VERDIN_IMX8MM 117 config TARGET_VERDIN_IMX8MM
106 bool "Support Toradex Verdin iMX8M Mini module" 118 bool "Support Toradex Verdin iMX8M Mini module"
107 select IMX8MM 119 select IMX8MM
108 select SUPPORT_SPL 120 select SUPPORT_SPL
109 select IMX8M_LPDDR4 121 select IMX8M_LPDDR4
110 122
111 endchoice 123 endchoice
112 124
113 source "board/freescale/imx8mq_evk/Kconfig" 125 source "board/freescale/imx8mq_evk/Kconfig"
114 source "board/freescale/imx8mq_val/Kconfig" 126 source "board/freescale/imx8mq_val/Kconfig"
115 source "board/freescale/imx8mm_ab2/Kconfig" 127 source "board/freescale/imx8mm_ab2/Kconfig"
116 source "board/freescale/imx8mm_evk/Kconfig" 128 source "board/freescale/imx8mm_evk/Kconfig"
117 source "board/freescale/imx8mm_val/Kconfig" 129 source "board/freescale/imx8mm_val/Kconfig"
118 source "board/freescale/imx8mn_evk/Kconfig" 130 source "board/freescale/imx8mn_evk/Kconfig"
119 source "board/freescale/imx8mp_evk/Kconfig" 131 source "board/freescale/imx8mp_evk/Kconfig"
120 source "board/toradex/verdin-imx8mm/Kconfig" 132 source "board/toradex/verdin-imx8mm/Kconfig"
121 133
122 endif 134 endif
123 135
board/freescale/imx8mm_ab2/Kconfig
Diff comments   View file @ 5187303
1 if TARGET_IMX8MM_AB2 1 if TARGET_IMX8MM_AB2 || TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2
2 2
3 config SYS_BOARD 3 config SYS_BOARD
4 default "imx8mm_ab2" 4 default "imx8mm_ab2"
5 5
6 config SYS_VENDOR 6 config SYS_VENDOR
7 default "freescale" 7 default "freescale"
8 8
9 if TARGET_IMX8MM_AB2 9 if TARGET_IMX8MM_AB2
10 config SYS_CONFIG_NAME 10 config SYS_CONFIG_NAME
11 default "imx8mm_ab2" 11 default "imx8mm_ab2"
12 endif
13
14 if TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2
15 config SYS_CONFIG_NAME
16 default "imx8mn_ab2"
12 endif 17 endif
13 18
14 source "board/freescale/common/Kconfig" 19 source "board/freescale/common/Kconfig"
15 20
16 endif 21 endif
17 22
board/freescale/imx8mm_ab2/Makefile
Diff comments   View file @ 5187303
1 # 1 #
2 # Copyright 2020 NXP 2 # Copyright 2020 NXP
3 # 3 #
4 # SPDX-License-Identifier: GPL-2.0+ 4 # SPDX-License-Identifier: GPL-2.0+
5 # 5 #
6 6
7 obj-y += imx8mm_ab2.o 7 obj-y += imx8mm_ab2.o
8 8
9 ifdef CONFIG_SPL_BUILD 9 ifdef CONFIG_SPL_BUILD
10 obj-y += spl.o 10 obj-y += spl.o
11 obj-$(CONFIG_TARGET_IMX8MM_AB2) += lpddr4_imx8mm_som.o 11 obj-$(CONFIG_TARGET_IMX8MM_AB2) += lpddr4_imx8mm_som.o
12 obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som.o
13 obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som.o
12 endif 14 endif
13 15
board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c
Diff comments   View file @ 5187303
File was created 1 /*
2 * Copyright 2019 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Generated code from MX8M_DDR_tool
7 * Align with uboot version:
8 * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
9 */
10
11 #include <linux/kernel.h>
12 #include <asm/arch/ddr.h>
13
14 struct dram_cfg_param ddr_ddrc_cfg[] = {
15 /** Initialize DDRC registers **/
16 { 0x3d400000, 0x81040010 },
17 { 0x3d400030, 0x20 },
18 { 0x3d400034, 0x221306 },
19 { 0x3d400050, 0x210070 },
20 { 0x3d400054, 0x10008 },
21 { 0x3d400060, 0x0 },
22 { 0x3d400064, 0x92014a },
23 { 0x3d4000c0, 0x0 },
24 { 0x3d4000c4, 0x1000 },
25 { 0x3d4000d0, 0xc0030126 },
26 { 0x3d4000d4, 0x770000 },
27 { 0x3d4000dc, 0x8340105 },
28 { 0x3d4000e0, 0x180200 },
29 { 0x3d4000e4, 0x110000 },
30 { 0x3d4000e8, 0x2000600 },
31 { 0x3d4000ec, 0x810 },
32 { 0x3d4000f0, 0x20 },
33 { 0x3d4000f4, 0xec7 },
34 { 0x3d400100, 0x11122914 },
35 { 0x3d400104, 0x4051c },
36 { 0x3d400108, 0x608050d },
37 { 0x3d40010c, 0x400c },
38 { 0x3d400110, 0x8030409 },
39 { 0x3d400114, 0x6060403 },
40 { 0x3d40011c, 0x606 },
41 { 0x3d400120, 0x7070d0c },
42 { 0x3d400124, 0x2040a },
43 { 0x3d40012c, 0x1809010e },
44 { 0x3d400130, 0x8 },
45 { 0x3d40013c, 0x0 },
46 { 0x3d400180, 0x1000040 },
47 { 0x3d400184, 0x493e },
48 { 0x3d400190, 0x38b8207 },
49 { 0x3d400194, 0x2020303 },
50 { 0x3d400198, 0x7f04011 },
51 { 0x3d40019c, 0xb0 },
52 { 0x3d4001a0, 0xe0400018 },
53 { 0x3d4001a4, 0x48005a },
54 { 0x3d4001a8, 0x80000000 },
55 { 0x3d4001b0, 0x1 },
56 { 0x3d4001b4, 0xb07 },
57 { 0x3d4001b8, 0x4 },
58 { 0x3d4001c0, 0x1 },
59 { 0x3d4001c4, 0x0 },
60 { 0x3d400200, 0x3f1f },
61 { 0x3d400204, 0x3f0909 },
62 { 0x3d400208, 0x700 },
63 { 0x3d40020c, 0x0 },
64 { 0x3d400210, 0x1f1f },
65 { 0x3d400214, 0x7070707 },
66 { 0x3d400218, 0x7070707 },
67 { 0x3d40021c, 0xf07 },
68 { 0x3d400220, 0x3f01 },
69 { 0x3d400240, 0x6000610 },
70 { 0x3d400244, 0x1323 },
71 { 0x3d400400, 0x100 },
72
73 /* performance setting */
74 { 0x3d400250, 0x00001f05 },
75 { 0x3d400254, 0x1f },
76 { 0x3d400264, 0x900003ff },
77 { 0x3d40026c, 0x200003ff },
78 { 0x3d400494, 0x01000e00 },
79 { 0x3d400498, 0x03ff0000 },
80 { 0x3d40049c, 0x01000e00 },
81 { 0x3d4004a0, 0x03ff0000 },
82
83 { 0x3d402050, 0x210070 },
84 { 0x3d402064, 0x400093 },
85 { 0x3d4020dc, 0x105 },
86 { 0x3d4020e0, 0x0 },
87 { 0x3d4020e8, 0x2000600 },
88 { 0x3d4020ec, 0x10 },
89 { 0x3d402100, 0xb081209 },
90 { 0x3d402104, 0x2020d },
91 { 0x3d402108, 0x5050309 },
92 { 0x3d40210c, 0x400c },
93 { 0x3d402110, 0x5030206 },
94 { 0x3d402114, 0x3030202 },
95 { 0x3d40211c, 0x303 },
96 { 0x3d402120, 0x4040d06 },
97 { 0x3d402124, 0x20208 },
98 { 0x3d40212c, 0x1205010e },
99 { 0x3d402130, 0x8 },
100 { 0x3d40213c, 0x0 },
101 { 0x3d402180, 0x1000040 },
102 { 0x3d402190, 0x3848204 },
103 { 0x3d402194, 0x2020303 },
104 { 0x3d4021b4, 0x404 },
105 { 0x3d4021b8, 0x4 },
106 { 0x3d402240, 0x6000600 },
107 { 0x3d4020f4, 0xec7 },
108 };
109
110 /* PHY Initialize Configuration */
111 struct dram_cfg_param ddr_ddrphy_cfg[] = {
112 { 0x1005f, 0x2fd },
113 { 0x1015f, 0x2fd },
114 { 0x1105f, 0x2fd },
115 { 0x1115f, 0x2fd },
116 { 0x11005f, 0x2fd },
117 { 0x11015f, 0x2fd },
118 { 0x11105f, 0x2fd },
119 { 0x11115f, 0x2fd },
120 { 0x55, 0x355 },
121 { 0x1055, 0x355 },
122 { 0x2055, 0x355 },
123 { 0x3055, 0x355 },
124 { 0x4055, 0x55 },
125 { 0x5055, 0x55 },
126 { 0x6055, 0x355 },
127 { 0x7055, 0x355 },
128 { 0x8055, 0x355 },
129 { 0x9055, 0x355 },
130 { 0x200c5, 0xa },
131 { 0x1200c5, 0x6 },
132 { 0x2002e, 0x2 },
133 { 0x12002e, 0x1 },
134 { 0x20024, 0x8 },
135 { 0x2003a, 0x2 },
136 { 0x120024, 0x8 },
137 { 0x2003a, 0x2 },
138 { 0x20056, 0x6 },
139 { 0x120056, 0xa },
140 { 0x1004d, 0x1a },
141 { 0x1014d, 0x1a },
142 { 0x1104d, 0x1a },
143 { 0x1114d, 0x1a },
144 { 0x11004d, 0x1a },
145 { 0x11014d, 0x1a },
146 { 0x11104d, 0x1a },
147 { 0x11114d, 0x1a },
148 { 0x10049, 0xe38 },
149 { 0x10149, 0xe38 },
150 { 0x11049, 0xe38 },
151 { 0x11149, 0xe38 },
152 { 0x110049, 0xe38 },
153 { 0x110149, 0xe38 },
154 { 0x111049, 0xe38 },
155 { 0x111149, 0xe38 },
156 { 0x43, 0x63 },
157 { 0x1043, 0x63 },
158 { 0x2043, 0x63 },
159 { 0x3043, 0x63 },
160 { 0x4043, 0x63 },
161 { 0x5043, 0x63 },
162 { 0x6043, 0x63 },
163 { 0x7043, 0x63 },
164 { 0x8043, 0x63 },
165 { 0x9043, 0x63 },
166 { 0x20018, 0x1 },
167 { 0x20075, 0x2 },
168 { 0x20050, 0x0 },
169 { 0x20008, 0x258 },
170 { 0x120008, 0x10a },
171 { 0x20088, 0x9 },
172 { 0x200b2, 0x268 },
173 { 0x10043, 0x5b1 },
174 { 0x10143, 0x5b1 },
175 { 0x11043, 0x5b1 },
176 { 0x11143, 0x5b1 },
177 { 0x1200b2, 0x268 },
178 { 0x110043, 0x5b1 },
179 { 0x110143, 0x5b1 },
180 { 0x111043, 0x5b1 },
181 { 0x111143, 0x5b1 },
182 { 0x200fa, 0x1 },
183 { 0x1200fa, 0x1 },
184 { 0x20019, 0x5 },
185 { 0x120019, 0x5 },
186 { 0x200f0, 0x5555 },
187 { 0x200f1, 0x5555 },
188 { 0x200f2, 0x5555 },
189 { 0x200f3, 0x5555 },
190 { 0x200f4, 0x5555 },
191 { 0x200f5, 0x5555 },
192 { 0x200f6, 0x5555 },
193 { 0x200f7, 0xf000 },
194 { 0x20025, 0x0 },
195 { 0x2002d, 0x0 },
196 { 0x12002d, 0x0 },
197 { 0x2005b, 0x7529 },
198 { 0x2005c, 0x0 },
199 { 0x200c7, 0x21 },
200 { 0x200ca, 0x24 },
201 { 0x200cc, 0x1f7 },
202 { 0x1200c7, 0x21 },
203 { 0x1200ca, 0x24 },
204 { 0x1200cc, 0x1f7 },
205 { 0x2007d, 0x212 },
206 { 0x12007d, 0x212 },
207 { 0x2007c, 0x61 },
208 { 0x12007c, 0x61 },
209 { 0x1004a, 0x500 },
210 { 0x1104a, 0x500 },
211 { 0x2002c, 0x0 },
212 };
213
214 /* ddr phy trained csr */
215 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
216 {0x0200b2, 0x0},
217 {0x1200b2, 0x0},
218 {0x2200b2, 0x0},
219 {0x0200cb, 0x0},
220 {0x010043, 0x0},
221 {0x110043, 0x0},
222 {0x210043, 0x0},
223 {0x010143, 0x0},
224 {0x110143, 0x0},
225 {0x210143, 0x0},
226 {0x011043, 0x0},
227 {0x111043, 0x0},
228 {0x211043, 0x0},
229 {0x011143, 0x0},
230 {0x111143, 0x0},
231 {0x211143, 0x0},
232 {0x000080, 0x0},
233 {0x100080, 0x0},
234 {0x200080, 0x0},
235 {0x001080, 0x0},
236 {0x101080, 0x0},
237 {0x201080, 0x0},
238 {0x002080, 0x0},
239 {0x102080, 0x0},
240 {0x202080, 0x0},
241 {0x003080, 0x0},
242 {0x103080, 0x0},
243 {0x203080, 0x0},
244 {0x004080, 0x0},
245 {0x104080, 0x0},
246 {0x204080, 0x0},
247 {0x005080, 0x0},
248 {0x105080, 0x0},
249 {0x205080, 0x0},
250 {0x006080, 0x0},
251 {0x106080, 0x0},
252 {0x206080, 0x0},
253 {0x007080, 0x0},
254 {0x107080, 0x0},
255 {0x207080, 0x0},
256 {0x008080, 0x0},
257 {0x108080, 0x0},
258 {0x208080, 0x0},
259 {0x009080, 0x0},
260 {0x109080, 0x0},
261 {0x209080, 0x0},
262 {0x010080, 0x0},
263 {0x110080, 0x0},
264 {0x210080, 0x0},
265 {0x010180, 0x0},
266 {0x110180, 0x0},
267 {0x210180, 0x0},
268 {0x010081, 0x0},
269 {0x110081, 0x0},
270 {0x210081, 0x0},
271 {0x010181, 0x0},
272 {0x110181, 0x0},
273 {0x210181, 0x0},
274 {0x010082, 0x0},
275 {0x110082, 0x0},
276 {0x210082, 0x0},
277 {0x010182, 0x0},
278 {0x110182, 0x0},
279 {0x210182, 0x0},
280 {0x010083, 0x0},
281 {0x110083, 0x0},
282 {0x210083, 0x0},
283 {0x010183, 0x0},
284 {0x110183, 0x0},
285 {0x210183, 0x0},
286 {0x011080, 0x0},
287 {0x111080, 0x0},
288 {0x211080, 0x0},
289 {0x011180, 0x0},
290 {0x111180, 0x0},
291 {0x211180, 0x0},
292 {0x011081, 0x0},
293 {0x111081, 0x0},
294 {0x211081, 0x0},
295 {0x011181, 0x0},
296 {0x111181, 0x0},
297 {0x211181, 0x0},
298 {0x011082, 0x0},
299 {0x111082, 0x0},
300 {0x211082, 0x0},
301 {0x011182, 0x0},
302 {0x111182, 0x0},
303 {0x211182, 0x0},
304 {0x011083, 0x0},
305 {0x111083, 0x0},
306 {0x211083, 0x0},
307 {0x011183, 0x0},
308 {0x111183, 0x0},
309 {0x211183, 0x0},
310 {0x0100d0, 0x0},
311 {0x1100d0, 0x0},
312 {0x2100d0, 0x0},
313 {0x0101d0, 0x0},
314 {0x1101d0, 0x0},
315 {0x2101d0, 0x0},
316 {0x0100d1, 0x0},
317 {0x1100d1, 0x0},
318 {0x2100d1, 0x0},
319 {0x0101d1, 0x0},
320 {0x1101d1, 0x0},
321 {0x2101d1, 0x0},
322 {0x0100d2, 0x0},
323 {0x1100d2, 0x0},
324 {0x2100d2, 0x0},
325 {0x0101d2, 0x0},
326 {0x1101d2, 0x0},
327 {0x2101d2, 0x0},
328 {0x0100d3, 0x0},
329 {0x1100d3, 0x0},
330 {0x2100d3, 0x0},
331 {0x0101d3, 0x0},
332 {0x1101d3, 0x0},
333 {0x2101d3, 0x0},
334 {0x0110d0, 0x0},
335 {0x1110d0, 0x0},
336 {0x2110d0, 0x0},
337 {0x0111d0, 0x0},
338 {0x1111d0, 0x0},
339 {0x2111d0, 0x0},
340 {0x0110d1, 0x0},
341 {0x1110d1, 0x0},
342 {0x2110d1, 0x0},
343 {0x0111d1, 0x0},
344 {0x1111d1, 0x0},
345 {0x2111d1, 0x0},
346 {0x0110d2, 0x0},
347 {0x1110d2, 0x0},
348 {0x2110d2, 0x0},
349 {0x0111d2, 0x0},
350 {0x1111d2, 0x0},
351 {0x2111d2, 0x0},
352 {0x0110d3, 0x0},
353 {0x1110d3, 0x0},
354 {0x2110d3, 0x0},
355 {0x0111d3, 0x0},
356 {0x1111d3, 0x0},
357 {0x2111d3, 0x0},
358 {0x010068, 0x0},
359 {0x010168, 0x0},
360 {0x010268, 0x0},
361 {0x010368, 0x0},
362 {0x010468, 0x0},
363 {0x010568, 0x0},
364 {0x010668, 0x0},
365 {0x010768, 0x0},
366 {0x010868, 0x0},
367 {0x010069, 0x0},
368 {0x010169, 0x0},
369 {0x010269, 0x0},
370 {0x010369, 0x0},
371 {0x010469, 0x0},
372 {0x010569, 0x0},
373 {0x010669, 0x0},
374 {0x010769, 0x0},
375 {0x010869, 0x0},
376 {0x01006a, 0x0},
377 {0x01016a, 0x0},
378 {0x01026a, 0x0},
379 {0x01036a, 0x0},
380 {0x01046a, 0x0},
381 {0x01056a, 0x0},
382 {0x01066a, 0x0},
383 {0x01076a, 0x0},
384 {0x01086a, 0x0},
385 {0x01006b, 0x0},
386 {0x01016b, 0x0},
387 {0x01026b, 0x0},
388 {0x01036b, 0x0},
389 {0x01046b, 0x0},
390 {0x01056b, 0x0},
391 {0x01066b, 0x0},
392 {0x01076b, 0x0},
393 {0x01086b, 0x0},
394 {0x011068, 0x0},
395 {0x011168, 0x0},
396 {0x011268, 0x0},
397 {0x011368, 0x0},
398 {0x011468, 0x0},
399 {0x011568, 0x0},
400 {0x011668, 0x0},
401 {0x011768, 0x0},
402 {0x011868, 0x0},
403 {0x011069, 0x0},
404 {0x011169, 0x0},
405 {0x011269, 0x0},
406 {0x011369, 0x0},
407 {0x011469, 0x0},
408 {0x011569, 0x0},
409 {0x011669, 0x0},
410 {0x011769, 0x0},
411 {0x011869, 0x0},
412 {0x01106a, 0x0},
413 {0x01116a, 0x0},
414 {0x01126a, 0x0},
415 {0x01136a, 0x0},
416 {0x01146a, 0x0},
417 {0x01156a, 0x0},
418 {0x01166a, 0x0},
419 {0x01176a, 0x0},
420 {0x01186a, 0x0},
421 {0x01106b, 0x0},
422 {0x01116b, 0x0},
423 {0x01126b, 0x0},
424 {0x01136b, 0x0},
425 {0x01146b, 0x0},
426 {0x01156b, 0x0},
427 {0x01166b, 0x0},
428 {0x01176b, 0x0},
429 {0x01186b, 0x0},
430 {0x01008c, 0x0},
431 {0x11008c, 0x0},
432 {0x21008c, 0x0},
433 {0x01018c, 0x0},
434 {0x11018c, 0x0},
435 {0x21018c, 0x0},
436 {0x01008d, 0x0},
437 {0x11008d, 0x0},
438 {0x21008d, 0x0},
439 {0x01018d, 0x0},
440 {0x11018d, 0x0},
441 {0x21018d, 0x0},
442 {0x01008e, 0x0},
443 {0x11008e, 0x0},
444 {0x21008e, 0x0},
445 {0x01018e, 0x0},
446 {0x11018e, 0x0},
447 {0x21018e, 0x0},
448 {0x01008f, 0x0},
449 {0x11008f, 0x0},
450 {0x21008f, 0x0},
451 {0x01018f, 0x0},
452 {0x11018f, 0x0},
453 {0x21018f, 0x0},
454 {0x01108c, 0x0},
455 {0x11108c, 0x0},
456 {0x21108c, 0x0},
457 {0x01118c, 0x0},
458 {0x11118c, 0x0},
459 {0x21118c, 0x0},
460 {0x01108d, 0x0},
461 {0x11108d, 0x0},
462 {0x21108d, 0x0},
463 {0x01118d, 0x0},
464 {0x11118d, 0x0},
465 {0x21118d, 0x0},
466 {0x01108e, 0x0},
467 {0x11108e, 0x0},
468 {0x21108e, 0x0},
469 {0x01118e, 0x0},
470 {0x11118e, 0x0},
471 {0x21118e, 0x0},
472 {0x01108f, 0x0},
473 {0x11108f, 0x0},
474 {0x21108f, 0x0},
475 {0x01118f, 0x0},
476 {0x11118f, 0x0},
477 {0x21118f, 0x0},
478 {0x0100c0, 0x0},
479 {0x1100c0, 0x0},
480 {0x2100c0, 0x0},
481 {0x0101c0, 0x0},
482 {0x1101c0, 0x0},
483 {0x2101c0, 0x0},
484 {0x0102c0, 0x0},
485 {0x1102c0, 0x0},
486 {0x2102c0, 0x0},
487 {0x0103c0, 0x0},
488 {0x1103c0, 0x0},
489 {0x2103c0, 0x0},
490 {0x0104c0, 0x0},
491 {0x1104c0, 0x0},
492 {0x2104c0, 0x0},
493 {0x0105c0, 0x0},
494 {0x1105c0, 0x0},
495 {0x2105c0, 0x0},
496 {0x0106c0, 0x0},
497 {0x1106c0, 0x0},
498 {0x2106c0, 0x0},
499 {0x0107c0, 0x0},
500 {0x1107c0, 0x0},
501 {0x2107c0, 0x0},
502 {0x0108c0, 0x0},
503 {0x1108c0, 0x0},
504 {0x2108c0, 0x0},
505 {0x0100c1, 0x0},
506 {0x1100c1, 0x0},
507 {0x2100c1, 0x0},
508 {0x0101c1, 0x0},
509 {0x1101c1, 0x0},
510 {0x2101c1, 0x0},
511 {0x0102c1, 0x0},
512 {0x1102c1, 0x0},
513 {0x2102c1, 0x0},
514 {0x0103c1, 0x0},
515 {0x1103c1, 0x0},
516 {0x2103c1, 0x0},
517 {0x0104c1, 0x0},
518 {0x1104c1, 0x0},
519 {0x2104c1, 0x0},
520 {0x0105c1, 0x0},
521 {0x1105c1, 0x0},
522 {0x2105c1, 0x0},
523 {0x0106c1, 0x0},
524 {0x1106c1, 0x0},
525 {0x2106c1, 0x0},
526 {0x0107c1, 0x0},
527 {0x1107c1, 0x0},
528 {0x2107c1, 0x0},
529 {0x0108c1, 0x0},
530 {0x1108c1, 0x0},
531 {0x2108c1, 0x0},
532 {0x0100c2, 0x0},
533 {0x1100c2, 0x0},
534 {0x2100c2, 0x0},
535 {0x0101c2, 0x0},
536 {0x1101c2, 0x0},
537 {0x2101c2, 0x0},
538 {0x0102c2, 0x0},
539 {0x1102c2, 0x0},
540 {0x2102c2, 0x0},
541 {0x0103c2, 0x0},
542 {0x1103c2, 0x0},
543 {0x2103c2, 0x0},
544 {0x0104c2, 0x0},
545 {0x1104c2, 0x0},
546 {0x2104c2, 0x0},
547 {0x0105c2, 0x0},
548 {0x1105c2, 0x0},
549 {0x2105c2, 0x0},
550 {0x0106c2, 0x0},
551 {0x1106c2, 0x0},
552 {0x2106c2, 0x0},
553 {0x0107c2, 0x0},
554 {0x1107c2, 0x0},
555 {0x2107c2, 0x0},
556 {0x0108c2, 0x0},
557 {0x1108c2, 0x0},
558 {0x2108c2, 0x0},
559 {0x0100c3, 0x0},
560 {0x1100c3, 0x0},
561 {0x2100c3, 0x0},
562 {0x0101c3, 0x0},
563 {0x1101c3, 0x0},
564 {0x2101c3, 0x0},
565 {0x0102c3, 0x0},
566 {0x1102c3, 0x0},
567 {0x2102c3, 0x0},
568 {0x0103c3, 0x0},
569 {0x1103c3, 0x0},
570 {0x2103c3, 0x0},
571 {0x0104c3, 0x0},
572 {0x1104c3, 0x0},
573 {0x2104c3, 0x0},
574 {0x0105c3, 0x0},
575 {0x1105c3, 0x0},
576 {0x2105c3, 0x0},
577 {0x0106c3, 0x0},
578 {0x1106c3, 0x0},
579 {0x2106c3, 0x0},
580 {0x0107c3, 0x0},
581 {0x1107c3, 0x0},
582 {0x2107c3, 0x0},
583 {0x0108c3, 0x0},
584 {0x1108c3, 0x0},
585 {0x2108c3, 0x0},
586 {0x0110c0, 0x0},
587 {0x1110c0, 0x0},
588 {0x2110c0, 0x0},
589 {0x0111c0, 0x0},
590 {0x1111c0, 0x0},
591 {0x2111c0, 0x0},
592 {0x0112c0, 0x0},
593 {0x1112c0, 0x0},
594 {0x2112c0, 0x0},
595 {0x0113c0, 0x0},
596 {0x1113c0, 0x0},
597 {0x2113c0, 0x0},
598 {0x0114c0, 0x0},
599 {0x1114c0, 0x0},
600 {0x2114c0, 0x0},
601 {0x0115c0, 0x0},
602 {0x1115c0, 0x0},
603 {0x2115c0, 0x0},
604 {0x0116c0, 0x0},
605 {0x1116c0, 0x0},
606 {0x2116c0, 0x0},
607 {0x0117c0, 0x0},
608 {0x1117c0, 0x0},
609 {0x2117c0, 0x0},
610 {0x0118c0, 0x0},
611 {0x1118c0, 0x0},
612 {0x2118c0, 0x0},
613 {0x0110c1, 0x0},
614 {0x1110c1, 0x0},
615 {0x2110c1, 0x0},
616 {0x0111c1, 0x0},
617 {0x1111c1, 0x0},
618 {0x2111c1, 0x0},
619 {0x0112c1, 0x0},
620 {0x1112c1, 0x0},
621 {0x2112c1, 0x0},
622 {0x0113c1, 0x0},
623 {0x1113c1, 0x0},
624 {0x2113c1, 0x0},
625 {0x0114c1, 0x0},
626 {0x1114c1, 0x0},
627 {0x2114c1, 0x0},
628 {0x0115c1, 0x0},
629 {0x1115c1, 0x0},
630 {0x2115c1, 0x0},
631 {0x0116c1, 0x0},
632 {0x1116c1, 0x0},
633 {0x2116c1, 0x0},
634 {0x0117c1, 0x0},
635 {0x1117c1, 0x0},
636 {0x2117c1, 0x0},
637 {0x0118c1, 0x0},
638 {0x1118c1, 0x0},
639 {0x2118c1, 0x0},
640 {0x0110c2, 0x0},
641 {0x1110c2, 0x0},
642 {0x2110c2, 0x0},
643 {0x0111c2, 0x0},
644 {0x1111c2, 0x0},
645 {0x2111c2, 0x0},
646 {0x0112c2, 0x0},
647 {0x1112c2, 0x0},
648 {0x2112c2, 0x0},
649 {0x0113c2, 0x0},
650 {0x1113c2, 0x0},
651 {0x2113c2, 0x0},
652 {0x0114c2, 0x0},
653 {0x1114c2, 0x0},
654 {0x2114c2, 0x0},
655 {0x0115c2, 0x0},
656 {0x1115c2, 0x0},
657 {0x2115c2, 0x0},
658 {0x0116c2, 0x0},
659 {0x1116c2, 0x0},
660 {0x2116c2, 0x0},
661 {0x0117c2, 0x0},
662 {0x1117c2, 0x0},
663 {0x2117c2, 0x0},
664 {0x0118c2, 0x0},
665 {0x1118c2, 0x0},
666 {0x2118c2, 0x0},
667 {0x0110c3, 0x0},
668 {0x1110c3, 0x0},
669 {0x2110c3, 0x0},
670 {0x0111c3, 0x0},
671 {0x1111c3, 0x0},
672 {0x2111c3, 0x0},
673 {0x0112c3, 0x0},
674 {0x1112c3, 0x0},
675 {0x2112c3, 0x0},
676 {0x0113c3, 0x0},
677 {0x1113c3, 0x0},
678 {0x2113c3, 0x0},
679 {0x0114c3, 0x0},
680 {0x1114c3, 0x0},
681 {0x2114c3, 0x0},
682 {0x0115c3, 0x0},
683 {0x1115c3, 0x0},
684 {0x2115c3, 0x0},
685 {0x0116c3, 0x0},
686 {0x1116c3, 0x0},
687 {0x2116c3, 0x0},
688 {0x0117c3, 0x0},
689 {0x1117c3, 0x0},
690 {0x2117c3, 0x0},
691 {0x0118c3, 0x0},
692 {0x1118c3, 0x0},
693 {0x2118c3, 0x0},
694 {0x010020, 0x0},
695 {0x110020, 0x0},
696 {0x210020, 0x0},
697 {0x011020, 0x0},
698 {0x111020, 0x0},
699 {0x211020, 0x0},
700 {0x02007d, 0x0},
701 {0x12007d, 0x0},
702 {0x22007d, 0x0},
703 {0x010040, 0x0},
704 {0x010140, 0x0},
705 {0x010240, 0x0},
706 {0x010340, 0x0},
707 {0x010440, 0x0},
708 {0x010540, 0x0},
709 {0x010640, 0x0},
710 {0x010740, 0x0},
711 {0x010840, 0x0},
712 {0x010030, 0x0},
713 {0x010130, 0x0},
714 {0x010230, 0x0},
715 {0x010330, 0x0},
716 {0x010430, 0x0},
717 {0x010530, 0x0},
718 {0x010630, 0x0},
719 {0x010730, 0x0},
720 {0x010830, 0x0},
721 {0x011040, 0x0},
722 {0x011140, 0x0},
723 {0x011240, 0x0},
724 {0x011340, 0x0},
725 {0x011440, 0x0},
726 {0x011540, 0x0},
727 {0x011640, 0x0},
728 {0x011740, 0x0},
729 {0x011840, 0x0},
730 {0x011030, 0x0},
731 {0x011130, 0x0},
732 {0x011230, 0x0},
733 {0x011330, 0x0},
734 {0x011430, 0x0},
735 {0x011530, 0x0},
736 {0x011630, 0x0},
737 {0x011730, 0x0},
738 {0x011830, 0x0},
739 };
740
741 /* P0 message block paremeter for training firmware */
742 struct dram_cfg_param ddr_fsp0_cfg[] = {
743 { 0xd0000, 0x0 },
744 { 0x54003, 0x960 },
745 { 0x54004, 0x2 },
746 { 0x54005, 0x2830 },
747 { 0x54006, 0x25e },
748 { 0x54007, 0x1000 },
749 { 0x54008, 0x101 },
750 { 0x5400b, 0x31f },
751 { 0x5400c, 0xc8 },
752 { 0x5400d, 0x100 },
753 { 0x54012, 0x1 },
754 { 0x5402f, 0x834 },
755 { 0x54030, 0x105 },
756 { 0x54031, 0x18 },
757 { 0x54032, 0x200 },
758 { 0x54033, 0x200 },
759 { 0x54034, 0x600 },
760 { 0x54035, 0x810 },
761 { 0x54036, 0x101 },
762 { 0x5403f, 0x1221 },
763 { 0x541fc, 0x100 },
764 { 0xd0000, 0x1 },
765 };
766
767
768 /* P1 message block paremeter for training firmware */
769 struct dram_cfg_param ddr_fsp1_cfg[] = {
770 { 0xd0000, 0x0 },
771 { 0x54002, 0x1 },
772 { 0x54003, 0x42a },
773 { 0x54004, 0x2 },
774 { 0x54005, 0x2830 },
775 { 0x54006, 0x25e },
776 { 0x54007, 0x1000 },
777 { 0x54008, 0x101 },
778 { 0x5400b, 0x21f },
779 { 0x5400c, 0xc8 },
780 { 0x5400d, 0x100 },
781 { 0x54012, 0x1 },
782 { 0x54030, 0x105 },
783 { 0x54033, 0x200 },
784 { 0x54034, 0x600 },
785 { 0x54035, 0x10 },
786 { 0x54036, 0x101 },
787 { 0x5403f, 0x1221 },
788 { 0x541fc, 0x100 },
789 { 0xd0000, 0x1 },
790 };
791
792
793 /* P0 2D message block paremeter for training firmware */
794 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
795 { 0xd0000, 0x0 },
796 { 0x54003, 0x960 },
797 { 0x54004, 0x2 },
798 { 0x54005, 0x2830 },
799 { 0x54006, 0x25e },
800 { 0x54007, 0x1000 },
801 { 0x54008, 0x101 },
802 { 0x5400b, 0x61 },
803 { 0x5400c, 0xc8 },
804 { 0x5400d, 0x100 },
805 { 0x5400e, 0x1f7f },
806 { 0x54012, 0x1 },
807 { 0x5402f, 0x834 },
808 { 0x54030, 0x105 },
809 { 0x54031, 0x18 },
810 { 0x54032, 0x200 },
811 { 0x54033, 0x200 },
812 { 0x54034, 0x600 },
813 { 0x54035, 0x810 },
814 { 0x54036, 0x101 },
815 { 0x5403f, 0x1221 },
816 { 0x541fc, 0x100 },
817 { 0xd0000, 0x1 },
818 };
819
820 /* DRAM PHY init engine image */
821 struct dram_cfg_param ddr_phy_pie[] = {
822 { 0xd0000, 0x0 },
823 { 0x90000, 0x10 },
824 { 0x90001, 0x400 },
825 { 0x90002, 0x10e },
826 { 0x90003, 0x0 },
827 { 0x90004, 0x0 },
828 { 0x90005, 0x8 },
829 { 0x90029, 0xb },
830 { 0x9002a, 0x480 },
831 { 0x9002b, 0x109 },
832 { 0x9002c, 0x8 },
833 { 0x9002d, 0x448 },
834 { 0x9002e, 0x139 },
835 { 0x9002f, 0x8 },
836 { 0x90030, 0x478 },
837 { 0x90031, 0x109 },
838 { 0x90032, 0x2 },
839 { 0x90033, 0x10 },
840 { 0x90034, 0x139 },
841 { 0x90035, 0xb },
842 { 0x90036, 0x7c0 },
843 { 0x90037, 0x139 },
844 { 0x90038, 0x44 },
845 { 0x90039, 0x633 },
846 { 0x9003a, 0x159 },
847 { 0x9003b, 0x14f },
848 { 0x9003c, 0x630 },
849 { 0x9003d, 0x159 },
850 { 0x9003e, 0x47 },
851 { 0x9003f, 0x633 },
852 { 0x90040, 0x149 },
853 { 0x90041, 0x4f },
854 { 0x90042, 0x633 },
855 { 0x90043, 0x179 },
856 { 0x90044, 0x8 },
857 { 0x90045, 0xe0 },
858 { 0x90046, 0x109 },
859 { 0x90047, 0x0 },
860 { 0x90048, 0x7c8 },
861 { 0x90049, 0x109 },
862 { 0x9004a, 0x0 },
863 { 0x9004b, 0x1 },
864 { 0x9004c, 0x8 },
865 { 0x9004d, 0x0 },
866 { 0x9004e, 0x45a },
867 { 0x9004f, 0x9 },
868 { 0x90050, 0x0 },
869 { 0x90051, 0x448 },
870 { 0x90052, 0x109 },
871 { 0x90053, 0x40 },
872 { 0x90054, 0x633 },
873 { 0x90055, 0x179 },
874 { 0x90056, 0x1 },
875 { 0x90057, 0x618 },
876 { 0x90058, 0x109 },
877 { 0x90059, 0x40c0 },
878 { 0x9005a, 0x633 },
879 { 0x9005b, 0x149 },
880 { 0x9005c, 0x8 },
881 { 0x9005d, 0x4 },
882 { 0x9005e, 0x48 },
883 { 0x9005f, 0x4040 },
884 { 0x90060, 0x633 },
885 { 0x90061, 0x149 },
886 { 0x90062, 0x0 },
887 { 0x90063, 0x4 },
888 { 0x90064, 0x48 },
889 { 0x90065, 0x40 },
890 { 0x90066, 0x633 },
891 { 0x90067, 0x149 },
892 { 0x90068, 0x10 },
893 { 0x90069, 0x4 },
894 { 0x9006a, 0x18 },
895 { 0x9006b, 0x0 },
896 { 0x9006c, 0x4 },
897 { 0x9006d, 0x78 },
898 { 0x9006e, 0x549 },
899 { 0x9006f, 0x633 },
900 { 0x90070, 0x159 },
901 { 0x90071, 0xd49 },
902 { 0x90072, 0x633 },
903 { 0x90073, 0x159 },
904 { 0x90074, 0x94a },
905 { 0x90075, 0x633 },
906 { 0x90076, 0x159 },
907 { 0x90077, 0x441 },
908 { 0x90078, 0x633 },
909 { 0x90079, 0x149 },
910 { 0x9007a, 0x42 },
911 { 0x9007b, 0x633 },
912 { 0x9007c, 0x149 },
913 { 0x9007d, 0x1 },
914 { 0x9007e, 0x633 },
915 { 0x9007f, 0x149 },
916 { 0x90080, 0x0 },
917 { 0x90081, 0xe0 },
918 { 0x90082, 0x109 },
919 { 0x90083, 0xa },
920 { 0x90084, 0x10 },
921 { 0x90085, 0x109 },
922 { 0x90086, 0x9 },
923 { 0x90087, 0x3c0 },
924 { 0x90088, 0x149 },
925 { 0x90089, 0x9 },
926 { 0x9008a, 0x3c0 },
927 { 0x9008b, 0x159 },
928 { 0x9008c, 0x18 },
929 { 0x9008d, 0x10 },
930 { 0x9008e, 0x109 },
931 { 0x9008f, 0x0 },
932 { 0x90090, 0x3c0 },
933 { 0x90091, 0x109 },
934 { 0x90092, 0x18 },
935 { 0x90093, 0x4 },
936 { 0x90094, 0x48 },
937 { 0x90095, 0x18 },
938 { 0x90096, 0x4 },
939 { 0x90097, 0x58 },
940 { 0x90098, 0xb },
941 { 0x90099, 0x10 },
942 { 0x9009a, 0x109 },
943 { 0x9009b, 0x1 },
944 { 0x9009c, 0x10 },
945 { 0x9009d, 0x109 },
946 { 0x9009e, 0x5 },
947 { 0x9009f, 0x7c0 },
948 { 0x900a0, 0x109 },
949 { 0x900a1, 0x0 },
950 { 0x900a2, 0x8140 },
951 { 0x900a3, 0x10c },
952 { 0x900a4, 0x10 },
953 { 0x900a5, 0x8138 },
954 { 0x900a6, 0x10c },
955 { 0x900a7, 0x8 },
956 { 0x900a8, 0x7c8 },
957 { 0x900a9, 0x101 },
958 { 0x900aa, 0x8 },
959 { 0x900ab, 0x448 },
960 { 0x900ac, 0x109 },
961 { 0x900ad, 0xf },
962 { 0x900ae, 0x7c0 },
963 { 0x900af, 0x109 },
964 { 0x900b0, 0x47 },
965 { 0x900b1, 0x630 },
966 { 0x900b2, 0x109 },
967 { 0x900b3, 0x8 },
968 { 0x900b4, 0x618 },
969 { 0x900b5, 0x109 },
970 { 0x900b6, 0x8 },
971 { 0x900b7, 0xe0 },
972 { 0x900b8, 0x109 },
973 { 0x900b9, 0x0 },
974 { 0x900ba, 0x7c8 },
975 { 0x900bb, 0x109 },
976 { 0x900bc, 0x8 },
977 { 0x900bd, 0x8140 },
978 { 0x900be, 0x10c },
979 { 0x900bf, 0x0 },
980 { 0x900c0, 0x1 },
981 { 0x900c1, 0x8 },
982 { 0x900c2, 0x8 },
983 { 0x900c3, 0x4 },
984 { 0x900c4, 0x8 },
985 { 0x900c5, 0x8 },
986 { 0x900c6, 0x7c8 },
987 { 0x900c7, 0x101 },
988 { 0x90006, 0x0 },
989 { 0x90007, 0x0 },
990 { 0x90008, 0x8 },
991 { 0x90009, 0x0 },
992 { 0x9000a, 0x0 },
993 { 0x9000b, 0x0 },
994 { 0xd00e7, 0x400 },
995 { 0x90017, 0x0 },
996 { 0x90026, 0x2b },
997 { 0x2000b, 0x4b },
998 { 0x2000c, 0x96 },
999 { 0x2000d, 0x5dc },
1000 { 0x2000e, 0x2c },
1001 { 0x12000b, 0x21 },
1002 { 0x12000c, 0x42 },
1003 { 0x12000d, 0x29a },
1004 { 0x12000e, 0x21 },
1005 { 0x9000c, 0x0 },
1006 { 0x9000d, 0x173 },
1007 { 0x9000e, 0x60 },
1008 { 0x9000f, 0x6110 },
1009 { 0x90010, 0x2152 },
1010 { 0x90011, 0xdfbd },
1011 { 0x90012, 0xffff },
1012 { 0x90013, 0x6152 },
1013 { 0x20089, 0x1 },
1014 { 0x20088, 0x19 },
1015 { 0xc0080, 0x0 },
1016 { 0xd0000, 0x1 }
1017 };
1018
1019 struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1020 {
1021 /* P0 2400mts 1D */
1022 .drate = 2400,
1023 .fw_type = FW_1D_IMAGE,
1024 .fsp_cfg = ddr_fsp0_cfg,
1025 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1026 },
1027 {
1028 /* P1 1066mts 1D */
1029 .drate = 1066,
1030 .fw_type = FW_1D_IMAGE,
1031 .fsp_cfg = ddr_fsp1_cfg,
1032 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1033 },
1034 {
1035 /* P0 2400mts 2D */
1036 .drate = 2400,
1037 .fw_type = FW_2D_IMAGE,
1038 .fsp_cfg = ddr_fsp0_2d_cfg,
1039 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1040 },
1041 };
1042
1043 /* ddr timing config params */
1044 struct dram_timing_info dram_timing = {
1045 .ddrc_cfg = ddr_ddrc_cfg,
1046 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1047 .ddrphy_cfg = ddr_ddrphy_cfg,
1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1049 .fsp_msg = ddr_dram_fsp_msg,
1050 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1051 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1052 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1053 .ddrphy_pie = ddr_phy_pie,
1054 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1055 .fsp_table = { 2400, 1066, },
1056 };
1057
1058
board/freescale/imx8mm_ab2/imx8mm_ab2.c
Diff comments   View file @ 5187303
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2020 NXP 3 * Copyright 2020 NXP
4 */ 4 */
5 5
6 #include <common.h> 6 #include <common.h>
7 #include <malloc.h> 7 #include <malloc.h>
8 #include <errno.h> 8 #include <errno.h>
9 #include <miiphy.h> 9 #include <miiphy.h>
10 #include <netdev.h> 10 #include <netdev.h>
11 #include <fsl_esdhc.h> 11 #include <fsl_esdhc.h>
12 #include <mmc.h> 12 #include <mmc.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <asm/arch/clock.h> 14 #include <asm/arch/clock.h>
15 #ifdef CONFIG_TARGET_IMX8MM_AB2 15 #ifdef CONFIG_TARGET_IMX8MM_AB2
16 #include <asm/arch/imx8mm_pins.h> 16 #include <asm/arch/imx8mm_pins.h>
17 #else
18 #include <asm/arch/imx8mn_pins.h>
17 #endif 19 #endif
18 #include <asm/arch/sys_proto.h> 20 #include <asm/arch/sys_proto.h>
19 #include <asm-generic/gpio.h> 21 #include <asm-generic/gpio.h>
20 #include <asm/mach-imx/dma.h> 22 #include <asm/mach-imx/dma.h>
21 #include <asm/mach-imx/gpio.h> 23 #include <asm/mach-imx/gpio.h>
22 #include <asm/mach-imx/iomux-v3.h> 24 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/mach-imx/mxc_i2c.h> 25 #include <asm/mach-imx/mxc_i2c.h>
24 #include <spl.h> 26 #include <spl.h>
25 27
26 DECLARE_GLOBAL_DATA_PTR; 28 DECLARE_GLOBAL_DATA_PTR;
27 29
28 #define PWR_EN_5V0 IMX_GPIO_NR(1, 7) 30 #define PWR_EN_5V0 IMX_GPIO_NR(1, 7)
29 #define PWR_EN_ANA IMX_GPIO_NR(1, 10) 31 #define PWR_EN_ANA IMX_GPIO_NR(1, 10)
30 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) 32 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
31 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) 33 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
32 34
33 #ifdef CONFIG_TARGET_IMX8MM_AB2 35 #ifdef CONFIG_TARGET_IMX8MM_AB2
34 static iomux_v3_cfg_t const uart_pads[] = { 36 static iomux_v3_cfg_t const uart_pads[] = {
35 IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 37 IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
36 IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 38 IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
37 }; 39 };
38 40
39 static iomux_v3_cfg_t const wdog_pads[] = { 41 static iomux_v3_cfg_t const wdog_pads[] = {
40 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), 42 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
41 }; 43 };
42 44
43 static iomux_v3_cfg_t const pwr_en_5v0[] = { 45 static iomux_v3_cfg_t const pwr_en_5v0[] = {
44 IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), 46 IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
45 }; 47 };
46 48
47 static iomux_v3_cfg_t const pwr_en_ana[] = { 49 static iomux_v3_cfg_t const pwr_en_ana[] = {
48 IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 50 IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
49 }; 51 };
50 #endif 52 #endif
51 53
54 #if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2)
55 static iomux_v3_cfg_t const uart_pads[] = {
56 IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
57 IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
58 };
59
60 static iomux_v3_cfg_t const wdog_pads[] = {
61 IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
62 };
63
64 static iomux_v3_cfg_t const pwr_en_5v0[] = {
65 IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
66 };
67
68 static iomux_v3_cfg_t const pwr_en_ana[] = {
69 IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
70 };
71 #endif
72
52 #ifdef CONFIG_NAND_MXS 73 #ifdef CONFIG_NAND_MXS
53 static void setup_gpmi_nand(void) 74 static void setup_gpmi_nand(void)
54 { 75 {
55 init_nand_clk(); 76 init_nand_clk();
56 } 77 }
57 #endif 78 #endif
58 79
59 int board_early_init_f(void) 80 int board_early_init_f(void)
60 { 81 {
61 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 82 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
62 83
63 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 84 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
64 85
65 set_wdog_reset(wdog); 86 set_wdog_reset(wdog);
66 87
67 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 88 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
68 89
69 init_uart_clk(1); 90 init_uart_clk(1);
70 91
71 imx_iomux_v3_setup_multiple_pads(pwr_en_5v0, ARRAY_SIZE(pwr_en_5v0)); 92 imx_iomux_v3_setup_multiple_pads(pwr_en_5v0, ARRAY_SIZE(pwr_en_5v0));
72 gpio_request(PWR_EN_5V0, "pwr_en_5v0"); 93 gpio_request(PWR_EN_5V0, "pwr_en_5v0");
73 gpio_direction_output(PWR_EN_5V0, 1); 94 gpio_direction_output(PWR_EN_5V0, 1);
74 95
75 imx_iomux_v3_setup_multiple_pads(pwr_en_ana, ARRAY_SIZE(pwr_en_ana)); 96 imx_iomux_v3_setup_multiple_pads(pwr_en_ana, ARRAY_SIZE(pwr_en_ana));
76 gpio_request(PWR_EN_ANA, "pwr_en_ana"); 97 gpio_request(PWR_EN_ANA, "pwr_en_ana");
77 gpio_direction_output(PWR_EN_ANA, 1); 98 gpio_direction_output(PWR_EN_ANA, 1);
78 99
79 return 0; 100 return 0;
80 } 101 }
81 102
82 static int setup_fec(void) 103 static int setup_fec(void)
83 { 104 {
84 struct iomuxc_gpr_base_regs *gpr = 105 struct iomuxc_gpr_base_regs *gpr =
85 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 106 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
86 107
87 /* Use 125M anatop REF_CLK1 for ENET1, not from external */ 108 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
88 clrsetbits_le32(&gpr->gpr[1], 109 clrsetbits_le32(&gpr->gpr[1],
89 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0); 110 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
90 111
91 return set_clk_enet(ENET_125MHZ); 112 return set_clk_enet(ENET_125MHZ);
92 } 113 }
93 114
94 int board_phy_config(struct phy_device *phydev) 115 int board_phy_config(struct phy_device *phydev)
95 { 116 {
96 if (phydev->drv->config) 117 if (phydev->drv->config)
97 phydev->drv->config(phydev); 118 phydev->drv->config(phydev);
98 119
99 return 0; 120 return 0;
100 } 121 }
101 122
102 int board_init(void) 123 int board_init(void)
103 { 124 {
104 #ifdef CONFIG_FEC_MXC 125 #ifdef CONFIG_FEC_MXC
105 setup_fec(); 126 setup_fec();
106 #endif 127 #endif
107 128
108 #ifdef CONFIG_NAND_MXS 129 #ifdef CONFIG_NAND_MXS
109 setup_gpmi_nand(); 130 setup_gpmi_nand();
110 #endif 131 #endif
111 return 0; 132 return 0;
112 } 133 }
113 134
114 int board_late_init(void) 135 int board_late_init(void)
115 { 136 {
116 #ifdef CONFIG_ENV_IS_IN_MMC 137 #ifdef CONFIG_ENV_IS_IN_MMC
117 board_late_mmc_env_init(); 138 board_late_mmc_env_init();
118 #endif 139 #endif
119 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 140 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
120 env_set("board_name", "AB2"); 141 env_set("board_name", "AB2");
142 #ifdef CONFIG_TARGET_IMX8MM_AB2
121 env_set("board_rev", "iMX8MM"); 143 env_set("board_rev", "iMX8MM");
144 #else
145 env_set("board_rev", "iMX8MN");
146 #endif
122 #endif 147 #endif
123 return 0; 148 return 0;
124 } 149 }
125 150
board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c
Diff comments   View file @ 5187303
File was created 1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 *
5 * Generated code from MX8M_DDR_tool
6 * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
7 */
8
9 #include <linux/kernel.h>
10 #include <asm/arch/ddr.h>
11
12 struct dram_cfg_param ddr_ddrc_cfg[] = {
13 {0x3d400020, 0x00000213},
14 {0x3d400024, 0x0003e800},
15 {0x3d400030, 0x00000120},
16 {0x3d400000, 0xa3080020},
17 {0x3d400064, 0x006100e0},
18 {0x3d4000d0, 0xc003061c},
19 {0x3d4000d4, 0x009e0000},
20 {0x3d4000dc, 0x00d4002d},
21 {0x3d4000e0, 0x00310000},
22 {0x3d4000e8, 0x0066004d},
23 {0x3d4000ec, 0x0016004a},
24 {0x3d400100, 0x1a201b22},
25 {0x3d400104, 0x00060633},
26 {0x3d40010c, 0x00c0c000},
27 {0x3d400110, 0x0f04080f},
28 {0x3d400114, 0x02040c0c},
29 {0x3d400118, 0x01010007},
30 {0x3d40011c, 0x00000401},
31 {0x3d400130, 0x00020600},
32 {0x3d400134, 0x0c100002},
33 {0x3d400138, 0x000000e6},
34 {0x3d400144, 0x00a00050},
35 {0x3d400180, 0x03200018},
36 {0x3d400184, 0x028061a8},
37 {0x3d400188, 0x00000000},
38 {0x3d400190, 0x0497820a},
39 {0x3d4001b4, 0x0000170a},
40 {0x3d400108, 0x070e1617},
41 {0x3d4001c0, 0x00000001},
42 {0x3d400194, 0x00080303},
43 {0x3d4001a0, 0xe0400018},
44 {0x3d4001a4, 0x00df00e4},
45 {0x3d4001a8, 0x80000000},
46 {0x3d4001b0, 0x00000011},
47 {0x3d4001c4, 0x00000001},
48 {0x3d4000f4, 0x00000c99},
49 {0x3d400200, 0x00000017},
50 {0x3d400204, 0x00080808},
51 {0x3d400208, 0x00000000},
52 {0x3d40020c, 0x00000000},
53 {0x3d400210, 0x00001f1f},
54 {0x3d400214, 0x07070707},
55 {0x3d400218, 0x07070707},
56 {0x3d40021c, 0x00000f0f},
57 {0x3d400250, 0x29001701},
58 {0x3d400254, 0x0000002c},
59 {0x3d40025c, 0x04000030},
60 {0x3d400264, 0x900093e7},
61 {0x3d40026c, 0x20005574},
62 {0x3d400400, 0x00000111},
63 {0x3d400408, 0x000072ff},
64 {0x3d400494, 0x02100e07},
65 {0x3d400498, 0x00620096},
66 {0x3d40049c, 0x01100e07},
67 {0x3d4004a0, 0x00c8012c},
68 {0x3d402020, 0x00000011},
69 {0x3d402024, 0x00007d00},
70 {0x3d402050, 0x0020d040},
71 {0x3d402064, 0x000c001d},
72 {0x3d4020f4, 0x00000c99},
73 {0x3d402100, 0x0a040305},
74 {0x3d402104, 0x00030407},
75 {0x3d402108, 0x0203060b},
76 {0x3d40210c, 0x00505000},
77 {0x3d402110, 0x02040202},
78 {0x3d402114, 0x02030202},
79 {0x3d402118, 0x01010004},
80 {0x3d40211c, 0x00000301},
81 {0x3d402130, 0x00020300},
82 {0x3d402134, 0x0a100002},
83 {0x3d402138, 0x0000001d},
84 {0x3d402144, 0x0014000a},
85 {0x3d402180, 0x00650004},
86 {0x3d402190, 0x03818200},
87 {0x3d402194, 0x00080303},
88 {0x3d4021b4, 0x00000100},
89 {0x3d4020dc, 0x00840000},
90 {0x3d4020e0, 0x00310000},
91 {0x3d4020e8, 0x0066004d},
92 {0x3d4020ec, 0x0016004a},
93 {0x3d403020, 0x00000011},
94 {0x3d403024, 0x00001f40},
95 {0x3d403050, 0x0020d040},
96 {0x3d403064, 0x00030007},
97 {0x3d4030f4, 0x00000c99},
98 {0x3d403100, 0x0a010102},
99 {0x3d403104, 0x00030404},
100 {0x3d403108, 0x0203060b},
101 {0x3d40310c, 0x00505000},
102 {0x3d403110, 0x02040202},
103 {0x3d403114, 0x02030202},
104 {0x3d403118, 0x01010004},
105 {0x3d40311c, 0x00000301},
106 {0x3d403130, 0x00020300},
107 {0x3d403134, 0x0a100002},
108 {0x3d403138, 0x00000008},
109 {0x3d403144, 0x00050003},
110 {0x3d403180, 0x00190004},
111 {0x3d403190, 0x03818200},
112 {0x3d403194, 0x00080303},
113 {0x3d4031b4, 0x00000100},
114 {0x3d4030dc, 0x00840000},
115 {0x3d4030e0, 0x00310000},
116 {0x3d4030e8, 0x0066004d},
117 {0x3d4030ec, 0x0016004a},
118
119 /* default boot point */
120 { 0x3d400028, 0x0 },
121 };
122
123 /* PHY Initialize Configuration */
124 struct dram_cfg_param ddr_ddrphy_cfg[] = {
125 {0x000100a0, 0x00000000},
126 {0x000100a1, 0x00000001},
127 {0x000100a2, 0x00000002},
128 {0x000100a3, 0x00000003},
129 {0x000100a4, 0x00000004},
130 {0x000100a5, 0x00000005},
131 {0x000100a6, 0x00000006},
132 {0x000100a7, 0x00000007},
133 {0x000110a0, 0x00000000},
134 {0x000110a1, 0x00000001},
135 {0x000110a2, 0x00000003},
136 {0x000110a3, 0x00000004},
137 {0x000110a4, 0x00000005},
138 {0x000110a5, 0x00000002},
139 {0x000110a6, 0x00000007},
140 {0x000110a7, 0x00000006},
141 {0x0001005f, 0x0000015f},
142 {0x0001015f, 0x0000015f},
143 {0x0001105f, 0x0000015f},
144 {0x0001115f, 0x0000015f},
145 {0x0011005f, 0x0000015f},
146 {0x0011015f, 0x0000015f},
147 {0x0011105f, 0x0000015f},
148 {0x0011115f, 0x0000015f},
149 {0x0021005f, 0x0000015f},
150 {0x0021015f, 0x0000015f},
151 {0x0021105f, 0x0000015f},
152 {0x0021115f, 0x0000015f},
153 {0x00000055, 0x0000016f},
154 {0x00001055, 0x0000016f},
155 {0x00002055, 0x0000016f},
156 {0x00003055, 0x0000016f},
157 {0x00004055, 0x0000016f},
158 {0x00005055, 0x0000016f},
159 {0x00006055, 0x0000016f},
160 {0x00007055, 0x0000016f},
161 {0x00008055, 0x0000016f},
162 {0x00009055, 0x0000016f},
163 {0x000200c5, 0x00000019},
164 {0x001200c5, 0x00000007},
165 {0x002200c5, 0x00000007},
166 {0x0002002e, 0x00000002},
167 {0x0012002e, 0x00000002},
168 {0x0022002e, 0x00000002},
169 {0x00090204, 0x00000000},
170 {0x00190204, 0x00000000},
171 {0x00290204, 0x00000000},
172 {0x00020024, 0x000001a3},
173 {0x0002003a, 0x00000002},
174 {0x0002007d, 0x00000212},
175 {0x0002007c, 0x00000061},
176 {0x00120024, 0x000001a3},
177 {0x0002003a, 0x00000002},
178 {0x0012007d, 0x00000212},
179 {0x0012007c, 0x00000061},
180 {0x00220024, 0x000001a3},
181 {0x0002003a, 0x00000002},
182 {0x0022007d, 0x00000212},
183 {0x0022007c, 0x00000061},
184 {0x00020056, 0x00000003},
185 {0x00120056, 0x00000003},
186 {0x00220056, 0x00000003},
187 {0x0001004d, 0x00000f80},
188 {0x0001014d, 0x00000f80},
189 {0x0001104d, 0x00000f80},
190 {0x0001114d, 0x00000f80},
191 {0x0011004d, 0x00000f80},
192 {0x0011014d, 0x00000f80},
193 {0x0011104d, 0x00000f80},
194 {0x0011114d, 0x00000f80},
195 {0x0021004d, 0x00000f80},
196 {0x0021014d, 0x00000f80},
197 {0x0021104d, 0x00000f80},
198 {0x0021114d, 0x00000f80},
199 {0x00010049, 0x00000fbe},
200 {0x00010149, 0x00000fbe},
201 {0x00011049, 0x00000fbe},
202 {0x00011149, 0x00000fbe},
203 {0x00110049, 0x00000fbe},
204 {0x00110149, 0x00000fbe},
205 {0x00111049, 0x00000fbe},
206 {0x00111149, 0x00000fbe},
207 {0x00210049, 0x00000fbe},
208 {0x00210149, 0x00000fbe},
209 {0x00211049, 0x00000fbe},
210 {0x00211149, 0x00000fbe},
211 {0x00000043, 0x00000063},
212 {0x00001043, 0x00000063},
213 {0x00002043, 0x00000063},
214 {0x00003043, 0x00000063},
215 {0x00004043, 0x00000063},
216 {0x00005043, 0x00000063},
217 {0x00006043, 0x00000063},
218 {0x00007043, 0x00000063},
219 {0x00008043, 0x00000063},
220 {0x00009043, 0x00000063},
221 {0x00020018, 0x00000001},
222 {0x00020075, 0x00000004},
223 {0x00020050, 0x00000000},
224 {0x00020008, 0x00000320},
225 {0x00120008, 0x00000064},
226 {0x00220008, 0x00000019},
227 {0x00020088, 0x00000009},
228 {0x000200b2, 0x000000dc},
229 {0x00010043, 0x000005a1},
230 {0x00010143, 0x000005a1},
231 {0x00011043, 0x000005a1},
232 {0x00011143, 0x000005a1},
233 {0x001200b2, 0x000000dc},
234 {0x00110043, 0x000005a1},
235 {0x00110143, 0x000005a1},
236 {0x00111043, 0x000005a1},
237 {0x00111143, 0x000005a1},
238 {0x002200b2, 0x000000dc},
239 {0x00210043, 0x000005a1},
240 {0x00210143, 0x000005a1},
241 {0x00211043, 0x000005a1},
242 {0x00211143, 0x000005a1},
243 {0x000200fa, 0x00000001},
244 {0x001200fa, 0x00000001},
245 {0x002200fa, 0x00000001},
246 {0x00020019, 0x00000001},
247 {0x00120019, 0x00000001},
248 {0x00220019, 0x00000001},
249 {0x000200f0, 0x00000660},
250 {0x000200f1, 0x00000000},
251 {0x000200f2, 0x00004444},
252 {0x000200f3, 0x00008888},
253 {0x000200f4, 0x00005665},
254 {0x000200f5, 0x00000000},
255 {0x000200f6, 0x00000000},
256 {0x000200f7, 0x0000f000},
257 {0x0001004a, 0x00000500},
258 {0x0001104a, 0x00000500},
259 {0x00020025, 0x00000000},
260 {0x0002002d, 0x00000000},
261 {0x0012002d, 0x00000000},
262 {0x0022002d, 0x00000000},
263 {0x0002002c, 0x00000000},
264 {0x000200c7, 0x00000021},
265 {0x000200ca, 0x00000024},
266 {0x000200cc, 0x000001f7},
267 {0x001200c7, 0x00000021},
268 {0x001200ca, 0x00000024},
269 {0x001200cc, 0x000001f7},
270 {0x002200c7, 0x00000021},
271 {0x002200ca, 0x00000024},
272 {0x002200cc, 0x000001f7},
273 };
274
275 /* ddr phy trained csr */
276 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
277 {0x0200b2, 0x0},
278 {0x1200b2, 0x0},
279 {0x2200b2, 0x0},
280 {0x0200cb, 0x0},
281 {0x010043, 0x0},
282 {0x110043, 0x0},
283 {0x210043, 0x0},
284 {0x010143, 0x0},
285 {0x110143, 0x0},
286 {0x210143, 0x0},
287 {0x011043, 0x0},
288 {0x111043, 0x0},
289 {0x211043, 0x0},
290 {0x011143, 0x0},
291 {0x111143, 0x0},
292 {0x211143, 0x0},
293 {0x000080, 0x0},
294 {0x100080, 0x0},
295 {0x200080, 0x0},
296 {0x001080, 0x0},
297 {0x101080, 0x0},
298 {0x201080, 0x0},
299 {0x002080, 0x0},
300 {0x102080, 0x0},
301 {0x202080, 0x0},
302 {0x003080, 0x0},
303 {0x103080, 0x0},
304 {0x203080, 0x0},
305 {0x004080, 0x0},
306 {0x104080, 0x0},
307 {0x204080, 0x0},
308 {0x005080, 0x0},
309 {0x105080, 0x0},
310 {0x205080, 0x0},
311 {0x006080, 0x0},
312 {0x106080, 0x0},
313 {0x206080, 0x0},
314 {0x007080, 0x0},
315 {0x107080, 0x0},
316 {0x207080, 0x0},
317 {0x008080, 0x0},
318 {0x108080, 0x0},
319 {0x208080, 0x0},
320 {0x009080, 0x0},
321 {0x109080, 0x0},
322 {0x209080, 0x0},
323 {0x010080, 0x0},
324 {0x110080, 0x0},
325 {0x210080, 0x0},
326 {0x010180, 0x0},
327 {0x110180, 0x0},
328 {0x210180, 0x0},
329 {0x011080, 0x0},
330 {0x111080, 0x0},
331 {0x211080, 0x0},
332 {0x011180, 0x0},
333 {0x111180, 0x0},
334 {0x211180, 0x0},
335 {0x010081, 0x0},
336 {0x110081, 0x0},
337 {0x210081, 0x0},
338 {0x010181, 0x0},
339 {0x110181, 0x0},
340 {0x210181, 0x0},
341 {0x011081, 0x0},
342 {0x111081, 0x0},
343 {0x211081, 0x0},
344 {0x011181, 0x0},
345 {0x111181, 0x0},
346 {0x211181, 0x0},
347 {0x0100d0, 0x0},
348 {0x1100d0, 0x0},
349 {0x2100d0, 0x0},
350 {0x0101d0, 0x0},
351 {0x1101d0, 0x0},
352 {0x2101d0, 0x0},
353 {0x0110d0, 0x0},
354 {0x1110d0, 0x0},
355 {0x2110d0, 0x0},
356 {0x0111d0, 0x0},
357 {0x1111d0, 0x0},
358 {0x2111d0, 0x0},
359 {0x0100d1, 0x0},
360 {0x1100d1, 0x0},
361 {0x2100d1, 0x0},
362 {0x0101d1, 0x0},
363 {0x1101d1, 0x0},
364 {0x2101d1, 0x0},
365 {0x0110d1, 0x0},
366 {0x1110d1, 0x0},
367 {0x2110d1, 0x0},
368 {0x0111d1, 0x0},
369 {0x1111d1, 0x0},
370 {0x2111d1, 0x0},
371 {0x010068, 0x0},
372 {0x010168, 0x0},
373 {0x010268, 0x0},
374 {0x010368, 0x0},
375 {0x010468, 0x0},
376 {0x010568, 0x0},
377 {0x010668, 0x0},
378 {0x010768, 0x0},
379 {0x010868, 0x0},
380 {0x011068, 0x0},
381 {0x011168, 0x0},
382 {0x011268, 0x0},
383 {0x011368, 0x0},
384 {0x011468, 0x0},
385 {0x011568, 0x0},
386 {0x011668, 0x0},
387 {0x011768, 0x0},
388 {0x011868, 0x0},
389 {0x010069, 0x0},
390 {0x010169, 0x0},
391 {0x010269, 0x0},
392 {0x010369, 0x0},
393 {0x010469, 0x0},
394 {0x010569, 0x0},
395 {0x010669, 0x0},
396 {0x010769, 0x0},
397 {0x010869, 0x0},
398 {0x011069, 0x0},
399 {0x011169, 0x0},
400 {0x011269, 0x0},
401 {0x011369, 0x0},
402 {0x011469, 0x0},
403 {0x011569, 0x0},
404 {0x011669, 0x0},
405 {0x011769, 0x0},
406 {0x011869, 0x0},
407 {0x01008c, 0x0},
408 {0x11008c, 0x0},
409 {0x21008c, 0x0},
410 {0x01018c, 0x0},
411 {0x11018c, 0x0},
412 {0x21018c, 0x0},
413 {0x01108c, 0x0},
414 {0x11108c, 0x0},
415 {0x21108c, 0x0},
416 {0x01118c, 0x0},
417 {0x11118c, 0x0},
418 {0x21118c, 0x0},
419 {0x01008d, 0x0},
420 {0x11008d, 0x0},
421 {0x21008d, 0x0},
422 {0x01018d, 0x0},
423 {0x11018d, 0x0},
424 {0x21018d, 0x0},
425 {0x01108d, 0x0},
426 {0x11108d, 0x0},
427 {0x21108d, 0x0},
428 {0x01118d, 0x0},
429 {0x11118d, 0x0},
430 {0x21118d, 0x0},
431 {0x0100c0, 0x0},
432 {0x1100c0, 0x0},
433 {0x2100c0, 0x0},
434 {0x0101c0, 0x0},
435 {0x1101c0, 0x0},
436 {0x2101c0, 0x0},
437 {0x0102c0, 0x0},
438 {0x1102c0, 0x0},
439 {0x2102c0, 0x0},
440 {0x0103c0, 0x0},
441 {0x1103c0, 0x0},
442 {0x2103c0, 0x0},
443 {0x0104c0, 0x0},
444 {0x1104c0, 0x0},
445 {0x2104c0, 0x0},
446 {0x0105c0, 0x0},
447 {0x1105c0, 0x0},
448 {0x2105c0, 0x0},
449 {0x0106c0, 0x0},
450 {0x1106c0, 0x0},
451 {0x2106c0, 0x0},
452 {0x0107c0, 0x0},
453 {0x1107c0, 0x0},
454 {0x2107c0, 0x0},
455 {0x0108c0, 0x0},
456 {0x1108c0, 0x0},
457 {0x2108c0, 0x0},
458 {0x0110c0, 0x0},
459 {0x1110c0, 0x0},
460 {0x2110c0, 0x0},
461 {0x0111c0, 0x0},
462 {0x1111c0, 0x0},
463 {0x2111c0, 0x0},
464 {0x0112c0, 0x0},
465 {0x1112c0, 0x0},
466 {0x2112c0, 0x0},
467 {0x0113c0, 0x0},
468 {0x1113c0, 0x0},
469 {0x2113c0, 0x0},
470 {0x0114c0, 0x0},
471 {0x1114c0, 0x0},
472 {0x2114c0, 0x0},
473 {0x0115c0, 0x0},
474 {0x1115c0, 0x0},
475 {0x2115c0, 0x0},
476 {0x0116c0, 0x0},
477 {0x1116c0, 0x0},
478 {0x2116c0, 0x0},
479 {0x0117c0, 0x0},
480 {0x1117c0, 0x0},
481 {0x2117c0, 0x0},
482 {0x0118c0, 0x0},
483 {0x1118c0, 0x0},
484 {0x2118c0, 0x0},
485 {0x0100c1, 0x0},
486 {0x1100c1, 0x0},
487 {0x2100c1, 0x0},
488 {0x0101c1, 0x0},
489 {0x1101c1, 0x0},
490 {0x2101c1, 0x0},
491 {0x0102c1, 0x0},
492 {0x1102c1, 0x0},
493 {0x2102c1, 0x0},
494 {0x0103c1, 0x0},
495 {0x1103c1, 0x0},
496 {0x2103c1, 0x0},
497 {0x0104c1, 0x0},
498 {0x1104c1, 0x0},
499 {0x2104c1, 0x0},
500 {0x0105c1, 0x0},
501 {0x1105c1, 0x0},
502 {0x2105c1, 0x0},
503 {0x0106c1, 0x0},
504 {0x1106c1, 0x0},
505 {0x2106c1, 0x0},
506 {0x0107c1, 0x0},
507 {0x1107c1, 0x0},
508 {0x2107c1, 0x0},
509 {0x0108c1, 0x0},
510 {0x1108c1, 0x0},
511 {0x2108c1, 0x0},
512 {0x0110c1, 0x0},
513 {0x1110c1, 0x0},
514 {0x2110c1, 0x0},
515 {0x0111c1, 0x0},
516 {0x1111c1, 0x0},
517 {0x2111c1, 0x0},
518 {0x0112c1, 0x0},
519 {0x1112c1, 0x0},
520 {0x2112c1, 0x0},
521 {0x0113c1, 0x0},
522 {0x1113c1, 0x0},
523 {0x2113c1, 0x0},
524 {0x0114c1, 0x0},
525 {0x1114c1, 0x0},
526 {0x2114c1, 0x0},
527 {0x0115c1, 0x0},
528 {0x1115c1, 0x0},
529 {0x2115c1, 0x0},
530 {0x0116c1, 0x0},
531 {0x1116c1, 0x0},
532 {0x2116c1, 0x0},
533 {0x0117c1, 0x0},
534 {0x1117c1, 0x0},
535 {0x2117c1, 0x0},
536 {0x0118c1, 0x0},
537 {0x1118c1, 0x0},
538 {0x2118c1, 0x0},
539 {0x010020, 0x0},
540 {0x110020, 0x0},
541 {0x210020, 0x0},
542 {0x011020, 0x0},
543 {0x111020, 0x0},
544 {0x211020, 0x0},
545 {0x020072, 0x0},
546 {0x020073, 0x0},
547 {0x020074, 0x0},
548 {0x0100aa, 0x0},
549 {0x0110aa, 0x0},
550 {0x020010, 0x0},
551 {0x120010, 0x0},
552 {0x220010, 0x0},
553 {0x020011, 0x0},
554 {0x120011, 0x0},
555 {0x220011, 0x0},
556 {0x0100ae, 0x0},
557 {0x1100ae, 0x0},
558 {0x2100ae, 0x0},
559 {0x0100af, 0x0},
560 {0x1100af, 0x0},
561 {0x2100af, 0x0},
562 {0x0110ae, 0x0},
563 {0x1110ae, 0x0},
564 {0x2110ae, 0x0},
565 {0x0110af, 0x0},
566 {0x1110af, 0x0},
567 {0x2110af, 0x0},
568 {0x020020, 0x0},
569 {0x120020, 0x0},
570 {0x220020, 0x0},
571 {0x0100a0, 0x0},
572 {0x0100a1, 0x0},
573 {0x0100a2, 0x0},
574 {0x0100a3, 0x0},
575 {0x0100a4, 0x0},
576 {0x0100a5, 0x0},
577 {0x0100a6, 0x0},
578 {0x0100a7, 0x0},
579 {0x0110a0, 0x0},
580 {0x0110a1, 0x0},
581 {0x0110a2, 0x0},
582 {0x0110a3, 0x0},
583 {0x0110a4, 0x0},
584 {0x0110a5, 0x0},
585 {0x0110a6, 0x0},
586 {0x0110a7, 0x0},
587 {0x02007c, 0x0},
588 {0x12007c, 0x0},
589 {0x22007c, 0x0},
590 {0x02007d, 0x0},
591 {0x12007d, 0x0},
592 {0x22007d, 0x0},
593 {0x0400fd, 0x0},
594 {0x0400c0, 0x0},
595 {0x090201, 0x0},
596 {0x190201, 0x0},
597 {0x290201, 0x0},
598 {0x090202, 0x0},
599 {0x190202, 0x0},
600 {0x290202, 0x0},
601 {0x090203, 0x0},
602 {0x190203, 0x0},
603 {0x290203, 0x0},
604 {0x090204, 0x0},
605 {0x190204, 0x0},
606 {0x290204, 0x0},
607 {0x090205, 0x0},
608 {0x190205, 0x0},
609 {0x290205, 0x0},
610 {0x090206, 0x0},
611 {0x190206, 0x0},
612 {0x290206, 0x0},
613 {0x090207, 0x0},
614 {0x190207, 0x0},
615 {0x290207, 0x0},
616 {0x090208, 0x0},
617 {0x190208, 0x0},
618 {0x290208, 0x0},
619 {0x010062, 0x0},
620 {0x010162, 0x0},
621 {0x010262, 0x0},
622 {0x010362, 0x0},
623 {0x010462, 0x0},
624 {0x010562, 0x0},
625 {0x010662, 0x0},
626 {0x010762, 0x0},
627 {0x010862, 0x0},
628 {0x011062, 0x0},
629 {0x011162, 0x0},
630 {0x011262, 0x0},
631 {0x011362, 0x0},
632 {0x011462, 0x0},
633 {0x011562, 0x0},
634 {0x011662, 0x0},
635 {0x011762, 0x0},
636 {0x011862, 0x0},
637 {0x020077, 0x0},
638 {0x010001, 0x0},
639 {0x011001, 0x0},
640 {0x010040, 0x0},
641 {0x010140, 0x0},
642 {0x010240, 0x0},
643 {0x010340, 0x0},
644 {0x010440, 0x0},
645 {0x010540, 0x0},
646 {0x010640, 0x0},
647 {0x010740, 0x0},
648 {0x010840, 0x0},
649 {0x010030, 0x0},
650 {0x010130, 0x0},
651 {0x010230, 0x0},
652 {0x010330, 0x0},
653 {0x010430, 0x0},
654 {0x010530, 0x0},
655 {0x010630, 0x0},
656 {0x010730, 0x0},
657 {0x010830, 0x0},
658 {0x011040, 0x0},
659 {0x011140, 0x0},
660 {0x011240, 0x0},
661 {0x011340, 0x0},
662 {0x011440, 0x0},
663 {0x011540, 0x0},
664 {0x011640, 0x0},
665 {0x011740, 0x0},
666 {0x011840, 0x0},
667 {0x011030, 0x0},
668 {0x011130, 0x0},
669 {0x011230, 0x0},
670 {0x011330, 0x0},
671 {0x011430, 0x0},
672 {0x011530, 0x0},
673 {0x011630, 0x0},
674 {0x011730, 0x0},
675 {0x011830, 0x0},
676 };
677
678 /* P0 message block paremeter for training firmware */
679 struct dram_cfg_param ddr_fsp0_cfg[] = {
680 {0x000d0000, 0x00000000},
681 {0x00054000, 0x00000000},
682 {0x00054001, 0x00000000},
683 {0x00054002, 0x00000000},
684 {0x00054003, 0x00000c80},
685 {0x00054004, 0x00000002},
686 {0x00054005, 0x00000000},
687 {0x00054006, 0x00000011},
688 {0x00054007, 0x00000000},
689 {0x00054008, 0x0000131f},
690 {0x00054009, 0x000000c8},
691 {0x0005400a, 0x00000000},
692 {0x0005400b, 0x00000002},
693 {0x0005400c, 0x00000000},
694 {0x0005400d, 0x00000000},
695 {0x0005400e, 0x00000000},
696 {0x0005400f, 0x00000100},
697 {0x00054010, 0x00000000},
698 {0x00054011, 0x00000000},
699 {0x00054012, 0x00000310},
700 {0x00054013, 0x00000000},
701 {0x00054014, 0x00000000},
702 {0x00054015, 0x00000000},
703 {0x00054016, 0x00000000},
704 {0x00054017, 0x00000000},
705 {0x00054018, 0x00000000},
706 {0x00054019, 0x00002dd4},
707 {0x0005401a, 0x00000031},
708 {0x0005401b, 0x00004d66},
709 {0x0005401c, 0x00004a00},
710 {0x0005401d, 0x00000000},
711 {0x0005401e, 0x00000016},
712 {0x0005401f, 0x00002dd4},
713 {0x00054020, 0x00000031},
714 {0x00054021, 0x00004d66},
715 {0x00054022, 0x00004a00},
716 {0x00054023, 0x00000000},
717 {0x00054024, 0x0000002e},
718 {0x00054025, 0x00000000},
719 {0x00054026, 0x00000000},
720 {0x00054027, 0x00000000},
721 {0x00054028, 0x00000000},
722 {0x00054029, 0x00000000},
723 {0x0005402a, 0x00000000},
724 {0x0005402b, 0x00000000},
725 {0x0005402c, 0x00000000},
726 {0x0005402d, 0x00000000},
727 {0x0005402e, 0x00000000},
728 {0x0005402f, 0x00000000},
729 {0x00054030, 0x00000000},
730 {0x00054031, 0x00000000},
731 {0x00054032, 0x0000d400},
732 {0x00054033, 0x0000312d},
733 {0x00054034, 0x00006600},
734 {0x00054035, 0x0000004d},
735 {0x00054036, 0x0000004a},
736 {0x00054037, 0x00001600},
737 {0x00054038, 0x0000d400},
738 {0x00054039, 0x0000312d},
739 {0x0005403a, 0x00006600},
740 {0x0005403b, 0x0000004d},
741 {0x0005403c, 0x0000004a},
742 {0x0005403d, 0x00002e00},
743 {0x0005403e, 0x00000000},
744 {0x0005403f, 0x00000000},
745 {0x00054040, 0x00000000},
746 {0x00054041, 0x00000000},
747 {0x00054042, 0x00000000},
748 {0x00054043, 0x00000000},
749 {0x00054044, 0x00000000},
750 {0x000d0000, 0x00000001},
751 };
752
753 /* P1 message block paremeter for training firmware */
754 struct dram_cfg_param ddr_fsp1_cfg[] = {
755 {0x000d0000, 0x00000000},
756 {0x00054000, 0x00000000},
757 {0x00054001, 0x00000000},
758 {0x00054002, 0x00000101},
759 {0x00054003, 0x00000190},
760 {0x00054004, 0x00000002},
761 {0x00054005, 0x00000000},
762 {0x00054006, 0x00000011},
763 {0x00054007, 0x00000000},
764 {0x00054008, 0x0000121f},
765 {0x00054009, 0x000000c8},
766 {0x0005400a, 0x00000000},
767 {0x0005400b, 0x00000002},
768 {0x0005400c, 0x00000000},
769 {0x0005400d, 0x00000000},
770 {0x0005400e, 0x00000000},
771 {0x0005400f, 0x00000100},
772 {0x00054010, 0x00000000},
773 {0x00054011, 0x00000000},
774 {0x00054012, 0x00000310},
775 {0x00054013, 0x00000000},
776 {0x00054014, 0x00000000},
777 {0x00054015, 0x00000000},
778 {0x00054016, 0x00000000},
779 {0x00054017, 0x00000000},
780 {0x00054018, 0x00000000},
781 {0x00054019, 0x00000084},
782 {0x0005401a, 0x00000031},
783 {0x0005401b, 0x00004d66},
784 {0x0005401c, 0x00004a00},
785 {0x0005401d, 0x00000000},
786 {0x0005401e, 0x00000016},
787 {0x0005401f, 0x00000084},
788 {0x00054020, 0x00000031},
789 {0x00054021, 0x00004d66},
790 {0x00054022, 0x00004a00},
791 {0x00054023, 0x00000000},
792 {0x00054024, 0x0000002e},
793 {0x00054025, 0x00000000},
794 {0x00054026, 0x00000000},
795 {0x00054027, 0x00000000},
796 {0x00054028, 0x00000000},
797 {0x00054029, 0x00000000},
798 {0x0005402a, 0x00000000},
799 {0x0005402b, 0x00000000},
800 {0x0005402c, 0x00000000},
801 {0x0005402d, 0x00000000},
802 {0x0005402e, 0x00000000},
803 {0x0005402f, 0x00000000},
804 {0x00054030, 0x00000000},
805 {0x00054031, 0x00000000},
806 {0x00054032, 0x00008400},
807 {0x00054033, 0x00003100},
808 {0x00054034, 0x00006600},
809 {0x00054035, 0x0000004d},
810 {0x00054036, 0x0000004a},
811 {0x00054037, 0x00001600},
812 {0x00054038, 0x00008400},
813 {0x00054039, 0x00003100},
814 {0x0005403a, 0x00006600},
815 {0x0005403b, 0x0000004d},
816 {0x0005403c, 0x0000004a},
817 {0x0005403d, 0x00002e00},
818 {0x0005403e, 0x00000000},
819 {0x0005403f, 0x00000000},
820 {0x00054040, 0x00000000},
821 {0x00054041, 0x00000000},
822 {0x00054042, 0x00000000},
823 {0x00054043, 0x00000000},
824 {0x00054044, 0x00000000},
825 {0x000d0000, 0x00000001},
826 };
827
828
829 /* P2 message block paremeter for training firmware */
830 struct dram_cfg_param ddr_fsp2_cfg[] = {
831 {0x000d0000, 0x00000000},
832 {0x00054000, 0x00000000},
833 {0x00054001, 0x00000000},
834 {0x00054002, 0x00000102},
835 {0x00054003, 0x00000064},
836 {0x00054004, 0x00000002},
837 {0x00054005, 0x00000000},
838 {0x00054006, 0x00000011},
839 {0x00054007, 0x00000000},
840 {0x00054008, 0x0000121f},
841 {0x00054009, 0x000000c8},
842 {0x0005400a, 0x00000000},
843 {0x0005400b, 0x00000002},
844 {0x0005400c, 0x00000000},
845 {0x0005400d, 0x00000000},
846 {0x0005400e, 0x00000000},
847 {0x0005400f, 0x00000100},
848 {0x00054010, 0x00000000},
849 {0x00054011, 0x00000000},
850 {0x00054012, 0x00000310},
851 {0x00054013, 0x00000000},
852 {0x00054014, 0x00000000},
853 {0x00054015, 0x00000000},
854 {0x00054016, 0x00000000},
855 {0x00054017, 0x00000000},
856 {0x00054018, 0x00000000},
857 {0x00054019, 0x00000084},
858 {0x0005401a, 0x00000031},
859 {0x0005401b, 0x00004d66},
860 {0x0005401c, 0x00004a00},
861 {0x0005401d, 0x00000000},
862 {0x0005401e, 0x00000016},
863 {0x0005401f, 0x00000084},
864 {0x00054020, 0x00000031},
865 {0x00054021, 0x00004d66},
866 {0x00054022, 0x00004a00},
867 {0x00054023, 0x00000000},
868 {0x00054024, 0x0000002e},
869 {0x00054025, 0x00000000},
870 {0x00054026, 0x00000000},
871 {0x00054027, 0x00000000},
872 {0x00054028, 0x00000000},
873 {0x00054029, 0x00000000},
874 {0x0005402a, 0x00000000},
875 {0x0005402b, 0x00000000},
876 {0x0005402c, 0x00000000},
877 {0x0005402d, 0x00000000},
878 {0x0005402e, 0x00000000},
879 {0x0005402f, 0x00000000},
880 {0x00054030, 0x00000000},
881 {0x00054031, 0x00000000},
882 {0x00054032, 0x00008400},
883 {0x00054033, 0x00003100},
884 {0x00054034, 0x00006600},
885 {0x00054035, 0x0000004d},
886 {0x00054036, 0x0000004a},
887 {0x00054037, 0x00001600},
888 {0x00054038, 0x00008400},
889 {0x00054039, 0x00003100},
890 {0x0005403a, 0x00006600},
891 {0x0005403b, 0x0000004d},
892 {0x0005403c, 0x0000004a},
893 {0x0005403d, 0x00002e00},
894 {0x0005403e, 0x00000000},
895 {0x0005403f, 0x00000000},
896 {0x00054040, 0x00000000},
897 {0x00054041, 0x00000000},
898 {0x00054042, 0x00000000},
899 {0x00054043, 0x00000000},
900 {0x00054044, 0x00000000},
901 {0x000d0000, 0x00000001},
902 };
903
904 /* P0 2D message block paremeter for training firmware */
905 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
906 {0x000d0000, 0x00000000},
907 {0x00054000, 0x00000000},
908 {0x00054001, 0x00000000},
909 {0x00054002, 0x00000000},
910 {0x00054003, 0x00000c80},
911 {0x00054004, 0x00000002},
912 {0x00054005, 0x00000000},
913 {0x00054006, 0x00000011},
914 {0x00054007, 0x00000000},
915 {0x00054008, 0x00000061},
916 {0x00054009, 0x000000c8},
917 {0x0005400a, 0x00000000},
918 {0x0005400b, 0x00000002},
919 {0x0005400c, 0x00000000},
920 {0x0005400d, 0x00000000},
921 {0x0005400e, 0x00000000},
922 {0x0005400f, 0x00000100},
923 {0x00054010, 0x00001f7f},
924 {0x00054011, 0x00000000},
925 {0x00054012, 0x00000310},
926 {0x00054013, 0x00000000},
927 {0x00054014, 0x00000000},
928 {0x00054015, 0x00000000},
929 {0x00054016, 0x00000000},
930 {0x00054017, 0x00000000},
931 {0x00054018, 0x00000000},
932 {0x00054019, 0x00002dd4},
933 {0x0005401a, 0x00000031},
934 {0x0005401b, 0x00004d66},
935 {0x0005401c, 0x00004a00},
936 {0x0005401d, 0x00000000},
937 {0x0005401e, 0x00000016},
938 {0x0005401f, 0x00002dd4},
939 {0x00054020, 0x00000031},
940 {0x00054021, 0x00004d66},
941 {0x00054022, 0x00004a00},
942 {0x00054023, 0x00000000},
943 {0x00054024, 0x0000002e},
944 {0x00054025, 0x00000000},
945 {0x00054026, 0x00000000},
946 {0x00054027, 0x00000000},
947 {0x00054028, 0x00000000},
948 {0x00054029, 0x00000000},
949 {0x0005402a, 0x00000000},
950 {0x0005402b, 0x00000000},
951 {0x0005402c, 0x00000000},
952 {0x0005402d, 0x00000000},
953 {0x0005402e, 0x00000000},
954 {0x0005402f, 0x00000000},
955 {0x00054030, 0x00000000},
956 {0x00054031, 0x00000000},
957 {0x00054032, 0x0000d400},
958 {0x00054033, 0x0000312d},
959 {0x00054034, 0x00006600},
960 {0x00054035, 0x0000004d},
961 {0x00054036, 0x0000004a},
962 {0x00054037, 0x00001600},
963 {0x00054038, 0x0000d400},
964 {0x00054039, 0x0000312d},
965 {0x0005403a, 0x00006600},
966 {0x0005403b, 0x0000004d},
967 {0x0005403c, 0x0000004a},
968 {0x0005403d, 0x00002e00},
969 {0x0005403e, 0x00000000},
970 {0x0005403f, 0x00000000},
971 {0x00054040, 0x00000000},
972 {0x00054041, 0x00000000},
973 {0x00054042, 0x00000000},
974 {0x00054043, 0x00000000},
975 {0x00054044, 0x00000000},
976 {0x000d0000, 0x00000001},
977 };
978
979 /* DRAM PHY init engine image */
980 struct dram_cfg_param ddr_phy_pie[] = {
981 {0xd0000, 0x0},
982 {0x90000, 0x10},
983 {0x90001, 0x400},
984 {0x90002, 0x10e},
985 {0x90003, 0x0},
986 {0x90004, 0x0},
987 {0x90005, 0x8},
988 {0x90029, 0xb},
989 {0x9002a, 0x480},
990 {0x9002b, 0x109},
991 {0x9002c, 0x8},
992 {0x9002d, 0x448},
993 {0x9002e, 0x139},
994 {0x9002f, 0x8},
995 {0x90030, 0x478},
996 {0x90031, 0x109},
997 {0x90032, 0x0},
998 {0x90033, 0xe8},
999 {0x90034, 0x109},
1000 {0x90035, 0x2},
1001 {0x90036, 0x10},
1002 {0x90037, 0x139},
1003 {0x90038, 0xb},
1004 {0x90039, 0x7c0},
1005 {0x9003a, 0x139},
1006 {0x9003b, 0x44},
1007 {0x9003c, 0x633},
1008 {0x9003d, 0x159},
1009 {0x9003e, 0x14f},
1010 {0x9003f, 0x630},
1011 {0x90040, 0x159},
1012 {0x90041, 0x47},
1013 {0x90042, 0x633},
1014 {0x90043, 0x149},
1015 {0x90044, 0x4f},
1016 {0x90045, 0x633},
1017 {0x90046, 0x179},
1018 {0x90047, 0x8},
1019 {0x90048, 0xe0},
1020 {0x90049, 0x109},
1021 {0x9004a, 0x0},
1022 {0x9004b, 0x7c8},
1023 {0x9004c, 0x109},
1024 {0x9004d, 0x0},
1025 {0x9004e, 0x1},
1026 {0x9004f, 0x8},
1027 {0x90050, 0x0},
1028 {0x90051, 0x45a},
1029 {0x90052, 0x9},
1030 {0x90053, 0x0},
1031 {0x90054, 0x448},
1032 {0x90055, 0x109},
1033 {0x90056, 0x40},
1034 {0x90057, 0x633},
1035 {0x90058, 0x179},
1036 {0x90059, 0x1},
1037 {0x9005a, 0x618},
1038 {0x9005b, 0x109},
1039 {0x9005c, 0x40c0},
1040 {0x9005d, 0x633},
1041 {0x9005e, 0x149},
1042 {0x9005f, 0x8},
1043 {0x90060, 0x4},
1044 {0x90061, 0x48},
1045 {0x90062, 0x4040},
1046 {0x90063, 0x633},
1047 {0x90064, 0x149},
1048 {0x90065, 0x0},
1049 {0x90066, 0x4},
1050 {0x90067, 0x48},
1051 {0x90068, 0x40},
1052 {0x90069, 0x633},
1053 {0x9006a, 0x149},
1054 {0x9006b, 0x10},
1055 {0x9006c, 0x4},
1056 {0x9006d, 0x18},
1057 {0x9006e, 0x0},
1058 {0x9006f, 0x4},
1059 {0x90070, 0x78},
1060 {0x90071, 0x549},
1061 {0x90072, 0x633},
1062 {0x90073, 0x159},
1063 {0x90074, 0xd49},
1064 {0x90075, 0x633},
1065 {0x90076, 0x159},
1066 {0x90077, 0x94a},
1067 {0x90078, 0x633},
1068 {0x90079, 0x159},
1069 {0x9007a, 0x441},
1070 {0x9007b, 0x633},
1071 {0x9007c, 0x149},
1072 {0x9007d, 0x42},
1073 {0x9007e, 0x633},
1074 {0x9007f, 0x149},
1075 {0x90080, 0x1},
1076 {0x90081, 0x633},
1077 {0x90082, 0x149},
1078 {0x90083, 0x0},
1079 {0x90084, 0xe0},
1080 {0x90085, 0x109},
1081 {0x90086, 0xa},
1082 {0x90087, 0x10},
1083 {0x90088, 0x109},
1084 {0x90089, 0x9},
1085 {0x9008a, 0x3c0},
1086 {0x9008b, 0x149},
1087 {0x9008c, 0x9},
1088 {0x9008d, 0x3c0},
1089 {0x9008e, 0x159},
1090 {0x9008f, 0x18},
1091 {0x90090, 0x10},
1092 {0x90091, 0x109},
1093 {0x90092, 0x0},
1094 {0x90093, 0x3c0},
1095 {0x90094, 0x109},
1096 {0x90095, 0x18},
1097 {0x90096, 0x4},
1098 {0x90097, 0x48},
1099 {0x90098, 0x18},
1100 {0x90099, 0x4},
1101 {0x9009a, 0x58},
1102 {0x9009b, 0xb},
1103 {0x9009c, 0x10},
1104 {0x9009d, 0x109},
1105 {0x9009e, 0x1},
1106 {0x9009f, 0x10},
1107 {0x900a0, 0x109},
1108 {0x900a1, 0x5},
1109 {0x900a2, 0x7c0},
1110 {0x900a3, 0x109},
1111 {0x40000, 0x811},
1112 {0x40020, 0x880},
1113 {0x40040, 0x0},
1114 {0x40060, 0x0},
1115 {0x40001, 0x4008},
1116 {0x40021, 0x83},
1117 {0x40041, 0x4f},
1118 {0x40061, 0x0},
1119 {0x40002, 0x4040},
1120 {0x40022, 0x83},
1121 {0x40042, 0x51},
1122 {0x40062, 0x0},
1123 {0x40003, 0x811},
1124 {0x40023, 0x880},
1125 {0x40043, 0x0},
1126 {0x40063, 0x0},
1127 {0x40004, 0x720},
1128 {0x40024, 0xf},
1129 {0x40044, 0x1740},
1130 {0x40064, 0x0},
1131 {0x40005, 0x16},
1132 {0x40025, 0x83},
1133 {0x40045, 0x4b},
1134 {0x40065, 0x0},
1135 {0x40006, 0x716},
1136 {0x40026, 0xf},
1137 {0x40046, 0x2001},
1138 {0x40066, 0x0},
1139 {0x40007, 0x716},
1140 {0x40027, 0xf},
1141 {0x40047, 0x2800},
1142 {0x40067, 0x0},
1143 {0x40008, 0x716},
1144 {0x40028, 0xf},
1145 {0x40048, 0xf00},
1146 {0x40068, 0x0},
1147 {0x40009, 0x720},
1148 {0x40029, 0xf},
1149 {0x40049, 0x1400},
1150 {0x40069, 0x0},
1151 {0x4000a, 0xe08},
1152 {0x4002a, 0xc15},
1153 {0x4004a, 0x0},
1154 {0x4006a, 0x0},
1155 {0x4000b, 0x625},
1156 {0x4002b, 0x15},
1157 {0x4004b, 0x0},
1158 {0x4006b, 0x0},
1159 {0x4000c, 0x4028},
1160 {0x4002c, 0x80},
1161 {0x4004c, 0x0},
1162 {0x4006c, 0x0},
1163 {0x4000d, 0xe08},
1164 {0x4002d, 0xc1a},
1165 {0x4004d, 0x0},
1166 {0x4006d, 0x0},
1167 {0x4000e, 0x625},
1168 {0x4002e, 0x1a},
1169 {0x4004e, 0x0},
1170 {0x4006e, 0x0},
1171 {0x4000f, 0x4040},
1172 {0x4002f, 0x80},
1173 {0x4004f, 0x0},
1174 {0x4006f, 0x0},
1175 {0x40010, 0x2604},
1176 {0x40030, 0x15},
1177 {0x40050, 0x0},
1178 {0x40070, 0x0},
1179 {0x40011, 0x708},
1180 {0x40031, 0x5},
1181 {0x40051, 0x0},
1182 {0x40071, 0x2002},
1183 {0x40012, 0x8},
1184 {0x40032, 0x80},
1185 {0x40052, 0x0},
1186 {0x40072, 0x0},
1187 {0x40013, 0x2604},
1188 {0x40033, 0x1a},
1189 {0x40053, 0x0},
1190 {0x40073, 0x0},
1191 {0x40014, 0x708},
1192 {0x40034, 0xa},
1193 {0x40054, 0x0},
1194 {0x40074, 0x2002},
1195 {0x40015, 0x4040},
1196 {0x40035, 0x80},
1197 {0x40055, 0x0},
1198 {0x40075, 0x0},
1199 {0x40016, 0x60a},
1200 {0x40036, 0x15},
1201 {0x40056, 0x1200},
1202 {0x40076, 0x0},
1203 {0x40017, 0x61a},
1204 {0x40037, 0x15},
1205 {0x40057, 0x1300},
1206 {0x40077, 0x0},
1207 {0x40018, 0x60a},
1208 {0x40038, 0x1a},
1209 {0x40058, 0x1200},
1210 {0x40078, 0x0},
1211 {0x40019, 0x642},
1212 {0x40039, 0x1a},
1213 {0x40059, 0x1300},
1214 {0x40079, 0x0},
1215 {0x4001a, 0x4808},
1216 {0x4003a, 0x880},
1217 {0x4005a, 0x0},
1218 {0x4007a, 0x0},
1219 {0x900a4, 0x0},
1220 {0x900a5, 0x790},
1221 {0x900a6, 0x11a},
1222 {0x900a7, 0x8},
1223 {0x900a8, 0x7aa},
1224 {0x900a9, 0x2a},
1225 {0x900aa, 0x10},
1226 {0x900ab, 0x7b2},
1227 {0x900ac, 0x2a},
1228 {0x900ad, 0x0},
1229 {0x900ae, 0x7c8},
1230 {0x900af, 0x109},
1231 {0x900b0, 0x10},
1232 {0x900b1, 0x10},
1233 {0x900b2, 0x109},
1234 {0x900b3, 0x10},
1235 {0x900b4, 0x2a8},
1236 {0x900b5, 0x129},
1237 {0x900b6, 0x8},
1238 {0x900b7, 0x370},
1239 {0x900b8, 0x129},
1240 {0x900b9, 0xa},
1241 {0x900ba, 0x3c8},
1242 {0x900bb, 0x1a9},
1243 {0x900bc, 0xc},
1244 {0x900bd, 0x408},
1245 {0x900be, 0x199},
1246 {0x900bf, 0x14},
1247 {0x900c0, 0x790},
1248 {0x900c1, 0x11a},
1249 {0x900c2, 0x8},
1250 {0x900c3, 0x4},
1251 {0x900c4, 0x18},
1252 {0x900c5, 0xe},
1253 {0x900c6, 0x408},
1254 {0x900c7, 0x199},
1255 {0x900c8, 0x8},
1256 {0x900c9, 0x8568},
1257 {0x900ca, 0x108},
1258 {0x900cb, 0x18},
1259 {0x900cc, 0x790},
1260 {0x900cd, 0x16a},
1261 {0x900ce, 0x8},
1262 {0x900cf, 0x1d8},
1263 {0x900d0, 0x169},
1264 {0x900d1, 0x10},
1265 {0x900d2, 0x8558},
1266 {0x900d3, 0x168},
1267 {0x900d4, 0x70},
1268 {0x900d5, 0x788},
1269 {0x900d6, 0x16a},
1270 {0x900d7, 0x1ff8},
1271 {0x900d8, 0x85a8},
1272 {0x900d9, 0x1e8},
1273 {0x900da, 0x50},
1274 {0x900db, 0x798},
1275 {0x900dc, 0x16a},
1276 {0x900dd, 0x60},
1277 {0x900de, 0x7a0},
1278 {0x900df, 0x16a},
1279 {0x900e0, 0x8},
1280 {0x900e1, 0x8310},
1281 {0x900e2, 0x168},
1282 {0x900e3, 0x8},
1283 {0x900e4, 0xa310},
1284 {0x900e5, 0x168},
1285 {0x900e6, 0xa},
1286 {0x900e7, 0x408},
1287 {0x900e8, 0x169},
1288 {0x900e9, 0x6e},
1289 {0x900ea, 0x0},
1290 {0x900eb, 0x68},
1291 {0x900ec, 0x0},
1292 {0x900ed, 0x408},
1293 {0x900ee, 0x169},
1294 {0x900ef, 0x0},
1295 {0x900f0, 0x8310},
1296 {0x900f1, 0x168},
1297 {0x900f2, 0x0},
1298 {0x900f3, 0xa310},
1299 {0x900f4, 0x168},
1300 {0x900f5, 0x1ff8},
1301 {0x900f6, 0x85a8},
1302 {0x900f7, 0x1e8},
1303 {0x900f8, 0x68},
1304 {0x900f9, 0x798},
1305 {0x900fa, 0x16a},
1306 {0x900fb, 0x78},
1307 {0x900fc, 0x7a0},
1308 {0x900fd, 0x16a},
1309 {0x900fe, 0x68},
1310 {0x900ff, 0x790},
1311 {0x90100, 0x16a},
1312 {0x90101, 0x8},
1313 {0x90102, 0x8b10},
1314 {0x90103, 0x168},
1315 {0x90104, 0x8},
1316 {0x90105, 0xab10},
1317 {0x90106, 0x168},
1318 {0x90107, 0xa},
1319 {0x90108, 0x408},
1320 {0x90109, 0x169},
1321 {0x9010a, 0x58},
1322 {0x9010b, 0x0},
1323 {0x9010c, 0x68},
1324 {0x9010d, 0x0},
1325 {0x9010e, 0x408},
1326 {0x9010f, 0x169},
1327 {0x90110, 0x0},
1328 {0x90111, 0x8b10},
1329 {0x90112, 0x168},
1330 {0x90113, 0x1},
1331 {0x90114, 0xab10},
1332 {0x90115, 0x168},
1333 {0x90116, 0x0},
1334 {0x90117, 0x1d8},
1335 {0x90118, 0x169},
1336 {0x90119, 0x80},
1337 {0x9011a, 0x790},
1338 {0x9011b, 0x16a},
1339 {0x9011c, 0x18},
1340 {0x9011d, 0x7aa},
1341 {0x9011e, 0x6a},
1342 {0x9011f, 0xa},
1343 {0x90120, 0x0},
1344 {0x90121, 0x1e9},
1345 {0x90122, 0x8},
1346 {0x90123, 0x8080},
1347 {0x90124, 0x108},
1348 {0x90125, 0xf},
1349 {0x90126, 0x408},
1350 {0x90127, 0x169},
1351 {0x90128, 0xc},
1352 {0x90129, 0x0},
1353 {0x9012a, 0x68},
1354 {0x9012b, 0x9},
1355 {0x9012c, 0x0},
1356 {0x9012d, 0x1a9},
1357 {0x9012e, 0x0},
1358 {0x9012f, 0x408},
1359 {0x90130, 0x169},
1360 {0x90131, 0x0},
1361 {0x90132, 0x8080},
1362 {0x90133, 0x108},
1363 {0x90134, 0x8},
1364 {0x90135, 0x7aa},
1365 {0x90136, 0x6a},
1366 {0x90137, 0x0},
1367 {0x90138, 0x8568},
1368 {0x90139, 0x108},
1369 {0x9013a, 0xb7},
1370 {0x9013b, 0x790},
1371 {0x9013c, 0x16a},
1372 {0x9013d, 0x1f},
1373 {0x9013e, 0x0},
1374 {0x9013f, 0x68},
1375 {0x90140, 0x8},
1376 {0x90141, 0x8558},
1377 {0x90142, 0x168},
1378 {0x90143, 0xf},
1379 {0x90144, 0x408},
1380 {0x90145, 0x169},
1381 {0x90146, 0xd},
1382 {0x90147, 0x0},
1383 {0x90148, 0x68},
1384 {0x90149, 0x0},
1385 {0x9014a, 0x408},
1386 {0x9014b, 0x169},
1387 {0x9014c, 0x0},
1388 {0x9014d, 0x8558},
1389 {0x9014e, 0x168},
1390 {0x9014f, 0x8},
1391 {0x90150, 0x3c8},
1392 {0x90151, 0x1a9},
1393 {0x90152, 0x3},
1394 {0x90153, 0x370},
1395 {0x90154, 0x129},
1396 {0x90155, 0x20},
1397 {0x90156, 0x2aa},
1398 {0x90157, 0x9},
1399 {0x90158, 0x0},
1400 {0x90159, 0x400},
1401 {0x9015a, 0x10e},
1402 {0x9015b, 0x8},
1403 {0x9015c, 0xe8},
1404 {0x9015d, 0x109},
1405 {0x9015e, 0x0},
1406 {0x9015f, 0x8140},
1407 {0x90160, 0x10c},
1408 {0x90161, 0x10},
1409 {0x90162, 0x8138},
1410 {0x90163, 0x10c},
1411 {0x90164, 0x8},
1412 {0x90165, 0x7c8},
1413 {0x90166, 0x101},
1414 {0x90167, 0x8},
1415 {0x90168, 0x448},
1416 {0x90169, 0x109},
1417 {0x9016a, 0xf},
1418 {0x9016b, 0x7c0},
1419 {0x9016c, 0x109},
1420 {0x9016d, 0x0},
1421 {0x9016e, 0xe8},
1422 {0x9016f, 0x109},
1423 {0x90170, 0x47},
1424 {0x90171, 0x630},
1425 {0x90172, 0x109},
1426 {0x90173, 0x8},
1427 {0x90174, 0x618},
1428 {0x90175, 0x109},
1429 {0x90176, 0x8},
1430 {0x90177, 0xe0},
1431 {0x90178, 0x109},
1432 {0x90179, 0x0},
1433 {0x9017a, 0x7c8},
1434 {0x9017b, 0x109},
1435 {0x9017c, 0x8},
1436 {0x9017d, 0x8140},
1437 {0x9017e, 0x10c},
1438 {0x9017f, 0x0},
1439 {0x90180, 0x1},
1440 {0x90181, 0x8},
1441 {0x90182, 0x8},
1442 {0x90183, 0x4},
1443 {0x90184, 0x8},
1444 {0x90185, 0x8},
1445 {0x90186, 0x7c8},
1446 {0x90187, 0x101},
1447 {0x90006, 0x0},
1448 {0x90007, 0x0},
1449 {0x90008, 0x8},
1450 {0x90009, 0x0},
1451 {0x9000a, 0x0},
1452 {0x9000b, 0x0},
1453 {0xd00e7, 0x400},
1454 {0x90017, 0x0},
1455 {0x9001f, 0x29},
1456 {0x90026, 0x6a},
1457 {0x400d0, 0x0},
1458 {0x400d1, 0x101},
1459 {0x400d2, 0x105},
1460 {0x400d3, 0x107},
1461 {0x400d4, 0x10f},
1462 {0x400d5, 0x202},
1463 {0x400d6, 0x20a},
1464 {0x400d7, 0x20b},
1465 {0x2003a, 0x2},
1466 {0x2000b, 0x64},
1467 {0x2000c, 0xc8},
1468 {0x2000d, 0x7d0},
1469 {0x2000e, 0x2c},
1470 {0x12000b, 0xc},
1471 {0x12000c, 0x19},
1472 {0x12000d, 0xfa},
1473 {0x12000e, 0x10},
1474 {0x22000b, 0x3},
1475 {0x22000c, 0x6},
1476 {0x22000d, 0x3e},
1477 {0x22000e, 0x10},
1478 {0x9000c, 0x0},
1479 {0x9000d, 0x173},
1480 {0x9000e, 0x60},
1481 {0x9000f, 0x6110},
1482 {0x90010, 0x2152},
1483 {0x90011, 0xdfbd},
1484 {0x90012, 0x2060},
1485 {0x90013, 0x6152},
1486 {0x20010, 0x5a},
1487 {0x20011, 0x3},
1488 {0x40080, 0xe0},
1489 {0x40081, 0x12},
1490 {0x40082, 0xe0},
1491 {0x40083, 0x12},
1492 {0x40084, 0xe0},
1493 {0x40085, 0x12},
1494 {0x140080, 0xe0},
1495 {0x140081, 0x12},
1496 {0x140082, 0xe0},
1497 {0x140083, 0x12},
1498 {0x140084, 0xe0},
1499 {0x140085, 0x12},
1500 {0x240080, 0xe0},
1501 {0x240081, 0x12},
1502 {0x240082, 0xe0},
1503 {0x240083, 0x12},
1504 {0x240084, 0xe0},
1505 {0x240085, 0x12},
1506 {0x400fd, 0xf},
1507 {0x10011, 0x1},
1508 {0x10012, 0x1},
1509 {0x10013, 0x180},
1510 {0x10018, 0x1},
1511 {0x10002, 0x6209},
1512 {0x100b2, 0x1},
1513 {0x101b4, 0x1},
1514 {0x102b4, 0x1},
1515 {0x103b4, 0x1},
1516 {0x104b4, 0x1},
1517 {0x105b4, 0x1},
1518 {0x106b4, 0x1},
1519 {0x107b4, 0x1},
1520 {0x108b4, 0x1},
1521 {0x11011, 0x1},
1522 {0x11012, 0x1},
1523 {0x11013, 0x180},
1524 {0x11018, 0x1},
1525 {0x11002, 0x6209},
1526 {0x110b2, 0x1},
1527 {0x111b4, 0x1},
1528 {0x112b4, 0x1},
1529 {0x113b4, 0x1},
1530 {0x114b4, 0x1},
1531 {0x115b4, 0x1},
1532 {0x116b4, 0x1},
1533 {0x117b4, 0x1},
1534 {0x118b4, 0x1},
1535 {0x20089, 0x1},
1536 {0x20088, 0x19},
1537 {0xc0080, 0x2},
1538 {0xd0000, 0x1},
1539 };
1540
1541 struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1542 {
1543 /* P0 3200mts 1D */
1544 .drate = 3200,
1545 .fw_type = FW_1D_IMAGE,
1546 .fsp_cfg = ddr_fsp0_cfg,
1547 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1548 },
1549 {
1550 /* P1 400mts 1D */
1551 .drate = 400,
1552 .fw_type = FW_1D_IMAGE,
1553 .fsp_cfg = ddr_fsp1_cfg,
1554 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1555 },
1556 {
1557 /* P2 100mts 1D */
1558 .drate = 100,
1559 .fw_type = FW_1D_IMAGE,
1560 .fsp_cfg = ddr_fsp2_cfg,
1561 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
1562 },
1563 {
1564 /* P0 3200mts 2D */
1565 .drate = 3200,
1566 .fw_type = FW_2D_IMAGE,
1567 .fsp_cfg = ddr_fsp0_2d_cfg,
1568 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1569 },
1570 };
1571
1572 /* ddr timing config params */
1573 struct dram_timing_info dram_timing = {
1574 .ddrc_cfg = ddr_ddrc_cfg,
1575 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1576 .ddrphy_cfg = ddr_ddrphy_cfg,
1577 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1578 .fsp_msg = ddr_dram_fsp_msg,
1579 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1580 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1581 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1582 .ddrphy_pie = ddr_phy_pie,
1583 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1584 .fsp_table = { 3200, 400, 100, },
1585 };
1586
board/freescale/imx8mm_ab2/spl.c
Diff comments   View file @ 5187303
1 /* 1 /*
2 * Copyright 2020 NXP 2 * Copyright 2020 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <cpu_func.h> 8 #include <cpu_func.h>
9 #include <hang.h> 9 #include <hang.h>
10 #include <spl.h> 10 #include <spl.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <errno.h> 12 #include <errno.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <asm/mach-imx/iomux-v3.h> 14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h> 16 #include <asm/mach-imx/boot_mode.h>
17 #include <power/pmic.h> 17 #include <power/pmic.h>
18 #include <asm/arch/clock.h> 18 #include <asm/arch/clock.h>
19 #include <asm/mach-imx/gpio.h> 19 #include <asm/mach-imx/gpio.h>
20 #include <asm/mach-imx/mxc_i2c.h> 20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <fsl_esdhc_imx.h> 21 #include <fsl_esdhc_imx.h>
22 #include <mmc.h> 22 #include <mmc.h>
23 #include <asm/arch/ddr.h> 23 #include <asm/arch/ddr.h>
24 24
25 #ifdef CONFIG_TARGET_IMX8MM_AB2 25 #ifdef CONFIG_TARGET_IMX8MM_AB2
26 #include <asm/arch/imx8mm_pins.h> 26 #include <asm/arch/imx8mm_pins.h>
27 #else
28 #include <asm/arch/imx8mn_pins.h>
27 #endif 29 #endif
28 30
29 #ifdef CONFIG_POWER_PCA9450 31 #ifdef CONFIG_POWER_PCA9450
30 #include <power/pca9450.h> 32 #include <power/pca9450.h>
31 #else 33 #else
32 #include <power/bd71837.h> 34 #include <power/bd71837.h>
33 #endif 35 #endif
34 36
35 DECLARE_GLOBAL_DATA_PTR; 37 DECLARE_GLOBAL_DATA_PTR;
36 38
37 int spl_board_boot_device(enum boot_device boot_dev_spl) 39 int spl_board_boot_device(enum boot_device boot_dev_spl)
38 { 40 {
41 #ifdef CONFIG_TARGET_IMX8MM_AB2
39 switch (boot_dev_spl) { 42 switch (boot_dev_spl) {
40 case SD2_BOOT: 43 case SD2_BOOT:
41 case MMC2_BOOT: 44 case MMC2_BOOT:
42 return BOOT_DEVICE_MMC1; 45 return BOOT_DEVICE_MMC1;
43 case SD3_BOOT: 46 case SD3_BOOT:
44 case MMC3_BOOT: 47 case MMC3_BOOT:
45 return BOOT_DEVICE_MMC2; 48 return BOOT_DEVICE_MMC2;
46 case QSPI_BOOT: 49 case QSPI_BOOT:
47 return BOOT_DEVICE_NOR; 50 return BOOT_DEVICE_NOR;
48 case NAND_BOOT: 51 case NAND_BOOT:
49 return BOOT_DEVICE_NAND; 52 return BOOT_DEVICE_NAND;
50 case USB_BOOT: 53 case USB_BOOT:
51 return BOOT_DEVICE_NONE; 54 return BOOT_DEVICE_NONE;
52 default: 55 default:
53 return BOOT_DEVICE_NONE; 56 return BOOT_DEVICE_NONE;
54 } 57 }
58 #else
59 return BOOT_DEVICE_BOOTROM;
60 #endif
55 } 61 }
56 62
57 void spl_dram_init(void) 63 void spl_dram_init(void)
58 { 64 {
59 ddr_init(&dram_timing); 65 ddr_init(&dram_timing);
60 } 66 }
61 67
62 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) 68 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
63 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 69 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
64 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ 70 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
65 PAD_CTL_FSEL2) 71 PAD_CTL_FSEL2)
66 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) 72 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
67 #define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4) 73 #define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4)
68 74
69 #ifdef CONFIG_TARGET_IMX8MM_AB2 75 #ifdef CONFIG_TARGET_IMX8MM_AB2
70 struct i2c_pads_info i2c_pad_info1 = { 76 struct i2c_pads_info i2c_pad_info1 = {
71 .scl = { 77 .scl = {
72 .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, 78 .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
73 .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, 79 .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
74 .gp = IMX_GPIO_NR(5, 14), 80 .gp = IMX_GPIO_NR(5, 14),
75 }, 81 },
76 .sda = { 82 .sda = {
77 .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, 83 .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
78 .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, 84 .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
79 .gp = IMX_GPIO_NR(5, 15), 85 .gp = IMX_GPIO_NR(5, 15),
80 }, 86 },
81 }; 87 };
82 #endif 88 #endif
83 89
90 #if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2)
91 struct i2c_pads_info i2c_pad_info1 = {
92 .scl = {
93 .i2c_mode = IMX8MN_PAD_I2C1_SCL__I2C1_SCL | PC,
94 .gpio_mode = IMX8MN_PAD_I2C1_SCL__GPIO5_IO14 | PC,
95 .gp = IMX_GPIO_NR(5, 14),
96 },
97 .sda = {
98 .i2c_mode = IMX8MN_PAD_I2C1_SDA__I2C1_SDA | PC,
99 .gpio_mode = IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 | PC,
100 .gp = IMX_GPIO_NR(5, 15),
101 },
102 };
103 #endif
104
84 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) 105 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
85 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) 106 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
86 107
87 #ifdef CONFIG_TARGET_IMX8MM_AB2 108 #ifdef CONFIG_TARGET_IMX8MM_AB2
88 static iomux_v3_cfg_t const usdhc3_pads[] = { 109 static iomux_v3_cfg_t const usdhc3_pads[] = {
89 IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110 IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 111 IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112 IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113 IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114 IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 115 IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116 IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117 IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 }; 120 };
100 121
101 static iomux_v3_cfg_t const usdhc2_pads[] = { 122 static iomux_v3_cfg_t const usdhc2_pads[] = {
102 IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 128 IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 129 IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
109 IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), 130 IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
110 }; 131 };
111 #endif 132 #endif
112 133
134 #if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2)
135 static iomux_v3_cfg_t const usdhc3_pads[] = {
136 IMX8MN_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 IMX8MN_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 IMX8MN_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 IMX8MN_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 IMX8MN_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 IMX8MN_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 IMX8MN_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 IMX8MN_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 };
147
148 static iomux_v3_cfg_t const usdhc2_pads[] = {
149 IMX8MN_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 IMX8MN_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 IMX8MN_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 IMX8MN_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 IMX8MN_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
156 IMX8MN_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
157 };
158 #endif
159
113 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 160 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
114 {USDHC2_BASE_ADDR, 0, 4}, 161 {USDHC2_BASE_ADDR, 0, 4},
115 {USDHC3_BASE_ADDR, 0, 8}, 162 {USDHC3_BASE_ADDR, 0, 8},
116 }; 163 };
117 164
118 int board_mmc_init(bd_t *bis) 165 int board_mmc_init(bd_t *bis)
119 { 166 {
120 int i, ret; 167 int i, ret;
121 /* 168 /*
122 * According to the board_mmc_init() the following map is done: 169 * According to the board_mmc_init() the following map is done:
123 * (U-Boot device node) (Physical Port) 170 * (U-Boot device node) (Physical Port)
124 * mmc0 USDHC1 171 * mmc0 USDHC1
125 * mmc1 USDHC2 172 * mmc1 USDHC2
126 */ 173 */
127 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 174 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
128 switch (i) { 175 switch (i) {
129 case 0: 176 case 0:
130 init_clk_usdhc(1); 177 init_clk_usdhc(1);
131 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 178 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
132 imx_iomux_v3_setup_multiple_pads( 179 imx_iomux_v3_setup_multiple_pads(
133 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 180 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
134 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); 181 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
135 gpio_direction_output(USDHC2_PWR_GPIO, 0); 182 gpio_direction_output(USDHC2_PWR_GPIO, 0);
136 udelay(500); 183 udelay(500);
137 gpio_direction_output(USDHC2_PWR_GPIO, 1); 184 gpio_direction_output(USDHC2_PWR_GPIO, 1);
138 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); 185 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
139 gpio_direction_input(USDHC2_CD_GPIO); 186 gpio_direction_input(USDHC2_CD_GPIO);
140 break; 187 break;
141 case 1: 188 case 1:
142 init_clk_usdhc(2); 189 init_clk_usdhc(2);
143 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 190 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
144 imx_iomux_v3_setup_multiple_pads( 191 imx_iomux_v3_setup_multiple_pads(
145 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 192 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
146 break; 193 break;
147 default: 194 default:
148 printf("Warning: you configured more USDHC controllers" 195 printf("Warning: you configured more USDHC controllers"
149 "(%d) than supported by the board\n", i + 1); 196 "(%d) than supported by the board\n", i + 1);
150 return -EINVAL; 197 return -EINVAL;
151 } 198 }
152 199
153 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 200 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
154 if (ret) 201 if (ret)
155 return ret; 202 return ret;
156 } 203 }
157 204
158 return 0; 205 return 0;
159 } 206 }
160 207
161 int board_mmc_getcd(struct mmc *mmc) 208 int board_mmc_getcd(struct mmc *mmc)
162 { 209 {
163 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 210 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
164 int ret = 0; 211 int ret = 0;
165 212
166 switch (cfg->esdhc_base) { 213 switch (cfg->esdhc_base) {
167 case USDHC3_BASE_ADDR: 214 case USDHC3_BASE_ADDR:
168 ret = 1; 215 ret = 1;
169 break; 216 break;
170 case USDHC2_BASE_ADDR: 217 case USDHC2_BASE_ADDR:
171 ret = !gpio_get_value(USDHC2_CD_GPIO); 218 ret = !gpio_get_value(USDHC2_CD_GPIO);
172 return ret; 219 return ret;
173 } 220 }
174 221
175 return 1; 222 return 1;
176 } 223 }
177 224
178 #ifdef CONFIG_POWER 225 #ifdef CONFIG_POWER
179 #define I2C_PMIC 0 226 #define I2C_PMIC 0
227
228 #ifdef CONFIG_POWER_PCA9450
180 int power_init_board(void) 229 int power_init_board(void)
181 { 230 {
182 struct pmic *p; 231 struct pmic *p;
183 int ret; 232 int ret;
184 233
185 #ifdef CONFIG_POWER_PCA9450
186 ret = power_pca9450b_init(I2C_PMIC); 234 ret = power_pca9450b_init(I2C_PMIC);
187 if (ret) 235 if (ret)
188 printf("power init failed"); 236 printf("power init failed");
189 p = pmic_get("PCA9450"); 237 p = pmic_get("PCA9450");
190 pmic_probe(p); 238 pmic_probe(p);
191 239
192 /* BUCKxOUT_DVS0/1 control BUCK123 output */ 240 /* BUCKxOUT_DVS0/1 control BUCK123 output */
193 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); 241 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
194 242
195 /* 243 /*
196 * increase VDD_SOC to typical value 0.95V before first 244 * increase VDD_SOC to typical value 0.95V before first
197 * DRAM access, set DVS1 to 0.85v for suspend. 245 * DRAM access, set DVS1 to 0.85v for suspend.
198 * Enable DVS control through PMIC_STBY_REQ and 246 * Enable DVS control through PMIC_STBY_REQ and
199 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) 247 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
200 */ 248 */
201 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); 249 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
202 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); 250 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
203 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); 251 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
204 252
205 /* Kernel uses OD/OD freq for SOC */ 253 #if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2)
206 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ 254 /* set VDD_SNVS_0V8 from default 0.85V */
207 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); 255 pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0);
208 256 /* enable LDO4 to 1.2v */
257 pmic_reg_write(p, PCA9450_LDO4CTRL, 0x44);
258 #endif
209 /* set WDOG_B_CFG to cold reset */ 259 /* set WDOG_B_CFG to cold reset */
210 pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); 260 pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
211 261
212 #else 262 return 0;
263 }
264 #endif /* CONFIG_POWER_PCA9450 */
265
266 #ifdef CONFIG_POWER_BD71837
267 int power_init_board(void)
268 {
269 struct pmic *p;
270 int ret;
271
213 ret = power_bd71837_init(I2C_PMIC); 272 ret = power_bd71837_init(I2C_PMIC);
214 if (ret) 273 if (ret)
215 printf("power init failed"); 274 printf("power init failed");
216 p = pmic_get("BD71837"); 275 p = pmic_get("BD71837");
217 pmic_probe(p); 276 pmic_probe(p);
218 277
219 /* decrease RESET key long push time from the default 10s to 10ms */ 278 /* decrease RESET key long push time from the default 10s to 10ms */
220 pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); 279 pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
221 /* unlock the PMIC regs */ 280 /* unlock the PMIC regs */
222 pmic_reg_write(p, BD71837_REGLOCK, 0x1); 281 pmic_reg_write(p, BD71837_REGLOCK, 0x1);
282 #ifdef CONFIG_TARGET_IMX8MM_AB2
223 /* increase VDD_SOC to typical value 0.85v before first DRAM access */ 283 /* increase VDD_SOC to typical value 0.85v before first DRAM access */
224 pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); 284 pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);
225 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ 285 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
226 pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); 286 pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);
227 #ifndef CONFIG_IMX8M_LPDDR4 287 #ifdef CONFIG_IMX8M_DDR4
228 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ 288 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
229 pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); 289 pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
230 #endif 290 #endif
291 #endif /* CONFIG_TARGET_IMX8MM_AB2 */
292
293 #if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2)
294 /* Set VDD_ARM to typical value 0.85v for 1.2Ghz */
295 pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0xf);
296 #ifdef CONFIG_IMX8M_DDR4
297 /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */
298 pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0xf);
299 #endif
300 /* Set VDD_SOC 0.85v for suspend */
301 pmic_reg_write(p, BD71837_BUCK1_VOLT_SUSP, 0xf);
302 #ifdef CONFIG_IMX8M_DDR4
303 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
304 pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
305 #endif
306 #endif /* CONFIG_TARGET_IMX8MN_AB2 */
307
231 /* lock the PMIC regs */ 308 /* lock the PMIC regs */
232 pmic_reg_write(p, BD71837_REGLOCK, 0x11); 309 pmic_reg_write(p, BD71837_REGLOCK, 0x11);
233 #endif
234 310
235 return 0; 311 return 0;
236 } 312 }
237 #endif 313 #endif /* CONFIG_POWER_BD71837 */
314 #endif /* CONFIG_POWER */
238 315
239 void spl_board_init(void) 316 void spl_board_init(void)
240 { 317 {
241 #ifndef CONFIG_SPL_USB_SDP_SUPPORT 318 #ifndef CONFIG_SPL_USB_SDP_SUPPORT
242 #ifdef CONFIG_TARGET_IMX8MM_AB2 319 #ifdef CONFIG_TARGET_IMX8MM_AB2
243 /* Serial download mode */ 320 /* Serial download mode */
244 if (is_usb_boot()) { 321 if (is_usb_boot()) {
245 puts("Back to ROM, SDP\n"); 322 puts("Back to ROM, SDP\n");
246 restore_boot_params(); 323 restore_boot_params();
247 } 324 }
248 #endif 325 #endif
249 #endif 326 #endif
250 puts("Normal Boot\n"); 327 puts("Normal Boot\n");
251 } 328 }
252 329
253 #ifdef CONFIG_SPL_LOAD_FIT 330 #ifdef CONFIG_SPL_LOAD_FIT
254 int board_fit_config_name_match(const char *name) 331 int board_fit_config_name_match(const char *name)
255 { 332 {
256 /* Just empty function now - can't decide what to choose */ 333 /* Just empty function now - can't decide what to choose */
257 debug("%s: %s\n", __func__, name); 334 debug("%s: %s\n", __func__, name);
258 335
259 return 0; 336 return 0;
260 } 337 }
261 #endif 338 #endif
262 339
263 void board_init_f(ulong dummy) 340 void board_init_f(ulong dummy)
264 { 341 {
265 int ret; 342 int ret;
266 343
267 /* Clear the BSS. */ 344 /* Clear the BSS. */
268 memset(__bss_start, 0, __bss_end - __bss_start); 345 memset(__bss_start, 0, __bss_end - __bss_start);
269 346
270 arch_cpu_init(); 347 arch_cpu_init();
271 348
272 board_early_init_f(); 349 board_early_init_f();
273 350
274 timer_init(); 351 timer_init();
275 352
276 preloader_console_init(); 353 preloader_console_init();
277 354
278 ret = spl_init(); 355 ret = spl_init();
279 if (ret) { 356 if (ret) {
280 debug("spl_init() failed: %d\n", ret); 357 debug("spl_init() failed: %d\n", ret);
281 hang(); 358 hang();
282 } 359 }
283 360
284 enable_tzc380(); 361 enable_tzc380();
285 362
286 /* Adjust pmic voltage to 1.0V for 800M */ 363 /* Adjust pmic voltage to 1.0V for 800M */
287 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 364 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
288 365
289 power_init_board(); 366 power_init_board();
290 367
291 /* DDR initialization */ 368 /* DDR initialization */
292 spl_dram_init(); 369 spl_dram_init();
293 370
294 board_init_r(NULL, 0); 371 board_init_r(NULL, 0);
295 } 372 }
296 373
297 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 374 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
298 { 375 {
299 puts("resetting ...\n"); 376 puts("resetting ...\n");
300 377
301 reset_cpu(WDOG1_BASE_ADDR); 378 reset_cpu(WDOG1_BASE_ADDR);
302 379
303 return 0; 380 return 0;
configs/imx8mn_ab2_defconfig
Diff comments   View file @ 5187303
File was created 1 CONFIG_ARM=y
2 CONFIG_SPL_SYS_ICACHE_OFF=y
3 CONFIG_SPL_SYS_DCACHE_OFF=y
4 CONFIG_ARCH_IMX8M=y
5 CONFIG_SYS_TEXT_BASE=0x40200000
6 CONFIG_SPL_GPIO_SUPPORT=y
7 CONFIG_SPL_LIBCOMMON_SUPPORT=y
8 CONFIG_SPL_LIBGENERIC_SUPPORT=y
9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_SYS_I2C_MXC_I2C1=y
11 CONFIG_SYS_I2C_MXC_I2C2=y
12 CONFIG_SYS_I2C_MXC_I2C3=y
13 CONFIG_ENV_SIZE=0x1000
14 CONFIG_ENV_OFFSET=0x400000
15 CONFIG_ENV_SECT_SIZE=0x10000
16 CONFIG_DM_GPIO=y
17 CONFIG_TARGET_IMX8MN_AB2=y
18 CONFIG_ARCH_MISC_INIT=y
19 CONFIG_SPL_SERIAL_SUPPORT=y
20 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
21 CONFIG_SPL=y
22 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
23 CONFIG_CSF_SIZE=0x2000
24 CONFIG_SPL_TEXT_BASE=0x912000
25 CONFIG_FIT=y
26 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
27 CONFIG_SPL_LOAD_FIT=y
28 CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
29 CONFIG_OF_SYSTEM_SETUP=y
30 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
31 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ab2"
32 CONFIG_DEFAULT_FDT_FILE="imx8mn-ab2.dtb"
33 CONFIG_BOARD_LATE_INIT=y
34 CONFIG_BOARD_EARLY_INIT_F=y
35 CONFIG_SPL_BOARD_INIT=y
36 CONFIG_SPL_BOOTROM_SUPPORT=y
37 CONFIG_SPL_SEPARATE_BSS=y
38 CONFIG_SPL_I2C_SUPPORT=y
39 CONFIG_SPL_POWER_SUPPORT=y
40 CONFIG_NR_DRAM_BANKS=2
41 CONFIG_HUSH_PARSER=y
42 CONFIG_SYS_PROMPT="u-boot=> "
43 # CONFIG_CMD_EXPORTENV is not set
44 # CONFIG_CMD_IMPORTENV is not set
45 CONFIG_CMD_ERASEENV=y
46 # CONFIG_CMD_CRC32 is not set
47 # CONFIG_BOOTM_NETBSD is not set
48 CONFIG_CMD_CLK=y
49 CONFIG_CMD_FUSE=y
50 CONFIG_CMD_GPIO=y
51 CONFIG_CMD_I2C=y
52 CONFIG_CMD_MMC=y
53 CONFIG_CMD_DHCP=y
54 CONFIG_CMD_MII=y
55 CONFIG_CMD_PING=y
56 CONFIG_CMD_CACHE=y
57 CONFIG_CMD_REGULATOR=y
58 CONFIG_CMD_MEMTEST=y
59 CONFIG_CMD_EXT2=y
60 CONFIG_CMD_EXT4=y
61 CONFIG_CMD_EXT4_WRITE=y
62 CONFIG_CMD_FAT=y
63 CONFIG_CMD_SF=y
64 CONFIG_OF_CONTROL=y
65 CONFIG_ENV_IS_IN_MMC=y
66 CONFIG_ENV_IS_IN_SPI_FLASH=y
67 CONFIG_ENV_IS_NOWHERE=y
68 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
69 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
70 CONFIG_CLK_COMPOSITE_CCF=y
71 CONFIG_CLK_IMX8MN=y
72 CONFIG_MXC_GPIO=y
73
74 CONFIG_DM_I2C=y
75 CONFIG_SYS_I2C_MXC=y
76 CONFIG_DM_MMC=y
77 CONFIG_MMC_IO_VOLTAGE=y
78 CONFIG_MMC_UHS_SUPPORT=y
79 CONFIG_MMC_HS400_SUPPORT=y
80 CONFIG_MMC_HS400_ES_SUPPORT=y
81 CONFIG_EFI_PARTITION=y
82 CONFIG_SUPPORT_EMMC_BOOT=y
83 CONFIG_FSL_ESDHC_IMX=y
84 CONFIG_DM_SPI_FLASH=y
85 CONFIG_DM_SPI=y
86 CONFIG_FSL_FSPI=y
87 CONFIG_SPI=y
88 CONFIG_SPI_FLASH=y
89 CONFIG_SPI_FLASH_BAR=y
90 CONFIG_SPI_FLASH_STMICRO=y
91 CONFIG_SF_DEFAULT_BUS=0
92 CONFIG_SF_DEFAULT_CS=0
93 CONFIG_SF_DEFAULT_SPEED=40000000
94 CONFIG_SF_DEFAULT_MODE=0
95
96 CONFIG_PHYLIB=y
97 CONFIG_PHY_REALTEK=y
98 CONFIG_DM_ETH=y
99 CONFIG_PHY_GIGE=y
100 CONFIG_FEC_MXC=y
101 CONFIG_MII=y
102 CONFIG_PINCTRL=y
103 CONFIG_PINCTRL_IMX8M=y
104 CONFIG_DM_REGULATOR=y
105 CONFIG_DM_REGULATOR_FIXED=y
106 CONFIG_DM_REGULATOR_GPIO=y
107 CONFIG_MXC_UART=y
108 CONFIG_SYSRESET=y
109 CONFIG_SYSRESET_PSCI=y
110 CONFIG_DM_THERMAL=y
111 CONFIG_NXP_TMU=y
112
113 CONFIG_OF_LIBFDT_OVERLAY=y
114
configs/imx8mn_ddr4_ab2_defconfig
Diff comments   View file @ 5187303
File was created 1 CONFIG_ARM=y
2 CONFIG_SPL_SYS_ICACHE_OFF=y
3 CONFIG_SPL_SYS_DCACHE_OFF=y
4 CONFIG_ARCH_IMX8M=y
5 CONFIG_SYS_TEXT_BASE=0x40200000
6 CONFIG_SPL_GPIO_SUPPORT=y
7 CONFIG_SPL_LIBCOMMON_SUPPORT=y
8 CONFIG_SPL_LIBGENERIC_SUPPORT=y
9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_SYS_I2C_MXC_I2C1=y
11 CONFIG_SYS_I2C_MXC_I2C2=y
12 CONFIG_SYS_I2C_MXC_I2C3=y
13 CONFIG_ENV_SIZE=0x1000
14 CONFIG_ENV_OFFSET=0x400000
15 CONFIG_ENV_SECT_SIZE=0x10000
16 CONFIG_DM_GPIO=y
17 CONFIG_TARGET_IMX8MN_DDR4_AB2=y
18 CONFIG_ARCH_MISC_INIT=y
19 CONFIG_SPL_SERIAL_SUPPORT=y
20 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
21 CONFIG_SPL=y
22 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
23 CONFIG_CSF_SIZE=0x2000
24 CONFIG_SPL_TEXT_BASE=0x912000
25 CONFIG_FIT=y
26 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
27 CONFIG_SPL_LOAD_FIT=y
28 CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
29 CONFIG_OF_SYSTEM_SETUP=y
30 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg"
31 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-ab2"
32 CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-ab2.dtb"
33 CONFIG_BOARD_LATE_INIT=y
34 CONFIG_BOARD_EARLY_INIT_F=y
35 CONFIG_SPL_BOARD_INIT=y
36 CONFIG_SPL_BOOTROM_SUPPORT=y
37 CONFIG_SPL_SEPARATE_BSS=y
38 CONFIG_SPL_I2C_SUPPORT=y
39 CONFIG_SPL_POWER_SUPPORT=y
40 CONFIG_NR_DRAM_BANKS=2
41 CONFIG_HUSH_PARSER=y
42 CONFIG_SYS_PROMPT="u-boot=> "
43 # CONFIG_CMD_EXPORTENV is not set
44 # CONFIG_CMD_IMPORTENV is not set
45 CONFIG_CMD_ERASEENV=y
46 # CONFIG_CMD_CRC32 is not set
47 # CONFIG_BOOTM_NETBSD is not set
48 CONFIG_CMD_CLK=y
49 CONFIG_CMD_FUSE=y
50 CONFIG_CMD_GPIO=y
51 CONFIG_CMD_I2C=y
52 CONFIG_CMD_MMC=y
53 CONFIG_CMD_DHCP=y
54 CONFIG_CMD_MII=y
55 CONFIG_CMD_PING=y
56 CONFIG_CMD_CACHE=y
57 CONFIG_CMD_REGULATOR=y
58 CONFIG_CMD_MEMTEST=y
59 CONFIG_CMD_EXT2=y
60 CONFIG_CMD_EXT4=y
61 CONFIG_CMD_EXT4_WRITE=y
62 CONFIG_CMD_FAT=y
63 CONFIG_CMD_SF=y
64 CONFIG_OF_CONTROL=y
65 CONFIG_ENV_IS_IN_MMC=y
66 CONFIG_ENV_IS_IN_SPI_FLASH=y
67 CONFIG_ENV_IS_NOWHERE=y
68 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
69 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
70 CONFIG_CLK_COMPOSITE_CCF=y
71 CONFIG_CLK_IMX8MN=y
72 CONFIG_MXC_GPIO=y
73
74 CONFIG_DM_I2C=y
75 CONFIG_SYS_I2C_MXC=y
76 CONFIG_DM_MMC=y
77 CONFIG_MMC_IO_VOLTAGE=y
78 CONFIG_MMC_UHS_SUPPORT=y
79 CONFIG_MMC_HS400_SUPPORT=y
80 CONFIG_MMC_HS400_ES_SUPPORT=y
81 CONFIG_EFI_PARTITION=y
82 CONFIG_SUPPORT_EMMC_BOOT=y
83 CONFIG_FSL_ESDHC_IMX=y
84 CONFIG_DM_SPI_FLASH=y
85 CONFIG_DM_SPI=y
86 CONFIG_FSL_FSPI=y
87 CONFIG_SPI=y
88 CONFIG_SPI_FLASH=y
89 CONFIG_SPI_FLASH_BAR=y
90 CONFIG_SPI_FLASH_STMICRO=y
91 CONFIG_SF_DEFAULT_BUS=0
92 CONFIG_SF_DEFAULT_CS=0
93 CONFIG_SF_DEFAULT_SPEED=40000000
94 CONFIG_SF_DEFAULT_MODE=0
95
96 CONFIG_PHYLIB=y
97 CONFIG_PHY_REALTEK=y
98 CONFIG_DM_ETH=y
99 CONFIG_PHY_GIGE=y
100 CONFIG_FEC_MXC=y
101 CONFIG_MII=y
102 CONFIG_PINCTRL=y
103 CONFIG_PINCTRL_IMX8M=y
104 CONFIG_DM_REGULATOR=y
105 CONFIG_DM_REGULATOR_FIXED=y
106 CONFIG_DM_REGULATOR_GPIO=y
107 CONFIG_MXC_UART=y
108 CONFIG_SYSRESET=y
109 CONFIG_SYSRESET_PSCI=y
110 CONFIG_DM_THERMAL=y
111 CONFIG_NXP_TMU=y
112
113 CONFIG_OF_LIBFDT_OVERLAY=y
114
include/configs/imx8mn_ab2.h
Diff comments   View file @ 5187303
File was created 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2020 NXP
4 */
5
6 #ifndef __IMX8MN_AB2_H
7 #define __IMX8MN_AB2_H
8
9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h>
11
12 #include "imx_env.h"
13
14 #define CONFIG_SPL_MAX_SIZE (208 * 1024)
15 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
18 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
19 #define CONFIG_SYS_UBOOT_BASE \
20 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
21
22 #ifdef CONFIG_SPL_BUILD
23 #define CONFIG_SPL_STACK 0x187FF0
24 #define CONFIG_SPL_BSS_START_ADDR 0x0095e000
25 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
26 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
27 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_64K /* 64 KB */
28
29 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
30 #define CONFIG_MALLOC_F_ADDR 0x184000
31
32 /* For RAW image gives a error info not panic */
33 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
34
35 #define CONFIG_POWER
36 #define CONFIG_POWER_I2C
37 #ifdef CONFIG_IMX8M_DDR4
38 #define CONFIG_POWER_BD71837
39 #else
40 #define CONFIG_POWER_PCA9450
41 #endif
42
43 #define CONFIG_SYS_I2C
44
45 #if defined(CONFIG_NAND_BOOT)
46 #define CONFIG_SPL_NAND_SUPPORT
47 #define CONFIG_SPL_DMA
48 #define CONFIG_SPL_NAND_MXS
49 #define CONFIG_SPL_NAND_BASE
50 #define CONFIG_SPL_NAND_IDENT
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
52
53 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
54 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
55 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
56 #endif
57
58 #endif
59
60 #define CONFIG_CMD_READ
61 #define CONFIG_SERIAL_TAG
62
63 #define CONFIG_REMAKE_ELF
64 /* ENET Config */
65 /* ENET1 */
66 #if defined(CONFIG_FEC_MXC)
67 #define CONFIG_ETHPRIME "eth0"
68
69 #define CONFIG_FEC_XCV_TYPE RGMII
70 #define CONFIG_FEC_MXC_PHYADDR 1
71 #define FEC_QUIRK_ENET_MAC
72
73 #define IMX_FEC_BASE 0x30BE0000
74 #endif
75
76
77 /*
78 * Another approach is add the clocks for inmates into clks_init_on
79 * in clk-imx8mm.c, then clk_ingore_unused could be removed.
80 */
81 #define JAILHOUSE_ENV \
82 "jh_clk= \0 " \
83 "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file imx8mn-ddr4-ab2-root.dtb;" \
84 "setenv jh_clk clk_ignore_unused; " \
85 "if run loadimage; then " \
86 "run mmcboot; " \
87 "else run jh_netboot; fi; \0" \
88 "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file imx8mn-ddr4-ab2-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
89
90 #define CONFIG_MFG_ENV_SETTINGS \
91 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
92 "initrd_addr=0x43800000\0" \
93 "initrd_high=0xffffffffffffffff\0" \
94 "emmc_dev=2\0"\
95 "sd_dev=1\0" \
96
97 /* Initial environment variables */
98 #define CONFIG_EXTRA_ENV_SETTINGS \
99 CONFIG_MFG_ENV_SETTINGS \
100 JAILHOUSE_ENV \
101 "script=boot.scr\0" \
102 "image=Image\0" \
103 "console=ttymxc1,115200\0" \
104 "fdt_addr=0x43000000\0" \
105 "fdt_high=0xffffffffffffffff\0" \
106 "boot_fit=no\0" \
107 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
108 "initrd_addr=0x43800000\0" \
109 "initrd_high=0xffffffffffffffff\0" \
110 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
111 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
112 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
113 "mmcautodetect=yes\0" \
114 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
115 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
116 "bootscript=echo Running bootscript from mmc ...; " \
117 "source\0" \
118 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
119 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
120 "mmcboot=echo Booting from mmc ...; " \
121 "run mmcargs; " \
122 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
123 "bootm ${loadaddr}; " \
124 "else " \
125 "if run loadfdt; then " \
126 "booti ${loadaddr} - ${fdt_addr}; " \
127 "else " \
128 "echo WARN: Cannot load the DT; " \
129 "fi; " \
130 "fi;\0" \
131 "netargs=setenv bootargs ${jh_clk} console=${console} " \
132 "root=/dev/nfs " \
133 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
134 "netboot=echo Booting from net ...; " \
135 "run netargs; " \
136 "if test ${ip_dyn} = yes; then " \
137 "setenv get_cmd dhcp; " \
138 "else " \
139 "setenv get_cmd tftp; " \
140 "fi; " \
141 "${get_cmd} ${loadaddr} ${image}; " \
142 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
143 "bootm ${loadaddr}; " \
144 "else " \
145 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
146 "booti ${loadaddr} - ${fdt_addr}; " \
147 "else " \
148 "echo WARN: Cannot load the DT; " \
149 "fi; " \
150 "fi;\0"
151
152 #define CONFIG_BOOTCOMMAND \
153 "mmc dev ${mmcdev}; if mmc rescan; then " \
154 "if run loadbootscript; then " \
155 "run bootscript; " \
156 "else " \
157 "if run loadimage; then " \
158 "run mmcboot; " \
159 "else run netboot; " \
160 "fi; " \
161 "fi; " \
162 "fi;"
163
164 /* Link Definitions */
165 #define CONFIG_LOADADDR 0x40480000
166
167 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
168
169 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
170 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
171 #define CONFIG_SYS_INIT_SP_OFFSET \
172 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
173 #define CONFIG_SYS_INIT_SP_ADDR \
174 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
175
176 #define CONFIG_ENV_OVERWRITE
177 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
178 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
179 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
180 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
181 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
182 #endif
183 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
184 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
185
186 /* Size of malloc() pool */
187 #define CONFIG_SYS_MALLOC_LEN SZ_32M
188
189 #define CONFIG_SYS_SDRAM_BASE 0x40000000
190 #define PHYS_SDRAM 0x40000000
191 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
192
193 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
194 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
195
196 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
197
198 /* Monitor Command Prompt */
199 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
200 #define CONFIG_SYS_CBSIZE 2048
201 #define CONFIG_SYS_MAXARGS 64
202 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
203 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
204 sizeof(CONFIG_SYS_PROMPT) + 16)
205
206 #define CONFIG_IMX_BOOTAUX
207
208 /* USDHC */
209 #define CONFIG_FSL_USDHC
210
211 #define CONFIG_SYS_FSL_USDHC_NUM 2
212 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
213
214 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
215
216 #ifdef CONFIG_FSL_FSPI
217 #define FSL_FSPI_FLASH_SIZE SZ_32M
218 #define FSL_FSPI_FLASH_NUM 1
219 #define FSPI0_BASE_ADDR 0x30bb0000
220 #define FSPI0_AMBA_BASE 0x0
221 #define CONFIG_FSPI_QUAD_SUPPORT
222
223 #define CONFIG_SYS_FSL_FSPI_AHB
224 #endif
225
226 #ifdef CONFIG_NAND_MXS
227 #define CONFIG_CMD_NAND_TRIMFFS
228
229 /* NAND stuff */
230 #define CONFIG_SYS_MAX_NAND_DEVICE 1
231 #define CONFIG_SYS_NAND_BASE 0x20000000
232 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
233 #define CONFIG_SYS_NAND_ONFI_DETECTION
234 #define CONFIG_SYS_NAND_USE_FLASH_BBT
235 #endif /* CONFIG_NAND_MXS */
236
237 #define CONFIG_SYS_I2C_SPEED 100000
238
239 #endif
240