Commit 5187303fc8ae3f5e266e725c5b526381d2b77236
Committed by
Ye Li
Ye Li
1 parent
e384b64424
Exists in
smarc_8mq_lf_v2020.04
and in
4 other branches
MLK-23928: board: freescale: imx8mn audio board 2.0
Add support for imx8mn audio board 2.0 support reuse common settings from imx8mn evk som Rework for imx_v2020.04 defconfig, dts and SPL Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Showing 15 changed files with 4469 additions and 11 deletions Side-by-side Diff
- arch/arm/dts/Makefile
- arch/arm/dts/imx8mn-ab2-u-boot.dtsi
- arch/arm/dts/imx8mn-ab2.dts
- arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
- arch/arm/dts/imx8mn-ddr4-ab2.dts
- arch/arm/mach-imx/imx8m/Kconfig
- board/freescale/imx8mm_ab2/Kconfig
- board/freescale/imx8mm_ab2/Makefile
- board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c
- board/freescale/imx8mm_ab2/imx8mm_ab2.c
- board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c
- board/freescale/imx8mm_ab2/spl.c
- configs/imx8mn_ab2_defconfig
- configs/imx8mn_ddr4_ab2_defconfig
- include/configs/imx8mn_ab2.h
arch/arm/dts/Makefile
arch/arm/dts/imx8mn-ab2-u-boot.dtsi
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +/* | |
| 3 | + * Copyright 2020 NXP | |
| 4 | + */ | |
| 5 | + | |
| 6 | +/ { | |
| 7 | + firmware { | |
| 8 | + optee { | |
| 9 | + compatible = "linaro,optee-tz"; | |
| 10 | + method = "smc"; | |
| 11 | + }; | |
| 12 | + }; | |
| 13 | +}; | |
| 14 | + | |
| 15 | +&{/soc@0} { | |
| 16 | + u-boot,dm-pre-reloc; | |
| 17 | + u-boot,dm-spl; | |
| 18 | +}; | |
| 19 | + | |
| 20 | +&clk { | |
| 21 | + u-boot,dm-spl; | |
| 22 | + u-boot,dm-pre-reloc; | |
| 23 | + /delete-property/ assigned-clocks; | |
| 24 | + /delete-property/ assigned-clock-parents; | |
| 25 | + /delete-property/ assigned-clock-rates; | |
| 26 | +}; | |
| 27 | + | |
| 28 | +&osc_24m { | |
| 29 | + u-boot,dm-spl; | |
| 30 | + u-boot,dm-pre-reloc; | |
| 31 | +}; | |
| 32 | + | |
| 33 | +&aips1 { | |
| 34 | + u-boot,dm-spl; | |
| 35 | + u-boot,dm-pre-reloc; | |
| 36 | +}; | |
| 37 | + | |
| 38 | +&aips2 { | |
| 39 | + u-boot,dm-spl; | |
| 40 | +}; | |
| 41 | + | |
| 42 | +&aips3 { | |
| 43 | + u-boot,dm-spl; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +&iomuxc { | |
| 47 | + u-boot,dm-spl; | |
| 48 | +}; | |
| 49 | + | |
| 50 | +®_usdhc2_vmmc { | |
| 51 | + u-boot,dm-spl; | |
| 52 | +}; | |
| 53 | + | |
| 54 | +&pinctrl_reg_usdhc2_vmmc { | |
| 55 | + u-boot,dm-spl; | |
| 56 | +}; | |
| 57 | + | |
| 58 | +&pinctrl_uart2 { | |
| 59 | + u-boot,dm-spl; | |
| 60 | +}; | |
| 61 | + | |
| 62 | +&pinctrl_usdhc2_gpio { | |
| 63 | + u-boot,dm-spl; | |
| 64 | +}; | |
| 65 | + | |
| 66 | +&pinctrl_usdhc2 { | |
| 67 | + u-boot,dm-spl; | |
| 68 | +}; | |
| 69 | + | |
| 70 | +&pinctrl_usdhc3 { | |
| 71 | + u-boot,dm-spl; | |
| 72 | +}; | |
| 73 | + | |
| 74 | +&gpio1 { | |
| 75 | + u-boot,dm-spl; | |
| 76 | +}; | |
| 77 | + | |
| 78 | +&gpio2 { | |
| 79 | + u-boot,dm-spl; | |
| 80 | +}; | |
| 81 | + | |
| 82 | +&gpio3 { | |
| 83 | + u-boot,dm-spl; | |
| 84 | +}; | |
| 85 | + | |
| 86 | +&gpio4 { | |
| 87 | + u-boot,dm-spl; | |
| 88 | +}; | |
| 89 | + | |
| 90 | +&gpio5 { | |
| 91 | + u-boot,dm-spl; | |
| 92 | +}; | |
| 93 | + | |
| 94 | +&uart2 { | |
| 95 | + u-boot,dm-spl; | |
| 96 | +}; | |
| 97 | + | |
| 98 | +&usdhc1 { | |
| 99 | + u-boot,dm-spl; | |
| 100 | + assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; | |
| 101 | + assigned-clock-rates = <400000000>; | |
| 102 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; | |
| 103 | +}; | |
| 104 | + | |
| 105 | +&usdhc2 { | |
| 106 | + u-boot,dm-spl; | |
| 107 | + sd-uhs-sdr104; | |
| 108 | + sd-uhs-ddr50; | |
| 109 | + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; | |
| 110 | + assigned-clock-rates = <400000000>; | |
| 111 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; | |
| 112 | +}; | |
| 113 | + | |
| 114 | +&usdhc3 { | |
| 115 | + u-boot,dm-spl; | |
| 116 | + mmc-hs400-1_8v; | |
| 117 | + mmc-hs400-enhanced-strobe; | |
| 118 | + assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; | |
| 119 | + assigned-clock-rates = <400000000>; | |
| 120 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; | |
| 121 | +}; | |
| 122 | + | |
| 123 | +&flexspi { | |
| 124 | + assigned-clock-rates = <100000000>; | |
| 125 | + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; | |
| 126 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; | |
| 127 | +}; |
arch/arm/dts/imx8mn-ab2.dts
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +/* | |
| 3 | + * Copyright 2020 NXP | |
| 4 | + */ | |
| 5 | + | |
| 6 | +/dts-v1/; | |
| 7 | + | |
| 8 | +#include "imx8mn.dtsi" | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + model = "NXP i.MX8MNano LPDDR4 Audio board 2.0"; | |
| 12 | + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; | |
| 13 | + | |
| 14 | + chosen { | |
| 15 | + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; | |
| 16 | + stdout-path = &uart2; | |
| 17 | + }; | |
| 18 | + | |
| 19 | + reg_usdhc2_vmmc: regulator-usdhc2 { | |
| 20 | + compatible = "regulator-fixed"; | |
| 21 | + pinctrl-names = "default"; | |
| 22 | + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; | |
| 23 | + regulator-name = "VSD_3V3"; | |
| 24 | + regulator-min-microvolt = <3300000>; | |
| 25 | + regulator-max-microvolt = <3300000>; | |
| 26 | + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; | |
| 27 | + enable-active-high; | |
| 28 | + startup-delay-us = <100>; | |
| 29 | + off-on-delay-us = <12000>; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { | |
| 33 | + compatible = "regulator-fixed"; | |
| 34 | + regulator-name = "ab2_ana_pwr"; | |
| 35 | + pinctrl-names = "default"; | |
| 36 | + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; | |
| 37 | + regulator-min-microvolt = <3300000>; | |
| 38 | + regulator-max-microvolt = <3300000>; | |
| 39 | + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; | |
| 40 | + enable-active-high; | |
| 41 | + }; | |
| 42 | + | |
| 43 | + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { | |
| 44 | + compatible = "regulator-fixed"; | |
| 45 | + regulator-name = "ab2_vdd_pwr_5v0"; | |
| 46 | + regulator-min-microvolt = <5000000>; | |
| 47 | + regulator-max-microvolt = <5000000>; | |
| 48 | + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
| 49 | + enable-active-high; | |
| 50 | + startup-delay-us = <100>; | |
| 51 | + u-boot,off-on-delay-us = <12000>; | |
| 52 | + }; | |
| 53 | +}; | |
| 54 | + | |
| 55 | +&iomuxc { | |
| 56 | + pinctrl-names = "default"; | |
| 57 | + pinctrl-0 = <&pinctrl_hog_1>; | |
| 58 | + | |
| 59 | + imx8mn-evk { | |
| 60 | + pinctrl_hog_1: hoggrp-1 { | |
| 61 | + fsl,pins = < | |
| 62 | + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 | |
| 63 | + >; | |
| 64 | + }; | |
| 65 | + | |
| 66 | + pinctrl_fec1: fec1grp { | |
| 67 | + fsl,pins = < | |
| 68 | + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 | |
| 69 | + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 | |
| 70 | + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f | |
| 71 | + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f | |
| 72 | + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f | |
| 73 | + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f | |
| 74 | + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 | |
| 75 | + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 | |
| 76 | + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 | |
| 77 | + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 | |
| 78 | + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f | |
| 79 | + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 | |
| 80 | + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 | |
| 81 | + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f | |
| 82 | + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 | |
| 83 | + >; | |
| 84 | + }; | |
| 85 | + | |
| 86 | + pinctrl_flexspi0: flexspi0grp { | |
| 87 | + fsl,pins = < | |
| 88 | + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 | |
| 89 | + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 | |
| 90 | + | |
| 91 | + MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084 | |
| 92 | + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 | |
| 93 | + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 | |
| 94 | + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 | |
| 95 | + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 | |
| 96 | + >; | |
| 97 | + }; | |
| 98 | + | |
| 99 | + pinctrl_i2c1: i2c1grp { | |
| 100 | + fsl,pins = < | |
| 101 | + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 | |
| 102 | + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 | |
| 103 | + >; | |
| 104 | + }; | |
| 105 | + | |
| 106 | + pinctrl_i2c2: i2c2grp { | |
| 107 | + fsl,pins = < | |
| 108 | + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 | |
| 109 | + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 | |
| 110 | + >; | |
| 111 | + }; | |
| 112 | + | |
| 113 | + pinctrl_i2c3: i2c3grp { | |
| 114 | + fsl,pins = < | |
| 115 | + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 | |
| 116 | + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 | |
| 117 | + >; | |
| 118 | + }; | |
| 119 | + | |
| 120 | + pinctrl_i2c1_gpio: i2c1grp-gpio { | |
| 121 | + fsl,pins = < | |
| 122 | + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 | |
| 123 | + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 | |
| 124 | + >; | |
| 125 | + }; | |
| 126 | + | |
| 127 | + pinctrl_i2c2_gpio: i2c2grp-gpio { | |
| 128 | + fsl,pins = < | |
| 129 | + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 | |
| 130 | + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 | |
| 131 | + >; | |
| 132 | + }; | |
| 133 | + | |
| 134 | + pinctrl_i2c3_gpio: i2c3grp-gpio { | |
| 135 | + fsl,pins = < | |
| 136 | + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 | |
| 137 | + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 | |
| 138 | + >; | |
| 139 | + }; | |
| 140 | + | |
| 141 | + pinctrl_pmic: pmicirq { | |
| 142 | + fsl,pins = < | |
| 143 | + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 | |
| 144 | + >; | |
| 145 | + }; | |
| 146 | + | |
| 147 | + | |
| 148 | + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { | |
| 149 | + fsl,pins = < | |
| 150 | + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 | |
| 151 | + >; | |
| 152 | + }; | |
| 153 | + | |
| 154 | + pinctrl_ab2_ana_pwr: ab2anapwrgrp { | |
| 155 | + fsl,pins = < | |
| 156 | + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 | |
| 157 | + >; | |
| 158 | + }; | |
| 159 | + | |
| 160 | + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { | |
| 161 | + fsl,pins = < | |
| 162 | + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 | |
| 163 | + >; | |
| 164 | + }; | |
| 165 | + | |
| 166 | + pinctrl_uart2: uart1grp { | |
| 167 | + fsl,pins = < | |
| 168 | + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 | |
| 169 | + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 | |
| 170 | + >; | |
| 171 | + }; | |
| 172 | + | |
| 173 | + pinctrl_usdhc2_gpio: usdhc2grpgpio { | |
| 174 | + fsl,pins = < | |
| 175 | + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 | |
| 176 | + >; | |
| 177 | + }; | |
| 178 | + | |
| 179 | + pinctrl_usdhc2: usdhc2grp { | |
| 180 | + fsl,pins = < | |
| 181 | + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 | |
| 182 | + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 | |
| 183 | + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 | |
| 184 | + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 | |
| 185 | + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 | |
| 186 | + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 | |
| 187 | + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 | |
| 188 | + >; | |
| 189 | + }; | |
| 190 | + | |
| 191 | + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { | |
| 192 | + fsl,pins = < | |
| 193 | + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 | |
| 194 | + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 | |
| 195 | + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 | |
| 196 | + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 | |
| 197 | + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 | |
| 198 | + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 | |
| 199 | + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 | |
| 200 | + >; | |
| 201 | + }; | |
| 202 | + | |
| 203 | + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { | |
| 204 | + fsl,pins = < | |
| 205 | + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 | |
| 206 | + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 | |
| 207 | + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 | |
| 208 | + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 | |
| 209 | + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 | |
| 210 | + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 | |
| 211 | + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 | |
| 212 | + >; | |
| 213 | + }; | |
| 214 | + | |
| 215 | + pinctrl_usdhc3: usdhc3grp { | |
| 216 | + fsl,pins = < | |
| 217 | + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 | |
| 218 | + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 | |
| 219 | + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 | |
| 220 | + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 | |
| 221 | + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 | |
| 222 | + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 | |
| 223 | + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 | |
| 224 | + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 | |
| 225 | + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 | |
| 226 | + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 | |
| 227 | + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 | |
| 228 | + >; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { | |
| 232 | + fsl,pins = < | |
| 233 | + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 | |
| 234 | + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 | |
| 235 | + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 | |
| 236 | + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 | |
| 237 | + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 | |
| 238 | + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 | |
| 239 | + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 | |
| 240 | + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 | |
| 241 | + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 | |
| 242 | + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 | |
| 243 | + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 | |
| 244 | + >; | |
| 245 | + }; | |
| 246 | + | |
| 247 | + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { | |
| 248 | + fsl,pins = < | |
| 249 | + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 | |
| 250 | + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 | |
| 251 | + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 | |
| 252 | + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 | |
| 253 | + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 | |
| 254 | + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 | |
| 255 | + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 | |
| 256 | + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 | |
| 257 | + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 | |
| 258 | + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 | |
| 259 | + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 | |
| 260 | + >; | |
| 261 | + }; | |
| 262 | + | |
| 263 | + pinctrl_wdog: wdoggrp { | |
| 264 | + fsl,pins = < | |
| 265 | + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 | |
| 266 | + >; | |
| 267 | + }; | |
| 268 | + | |
| 269 | + pinctrl_mipi_dsi_en: mipi_dsi_en { | |
| 270 | + fsl,pins = < | |
| 271 | + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 | |
| 272 | + >; | |
| 273 | + }; | |
| 274 | + }; | |
| 275 | +}; | |
| 276 | + | |
| 277 | +&i2c1 { | |
| 278 | + clock-frequency = <400000>; | |
| 279 | + pinctrl-names = "default", "gpio"; | |
| 280 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 281 | + pinctrl-1 = <&pinctrl_i2c1_gpio>; | |
| 282 | + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; | |
| 283 | + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; | |
| 284 | + status = "okay"; | |
| 285 | + | |
| 286 | + pmic: pca9450@25 { | |
| 287 | + reg = <0x25>; | |
| 288 | + compatible = "nxp,pca9450b"; | |
| 289 | + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ | |
| 290 | + pinctrl-0 = <&pinctrl_pmic>; | |
| 291 | + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; | |
| 292 | + | |
| 293 | + regulators { | |
| 294 | + #address-cells = <1>; | |
| 295 | + #size-cells = <0>; | |
| 296 | + | |
| 297 | + pca9450,pmic-buck2-uses-i2c-dvs; | |
| 298 | + /* Run/Standby voltage */ | |
| 299 | + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; | |
| 300 | + | |
| 301 | + buck1_reg: regulator@0 { | |
| 302 | + reg = <0>; | |
| 303 | + regulator-compatible = "buck1"; | |
| 304 | + regulator-min-microvolt = <600000>; | |
| 305 | + regulator-max-microvolt = <2187500>; | |
| 306 | + regulator-boot-on; | |
| 307 | + regulator-always-on; | |
| 308 | + regulator-ramp-delay = <3125>; | |
| 309 | + }; | |
| 310 | + | |
| 311 | + buck2_reg: regulator@1 { | |
| 312 | + reg = <1>; | |
| 313 | + regulator-compatible = "buck2"; | |
| 314 | + regulator-min-microvolt = <600000>; | |
| 315 | + regulator-max-microvolt = <2187500>; | |
| 316 | + regulator-boot-on; | |
| 317 | + regulator-always-on; | |
| 318 | + regulator-ramp-delay = <3125>; | |
| 319 | + }; | |
| 320 | + | |
| 321 | + buck3_reg: regulator@2 { | |
| 322 | + reg = <2>; | |
| 323 | + regulator-compatible = "buck3"; | |
| 324 | + regulator-min-microvolt = <600000>; | |
| 325 | + regulator-max-microvolt = <2187500>; | |
| 326 | + regulator-boot-on; | |
| 327 | + regulator-always-on; | |
| 328 | + }; | |
| 329 | + | |
| 330 | + buck4_reg: regulator@3 { | |
| 331 | + reg = <3>; | |
| 332 | + regulator-compatible = "buck4"; | |
| 333 | + regulator-min-microvolt = <600000>; | |
| 334 | + regulator-max-microvolt = <3400000>; | |
| 335 | + regulator-boot-on; | |
| 336 | + regulator-always-on; | |
| 337 | + }; | |
| 338 | + | |
| 339 | + buck5_reg: regulator@4 { | |
| 340 | + reg = <4>; | |
| 341 | + regulator-compatible = "buck5"; | |
| 342 | + regulator-min-microvolt = <600000>; | |
| 343 | + regulator-max-microvolt = <3400000>; | |
| 344 | + regulator-boot-on; | |
| 345 | + regulator-always-on; | |
| 346 | + }; | |
| 347 | + | |
| 348 | + buck6_reg: regulator@5 { | |
| 349 | + reg = <5>; | |
| 350 | + regulator-compatible = "buck6"; | |
| 351 | + regulator-min-microvolt = <600000>; | |
| 352 | + regulator-max-microvolt = <3400000>; | |
| 353 | + regulator-boot-on; | |
| 354 | + regulator-always-on; | |
| 355 | + }; | |
| 356 | + | |
| 357 | + ldo1_reg: regulator@6 { | |
| 358 | + reg = <6>; | |
| 359 | + regulator-compatible = "ldo1"; | |
| 360 | + regulator-min-microvolt = <1600000>; | |
| 361 | + regulator-max-microvolt = <3300000>; | |
| 362 | + regulator-boot-on; | |
| 363 | + regulator-always-on; | |
| 364 | + }; | |
| 365 | + | |
| 366 | + ldo2_reg: regulator@7 { | |
| 367 | + reg = <7>; | |
| 368 | + regulator-compatible = "ldo2"; | |
| 369 | + regulator-min-microvolt = <800000>; | |
| 370 | + regulator-max-microvolt = <1150000>; | |
| 371 | + regulator-boot-on; | |
| 372 | + regulator-always-on; | |
| 373 | + }; | |
| 374 | + | |
| 375 | + ldo3_reg: regulator@8 { | |
| 376 | + reg = <8>; | |
| 377 | + regulator-compatible = "ldo3"; | |
| 378 | + regulator-min-microvolt = <800000>; | |
| 379 | + regulator-max-microvolt = <3300000>; | |
| 380 | + regulator-boot-on; | |
| 381 | + regulator-always-on; | |
| 382 | + }; | |
| 383 | + | |
| 384 | + ldo4_reg: regulator@9 { | |
| 385 | + reg = <9>; | |
| 386 | + regulator-compatible = "ldo4"; | |
| 387 | + regulator-min-microvolt = <800000>; | |
| 388 | + regulator-max-microvolt = <3300000>; | |
| 389 | + regulator-boot-on; | |
| 390 | + regulator-always-on; | |
| 391 | + }; | |
| 392 | + | |
| 393 | + ldo5_reg: regulator@10 { | |
| 394 | + reg = <10>; | |
| 395 | + regulator-compatible = "ldo5"; | |
| 396 | + regulator-min-microvolt = <1800000>; | |
| 397 | + regulator-max-microvolt = <3300000>; | |
| 398 | + }; | |
| 399 | + | |
| 400 | + }; | |
| 401 | + }; | |
| 402 | +}; | |
| 403 | + | |
| 404 | +&i2c2 { | |
| 405 | + clock-frequency = <400000>; | |
| 406 | + pinctrl-names = "default", "gpio"; | |
| 407 | + pinctrl-0 = <&pinctrl_i2c2>; | |
| 408 | + pinctrl-1 = <&pinctrl_i2c2_gpio>; | |
| 409 | + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; | |
| 410 | + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; | |
| 411 | + status = "okay"; | |
| 412 | +}; | |
| 413 | + | |
| 414 | +&i2c3 { | |
| 415 | + clock-frequency = <100000>; | |
| 416 | + pinctrl-names = "default", "gpio"; | |
| 417 | + pinctrl-0 = <&pinctrl_i2c3>; | |
| 418 | + pinctrl-1 = <&pinctrl_i2c3_gpio>; | |
| 419 | + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; | |
| 420 | + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; | |
| 421 | + status = "okay"; | |
| 422 | +}; | |
| 423 | + | |
| 424 | +&flexspi { | |
| 425 | + pinctrl-names = "default"; | |
| 426 | + pinctrl-0 = <&pinctrl_flexspi0>; | |
| 427 | + status = "okay"; | |
| 428 | + | |
| 429 | + flash0: mt25qu256aba@0 { | |
| 430 | + reg = <0>; | |
| 431 | + compatible = "jedec,spi-nor"; | |
| 432 | + spi-max-frequency = <80000000>; | |
| 433 | + spi-tx-bus-width = <4>; | |
| 434 | + spi-rx-bus-width = <4>; | |
| 435 | + }; | |
| 436 | +}; | |
| 437 | + | |
| 438 | +&fec1 { | |
| 439 | + pinctrl-names = "default"; | |
| 440 | + pinctrl-0 = <&pinctrl_fec1>; | |
| 441 | + phy-mode = "rgmii-id"; | |
| 442 | + phy-handle = <ðphy0>; | |
| 443 | + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| 444 | + phy-reset-post-delay = <150>; | |
| 445 | + phy-reset-duration = <10>; | |
| 446 | + fsl,magic-packet; | |
| 447 | + status = "okay"; | |
| 448 | + | |
| 449 | + mdio { | |
| 450 | + #address-cells = <1>; | |
| 451 | + #size-cells = <0>; | |
| 452 | + | |
| 453 | + ethphy0: ethernet-phy@0 { | |
| 454 | + compatible = "ethernet-phy-ieee802.3-c22"; | |
| 455 | + reg = <1>; | |
| 456 | + eee-broken-1000t; | |
| 457 | + }; | |
| 458 | + }; | |
| 459 | +}; | |
| 460 | + | |
| 461 | +&snvs_pwrkey { | |
| 462 | + status = "okay"; | |
| 463 | +}; | |
| 464 | + | |
| 465 | +&uart2 { /* console */ | |
| 466 | + pinctrl-names = "default"; | |
| 467 | + pinctrl-0 = <&pinctrl_uart2>; | |
| 468 | + status = "okay"; | |
| 469 | +}; | |
| 470 | + | |
| 471 | +&usdhc2 { | |
| 472 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 473 | + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; | |
| 474 | + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; | |
| 475 | + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; | |
| 476 | + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; | |
| 477 | + bus-width = <4>; | |
| 478 | + vmmc-supply = <®_usdhc2_vmmc>; | |
| 479 | + status = "okay"; | |
| 480 | +}; | |
| 481 | + | |
| 482 | +&usdhc3 { | |
| 483 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 484 | + pinctrl-0 = <&pinctrl_usdhc3>; | |
| 485 | + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | |
| 486 | + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | |
| 487 | + bus-width = <8>; | |
| 488 | + non-removable; | |
| 489 | + status = "okay"; | |
| 490 | +}; | |
| 491 | + | |
| 492 | +&wdog1 { | |
| 493 | + pinctrl-names = "default"; | |
| 494 | + pinctrl-0 = <&pinctrl_wdog>; | |
| 495 | + fsl,ext-reset-output; | |
| 496 | + status = "okay"; | |
| 497 | +}; |
arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +/* | |
| 3 | + * Copyright 2020 NXP | |
| 4 | + */ | |
| 5 | + | |
| 6 | +/ { | |
| 7 | + firmware { | |
| 8 | + optee { | |
| 9 | + compatible = "linaro,optee-tz"; | |
| 10 | + method = "smc"; | |
| 11 | + }; | |
| 12 | + }; | |
| 13 | +}; | |
| 14 | + | |
| 15 | +&{/soc@0} { | |
| 16 | + u-boot,dm-pre-reloc; | |
| 17 | + u-boot,dm-spl; | |
| 18 | +}; | |
| 19 | + | |
| 20 | +&clk { | |
| 21 | + u-boot,dm-spl; | |
| 22 | + u-boot,dm-pre-reloc; | |
| 23 | + /delete-property/ assigned-clocks; | |
| 24 | + /delete-property/ assigned-clock-parents; | |
| 25 | + /delete-property/ assigned-clock-rates; | |
| 26 | +}; | |
| 27 | + | |
| 28 | +&osc_24m { | |
| 29 | + u-boot,dm-spl; | |
| 30 | + u-boot,dm-pre-reloc; | |
| 31 | +}; | |
| 32 | + | |
| 33 | +&aips1 { | |
| 34 | + u-boot,dm-spl; | |
| 35 | + u-boot,dm-pre-reloc; | |
| 36 | +}; | |
| 37 | + | |
| 38 | +&aips2 { | |
| 39 | + u-boot,dm-spl; | |
| 40 | +}; | |
| 41 | + | |
| 42 | +&aips3 { | |
| 43 | + u-boot,dm-spl; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +&iomuxc { | |
| 47 | + u-boot,dm-spl; | |
| 48 | +}; | |
| 49 | + | |
| 50 | +®_usdhc2_vmmc { | |
| 51 | + u-boot,dm-spl; | |
| 52 | +}; | |
| 53 | + | |
| 54 | +&pinctrl_reg_usdhc2_vmmc { | |
| 55 | + u-boot,dm-spl; | |
| 56 | +}; | |
| 57 | + | |
| 58 | +&pinctrl_uart2 { | |
| 59 | + u-boot,dm-spl; | |
| 60 | +}; | |
| 61 | + | |
| 62 | +&pinctrl_usdhc2_gpio { | |
| 63 | + u-boot,dm-spl; | |
| 64 | +}; | |
| 65 | + | |
| 66 | +&pinctrl_usdhc2 { | |
| 67 | + u-boot,dm-spl; | |
| 68 | +}; | |
| 69 | + | |
| 70 | +&pinctrl_usdhc3 { | |
| 71 | + u-boot,dm-spl; | |
| 72 | +}; | |
| 73 | + | |
| 74 | +&gpio1 { | |
| 75 | + u-boot,dm-spl; | |
| 76 | +}; | |
| 77 | + | |
| 78 | +&gpio2 { | |
| 79 | + u-boot,dm-spl; | |
| 80 | +}; | |
| 81 | + | |
| 82 | +&gpio3 { | |
| 83 | + u-boot,dm-spl; | |
| 84 | +}; | |
| 85 | + | |
| 86 | +&gpio4 { | |
| 87 | + u-boot,dm-spl; | |
| 88 | +}; | |
| 89 | + | |
| 90 | +&gpio5 { | |
| 91 | + u-boot,dm-spl; | |
| 92 | +}; | |
| 93 | + | |
| 94 | +&uart2 { | |
| 95 | + u-boot,dm-spl; | |
| 96 | +}; | |
| 97 | + | |
| 98 | +&usdhc1 { | |
| 99 | + u-boot,dm-spl; | |
| 100 | + assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; | |
| 101 | + assigned-clock-rates = <400000000>; | |
| 102 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; | |
| 103 | +}; | |
| 104 | + | |
| 105 | +&usdhc2 { | |
| 106 | + u-boot,dm-spl; | |
| 107 | + sd-uhs-sdr104; | |
| 108 | + sd-uhs-ddr50; | |
| 109 | + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; | |
| 110 | + assigned-clock-rates = <400000000>; | |
| 111 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; | |
| 112 | +}; | |
| 113 | + | |
| 114 | +&usdhc3 { | |
| 115 | + u-boot,dm-spl; | |
| 116 | + mmc-hs400-1_8v; | |
| 117 | + mmc-hs400-enhanced-strobe; | |
| 118 | + assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; | |
| 119 | + assigned-clock-rates = <400000000>; | |
| 120 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; | |
| 121 | +}; | |
| 122 | + | |
| 123 | +&flexspi { | |
| 124 | + assigned-clock-rates = <100000000>; | |
| 125 | + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; | |
| 126 | + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; | |
| 127 | +}; |
arch/arm/dts/imx8mn-ddr4-ab2.dts
| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
| 2 | +/* | |
| 3 | + * Copyright 2020 NXP | |
| 4 | + */ | |
| 5 | + | |
| 6 | +/dts-v1/; | |
| 7 | + | |
| 8 | +#include "imx8mn.dtsi" | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; | |
| 12 | + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; | |
| 13 | + | |
| 14 | + chosen { | |
| 15 | + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; | |
| 16 | + stdout-path = &uart2; | |
| 17 | + }; | |
| 18 | + | |
| 19 | + reg_usdhc2_vmmc: regulator-usdhc2 { | |
| 20 | + compatible = "regulator-fixed"; | |
| 21 | + pinctrl-names = "default"; | |
| 22 | + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; | |
| 23 | + regulator-name = "VSD_3V3"; | |
| 24 | + regulator-min-microvolt = <3300000>; | |
| 25 | + regulator-max-microvolt = <3300000>; | |
| 26 | + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; | |
| 27 | + enable-active-high; | |
| 28 | + startup-delay-us = <100>; | |
| 29 | + off-on-delay-us = <12000>; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { | |
| 33 | + compatible = "regulator-fixed"; | |
| 34 | + regulator-name = "ab2_ana_pwr"; | |
| 35 | + pinctrl-names = "default"; | |
| 36 | + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; | |
| 37 | + regulator-min-microvolt = <3300000>; | |
| 38 | + regulator-max-microvolt = <3300000>; | |
| 39 | + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; | |
| 40 | + enable-active-high; | |
| 41 | + }; | |
| 42 | + | |
| 43 | + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { | |
| 44 | + compatible = "regulator-fixed"; | |
| 45 | + regulator-name = "ab2_vdd_pwr_5v0"; | |
| 46 | + regulator-min-microvolt = <5000000>; | |
| 47 | + regulator-max-microvolt = <5000000>; | |
| 48 | + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
| 49 | + enable-active-high; | |
| 50 | + startup-delay-us = <100>; | |
| 51 | + u-boot,off-on-delay-us = <12000>; | |
| 52 | + }; | |
| 53 | +}; | |
| 54 | + | |
| 55 | +&iomuxc { | |
| 56 | + pinctrl-names = "default"; | |
| 57 | + pinctrl-0 = <&pinctrl_hog_1>; | |
| 58 | + | |
| 59 | + imx8mn-evk { | |
| 60 | + pinctrl_hog_1: hoggrp-1 { | |
| 61 | + fsl,pins = < | |
| 62 | + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 | |
| 63 | + >; | |
| 64 | + }; | |
| 65 | + | |
| 66 | + pinctrl_fec1: fec1grp { | |
| 67 | + fsl,pins = < | |
| 68 | + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 | |
| 69 | + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 | |
| 70 | + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f | |
| 71 | + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f | |
| 72 | + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f | |
| 73 | + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f | |
| 74 | + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 | |
| 75 | + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 | |
| 76 | + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 | |
| 77 | + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 | |
| 78 | + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f | |
| 79 | + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 | |
| 80 | + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 | |
| 81 | + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f | |
| 82 | + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 | |
| 83 | + >; | |
| 84 | + }; | |
| 85 | + | |
| 86 | + pinctrl_flexspi0: flexspi0grp { | |
| 87 | + fsl,pins = < | |
| 88 | + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 | |
| 89 | + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 | |
| 90 | + | |
| 91 | + MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084 | |
| 92 | + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 | |
| 93 | + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 | |
| 94 | + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 | |
| 95 | + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 | |
| 96 | + >; | |
| 97 | + }; | |
| 98 | + | |
| 99 | + pinctrl_i2c1: i2c1grp { | |
| 100 | + fsl,pins = < | |
| 101 | + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 | |
| 102 | + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 | |
| 103 | + >; | |
| 104 | + }; | |
| 105 | + | |
| 106 | + pinctrl_i2c2: i2c2grp { | |
| 107 | + fsl,pins = < | |
| 108 | + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 | |
| 109 | + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 | |
| 110 | + >; | |
| 111 | + }; | |
| 112 | + | |
| 113 | + pinctrl_i2c3: i2c3grp { | |
| 114 | + fsl,pins = < | |
| 115 | + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 | |
| 116 | + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 | |
| 117 | + >; | |
| 118 | + }; | |
| 119 | + | |
| 120 | + pinctrl_i2c1_gpio: i2c1grp-gpio { | |
| 121 | + fsl,pins = < | |
| 122 | + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 | |
| 123 | + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 | |
| 124 | + >; | |
| 125 | + }; | |
| 126 | + | |
| 127 | + pinctrl_i2c2_gpio: i2c2grp-gpio { | |
| 128 | + fsl,pins = < | |
| 129 | + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 | |
| 130 | + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 | |
| 131 | + >; | |
| 132 | + }; | |
| 133 | + | |
| 134 | + pinctrl_i2c3_gpio: i2c3grp-gpio { | |
| 135 | + fsl,pins = < | |
| 136 | + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 | |
| 137 | + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 | |
| 138 | + >; | |
| 139 | + }; | |
| 140 | + | |
| 141 | + pinctrl_pmic: pmicirq { | |
| 142 | + fsl,pins = < | |
| 143 | + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 | |
| 144 | + >; | |
| 145 | + }; | |
| 146 | + | |
| 147 | + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { | |
| 148 | + fsl,pins = < | |
| 149 | + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 | |
| 150 | + >; | |
| 151 | + }; | |
| 152 | + | |
| 153 | + pinctrl_ab2_ana_pwr: ab2anapwrgrp { | |
| 154 | + fsl,pins = < | |
| 155 | + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 | |
| 156 | + >; | |
| 157 | + }; | |
| 158 | + | |
| 159 | + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { | |
| 160 | + fsl,pins = < | |
| 161 | + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 | |
| 162 | + >; | |
| 163 | + }; | |
| 164 | + | |
| 165 | + pinctrl_uart2: uart1grp { | |
| 166 | + fsl,pins = < | |
| 167 | + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 | |
| 168 | + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 | |
| 169 | + >; | |
| 170 | + }; | |
| 171 | + | |
| 172 | + pinctrl_usdhc2_gpio: usdhc2grpgpio { | |
| 173 | + fsl,pins = < | |
| 174 | + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 | |
| 175 | + >; | |
| 176 | + }; | |
| 177 | + | |
| 178 | + pinctrl_usdhc2: usdhc2grp { | |
| 179 | + fsl,pins = < | |
| 180 | + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 | |
| 181 | + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 | |
| 182 | + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 | |
| 183 | + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 | |
| 184 | + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 | |
| 185 | + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 | |
| 186 | + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 | |
| 187 | + >; | |
| 188 | + }; | |
| 189 | + | |
| 190 | + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { | |
| 191 | + fsl,pins = < | |
| 192 | + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 | |
| 193 | + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 | |
| 194 | + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 | |
| 195 | + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 | |
| 196 | + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 | |
| 197 | + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 | |
| 198 | + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 | |
| 199 | + >; | |
| 200 | + }; | |
| 201 | + | |
| 202 | + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { | |
| 203 | + fsl,pins = < | |
| 204 | + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 | |
| 205 | + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 | |
| 206 | + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 | |
| 207 | + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 | |
| 208 | + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 | |
| 209 | + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 | |
| 210 | + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 | |
| 211 | + >; | |
| 212 | + }; | |
| 213 | + | |
| 214 | + pinctrl_usdhc3: usdhc3grp { | |
| 215 | + fsl,pins = < | |
| 216 | + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 | |
| 217 | + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 | |
| 218 | + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 | |
| 219 | + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 | |
| 220 | + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 | |
| 221 | + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 | |
| 222 | + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 | |
| 223 | + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 | |
| 224 | + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 | |
| 225 | + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 | |
| 226 | + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 | |
| 227 | + >; | |
| 228 | + }; | |
| 229 | + | |
| 230 | + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { | |
| 231 | + fsl,pins = < | |
| 232 | + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 | |
| 233 | + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 | |
| 234 | + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 | |
| 235 | + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 | |
| 236 | + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 | |
| 237 | + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 | |
| 238 | + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 | |
| 239 | + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 | |
| 240 | + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 | |
| 241 | + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 | |
| 242 | + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 | |
| 243 | + >; | |
| 244 | + }; | |
| 245 | + | |
| 246 | + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { | |
| 247 | + fsl,pins = < | |
| 248 | + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 | |
| 249 | + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 | |
| 250 | + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 | |
| 251 | + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 | |
| 252 | + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 | |
| 253 | + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 | |
| 254 | + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 | |
| 255 | + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 | |
| 256 | + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 | |
| 257 | + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 | |
| 258 | + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 | |
| 259 | + >; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + pinctrl_wdog: wdoggrp { | |
| 263 | + fsl,pins = < | |
| 264 | + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 | |
| 265 | + >; | |
| 266 | + }; | |
| 267 | + }; | |
| 268 | +}; | |
| 269 | + | |
| 270 | +&fec1 { | |
| 271 | + pinctrl-names = "default"; | |
| 272 | + pinctrl-0 = <&pinctrl_fec1>; | |
| 273 | + phy-mode = "rgmii-id"; | |
| 274 | + phy-handle = <ðphy0>; | |
| 275 | + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; | |
| 276 | + phy-reset-post-delay = <150>; | |
| 277 | + phy-reset-duration = <10>; | |
| 278 | + fsl,magic-packet; | |
| 279 | + status = "okay"; | |
| 280 | + | |
| 281 | + mdio { | |
| 282 | + #address-cells = <1>; | |
| 283 | + #size-cells = <0>; | |
| 284 | + | |
| 285 | + ethphy0: ethernet-phy@0 { | |
| 286 | + compatible = "ethernet-phy-ieee802.3-c22"; | |
| 287 | + reg = <1>; | |
| 288 | + eee-broken-1000t; | |
| 289 | + }; | |
| 290 | + }; | |
| 291 | +}; | |
| 292 | + | |
| 293 | + | |
| 294 | +&flexspi { | |
| 295 | + pinctrl-names = "default"; | |
| 296 | + pinctrl-0 = <&pinctrl_flexspi0>; | |
| 297 | + status = "okay"; | |
| 298 | + | |
| 299 | + flash0: mt25qu256aba@0 { | |
| 300 | + reg = <0>; | |
| 301 | + compatible = "jedec,spi-nor"; | |
| 302 | + spi-max-frequency = <80000000>; | |
| 303 | + spi-tx-bus-width = <4>; | |
| 304 | + spi-rx-bus-width = <4>; | |
| 305 | + }; | |
| 306 | +}; | |
| 307 | + | |
| 308 | +&i2c1 { | |
| 309 | + clock-frequency = <400000>; | |
| 310 | + pinctrl-names = "default", "gpio"; | |
| 311 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 312 | + pinctrl-1 = <&pinctrl_i2c1_gpio>; | |
| 313 | + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; | |
| 314 | + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; | |
| 315 | + status = "okay"; | |
| 316 | + | |
| 317 | + pmic@4b { | |
| 318 | + compatible = "rohm,bd71847"; | |
| 319 | + reg = <0x4b>; | |
| 320 | + pinctrl-0 = <&pinctrl_pmic>; | |
| 321 | + interrupt-parent = <&gpio1>; | |
| 322 | + interrupts = <3 GPIO_ACTIVE_LOW>; | |
| 323 | + rohm,reset-snvs-powered; | |
| 324 | + | |
| 325 | + regulators { | |
| 326 | + buck1_reg: BUCK1 { | |
| 327 | + regulator-name = "BUCK1"; | |
| 328 | + regulator-min-microvolt = <700000>; | |
| 329 | + regulator-max-microvolt = <1300000>; | |
| 330 | + regulator-boot-on; | |
| 331 | + regulator-always-on; | |
| 332 | + regulator-ramp-delay = <1250>; | |
| 333 | + }; | |
| 334 | + | |
| 335 | + buck2_reg: BUCK2 { | |
| 336 | + regulator-name = "BUCK2"; | |
| 337 | + regulator-min-microvolt = <700000>; | |
| 338 | + regulator-max-microvolt = <1300000>; | |
| 339 | + regulator-boot-on; | |
| 340 | + regulator-always-on; | |
| 341 | + regulator-ramp-delay = <1250>; | |
| 342 | + }; | |
| 343 | + | |
| 344 | + buck3_reg: BUCK3 { | |
| 345 | + // BUCK5 in datasheet | |
| 346 | + regulator-name = "BUCK3"; | |
| 347 | + regulator-min-microvolt = <700000>; | |
| 348 | + regulator-max-microvolt = <1350000>; | |
| 349 | + }; | |
| 350 | + | |
| 351 | + buck4_reg: BUCK4 { | |
| 352 | + // BUCK6 in datasheet | |
| 353 | + regulator-name = "BUCK4"; | |
| 354 | + regulator-min-microvolt = <3000000>; | |
| 355 | + regulator-max-microvolt = <3300000>; | |
| 356 | + regulator-boot-on; | |
| 357 | + regulator-always-on; | |
| 358 | + }; | |
| 359 | + | |
| 360 | + buck5_reg: BUCK5 { | |
| 361 | + // BUCK7 in datasheet | |
| 362 | + regulator-name = "BUCK5"; | |
| 363 | + regulator-min-microvolt = <1605000>; | |
| 364 | + regulator-max-microvolt = <1995000>; | |
| 365 | + regulator-boot-on; | |
| 366 | + regulator-always-on; | |
| 367 | + }; | |
| 368 | + | |
| 369 | + buck6_reg: BUCK6 { | |
| 370 | + // BUCK8 in datasheet | |
| 371 | + regulator-name = "BUCK6"; | |
| 372 | + regulator-min-microvolt = <800000>; | |
| 373 | + regulator-max-microvolt = <1400000>; | |
| 374 | + regulator-boot-on; | |
| 375 | + regulator-always-on; | |
| 376 | + }; | |
| 377 | + | |
| 378 | + ldo1_reg: LDO1 { | |
| 379 | + regulator-name = "LDO1"; | |
| 380 | + regulator-min-microvolt = <3000000>; | |
| 381 | + regulator-max-microvolt = <3300000>; | |
| 382 | + regulator-boot-on; | |
| 383 | + regulator-always-on; | |
| 384 | + }; | |
| 385 | + | |
| 386 | + ldo2_reg: LDO2 { | |
| 387 | + regulator-name = "LDO2"; | |
| 388 | + regulator-min-microvolt = <900000>; | |
| 389 | + regulator-max-microvolt = <900000>; | |
| 390 | + regulator-boot-on; | |
| 391 | + regulator-always-on; | |
| 392 | + }; | |
| 393 | + | |
| 394 | + ldo3_reg: LDO3 { | |
| 395 | + regulator-name = "LDO3"; | |
| 396 | + regulator-min-microvolt = <1800000>; | |
| 397 | + regulator-max-microvolt = <3300000>; | |
| 398 | + regulator-boot-on; | |
| 399 | + regulator-always-on; | |
| 400 | + }; | |
| 401 | + | |
| 402 | + ldo4_reg: LDO4 { | |
| 403 | + regulator-name = "LDO4"; | |
| 404 | + regulator-min-microvolt = <900000>; | |
| 405 | + regulator-max-microvolt = <1800000>; | |
| 406 | + regulator-boot-on; | |
| 407 | + regulator-always-on; | |
| 408 | + }; | |
| 409 | + | |
| 410 | + ldo6_reg: LDO6 { | |
| 411 | + regulator-name = "LDO6"; | |
| 412 | + regulator-min-microvolt = <900000>; | |
| 413 | + regulator-max-microvolt = <1800000>; | |
| 414 | + regulator-boot-on; | |
| 415 | + regulator-always-on; | |
| 416 | + }; | |
| 417 | + }; | |
| 418 | + }; | |
| 419 | +}; | |
| 420 | + | |
| 421 | +&i2c2 { | |
| 422 | + clock-frequency = <400000>; | |
| 423 | + pinctrl-names = "default", "gpio"; | |
| 424 | + pinctrl-0 = <&pinctrl_i2c2>; | |
| 425 | + pinctrl-1 = <&pinctrl_i2c2_gpio>; | |
| 426 | + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; | |
| 427 | + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; | |
| 428 | + status = "okay"; | |
| 429 | +}; | |
| 430 | + | |
| 431 | +&i2c3 { | |
| 432 | + clock-frequency = <100000>; | |
| 433 | + pinctrl-names = "default", "gpio"; | |
| 434 | + pinctrl-0 = <&pinctrl_i2c3>; | |
| 435 | + pinctrl-1 = <&pinctrl_i2c3_gpio>; | |
| 436 | + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; | |
| 437 | + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; | |
| 438 | + status = "okay"; | |
| 439 | +}; | |
| 440 | + | |
| 441 | +&snvs_pwrkey { | |
| 442 | + status = "okay"; | |
| 443 | +}; | |
| 444 | + | |
| 445 | +&uart2 { /* console */ | |
| 446 | + pinctrl-names = "default"; | |
| 447 | + pinctrl-0 = <&pinctrl_uart2>; | |
| 448 | + status = "okay"; | |
| 449 | +}; | |
| 450 | + | |
| 451 | +&usdhc2 { | |
| 452 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 453 | + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; | |
| 454 | + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; | |
| 455 | + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; | |
| 456 | + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; | |
| 457 | + bus-width = <4>; | |
| 458 | + vmmc-supply = <®_usdhc2_vmmc>; | |
| 459 | + status = "okay"; | |
| 460 | +}; | |
| 461 | + | |
| 462 | +&usdhc3 { | |
| 463 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 464 | + pinctrl-0 = <&pinctrl_usdhc3>; | |
| 465 | + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | |
| 466 | + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | |
| 467 | + bus-width = <8>; | |
| 468 | + non-removable; | |
| 469 | + status = "okay"; | |
| 470 | +}; | |
| 471 | + | |
| 472 | +&wdog1 { | |
| 473 | + pinctrl-names = "default"; | |
| 474 | + pinctrl-0 = <&pinctrl_wdog>; | |
| 475 | + fsl,ext-reset-output; | |
| 476 | + status = "okay"; | |
| 477 | +}; |
arch/arm/mach-imx/imx8m/Kconfig
| ... | ... | @@ -102,6 +102,18 @@ |
| 102 | 102 | select SUPPORT_SPL |
| 103 | 103 | select IMX8M_LPDDR4 |
| 104 | 104 | |
| 105 | +config TARGET_IMX8MN_AB2 | |
| 106 | + bool "imx8mn LPDDR4 Audio board 2.0" | |
| 107 | + select IMX8MN | |
| 108 | + select SUPPORT_SPL | |
| 109 | + select IMX8M_LPDDR4 | |
| 110 | + | |
| 111 | +config TARGET_IMX8MN_DDR4_AB2 | |
| 112 | + bool "imx8mn DDR4 Audio board 2.0" | |
| 113 | + select IMX8MN | |
| 114 | + select SUPPORT_SPL | |
| 115 | + select IMX8M_DDR4 | |
| 116 | + | |
| 105 | 117 | config TARGET_VERDIN_IMX8MM |
| 106 | 118 | bool "Support Toradex Verdin iMX8M Mini module" |
| 107 | 119 | select IMX8MM |
board/freescale/imx8mm_ab2/Kconfig
| 1 | -if TARGET_IMX8MM_AB2 | |
| 1 | +if TARGET_IMX8MM_AB2 || TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2 | |
| 2 | 2 | |
| 3 | 3 | config SYS_BOARD |
| 4 | 4 | default "imx8mm_ab2" |
| ... | ... | @@ -9,6 +9,11 @@ |
| 9 | 9 | if TARGET_IMX8MM_AB2 |
| 10 | 10 | config SYS_CONFIG_NAME |
| 11 | 11 | default "imx8mm_ab2" |
| 12 | +endif | |
| 13 | + | |
| 14 | +if TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2 | |
| 15 | +config SYS_CONFIG_NAME | |
| 16 | + default "imx8mn_ab2" | |
| 12 | 17 | endif |
| 13 | 18 | |
| 14 | 19 | source "board/freescale/common/Kconfig" |
board/freescale/imx8mm_ab2/Makefile
board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c
Changes suppressed. Click to show
| 1 | +/* | |
| 2 | + * Copyright 2019 NXP | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + * | |
| 6 | + * Generated code from MX8M_DDR_tool | |
| 7 | + * Align with uboot version: | |
| 8 | + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga | |
| 9 | + */ | |
| 10 | + | |
| 11 | +#include <linux/kernel.h> | |
| 12 | +#include <asm/arch/ddr.h> | |
| 13 | + | |
| 14 | +struct dram_cfg_param ddr_ddrc_cfg[] = { | |
| 15 | + /** Initialize DDRC registers **/ | |
| 16 | + { 0x3d400000, 0x81040010 }, | |
| 17 | + { 0x3d400030, 0x20 }, | |
| 18 | + { 0x3d400034, 0x221306 }, | |
| 19 | + { 0x3d400050, 0x210070 }, | |
| 20 | + { 0x3d400054, 0x10008 }, | |
| 21 | + { 0x3d400060, 0x0 }, | |
| 22 | + { 0x3d400064, 0x92014a }, | |
| 23 | + { 0x3d4000c0, 0x0 }, | |
| 24 | + { 0x3d4000c4, 0x1000 }, | |
| 25 | + { 0x3d4000d0, 0xc0030126 }, | |
| 26 | + { 0x3d4000d4, 0x770000 }, | |
| 27 | + { 0x3d4000dc, 0x8340105 }, | |
| 28 | + { 0x3d4000e0, 0x180200 }, | |
| 29 | + { 0x3d4000e4, 0x110000 }, | |
| 30 | + { 0x3d4000e8, 0x2000600 }, | |
| 31 | + { 0x3d4000ec, 0x810 }, | |
| 32 | + { 0x3d4000f0, 0x20 }, | |
| 33 | + { 0x3d4000f4, 0xec7 }, | |
| 34 | + { 0x3d400100, 0x11122914 }, | |
| 35 | + { 0x3d400104, 0x4051c }, | |
| 36 | + { 0x3d400108, 0x608050d }, | |
| 37 | + { 0x3d40010c, 0x400c }, | |
| 38 | + { 0x3d400110, 0x8030409 }, | |
| 39 | + { 0x3d400114, 0x6060403 }, | |
| 40 | + { 0x3d40011c, 0x606 }, | |
| 41 | + { 0x3d400120, 0x7070d0c }, | |
| 42 | + { 0x3d400124, 0x2040a }, | |
| 43 | + { 0x3d40012c, 0x1809010e }, | |
| 44 | + { 0x3d400130, 0x8 }, | |
| 45 | + { 0x3d40013c, 0x0 }, | |
| 46 | + { 0x3d400180, 0x1000040 }, | |
| 47 | + { 0x3d400184, 0x493e }, | |
| 48 | + { 0x3d400190, 0x38b8207 }, | |
| 49 | + { 0x3d400194, 0x2020303 }, | |
| 50 | + { 0x3d400198, 0x7f04011 }, | |
| 51 | + { 0x3d40019c, 0xb0 }, | |
| 52 | + { 0x3d4001a0, 0xe0400018 }, | |
| 53 | + { 0x3d4001a4, 0x48005a }, | |
| 54 | + { 0x3d4001a8, 0x80000000 }, | |
| 55 | + { 0x3d4001b0, 0x1 }, | |
| 56 | + { 0x3d4001b4, 0xb07 }, | |
| 57 | + { 0x3d4001b8, 0x4 }, | |
| 58 | + { 0x3d4001c0, 0x1 }, | |
| 59 | + { 0x3d4001c4, 0x0 }, | |
| 60 | + { 0x3d400200, 0x3f1f }, | |
| 61 | + { 0x3d400204, 0x3f0909 }, | |
| 62 | + { 0x3d400208, 0x700 }, | |
| 63 | + { 0x3d40020c, 0x0 }, | |
| 64 | + { 0x3d400210, 0x1f1f }, | |
| 65 | + { 0x3d400214, 0x7070707 }, | |
| 66 | + { 0x3d400218, 0x7070707 }, | |
| 67 | + { 0x3d40021c, 0xf07 }, | |
| 68 | + { 0x3d400220, 0x3f01 }, | |
| 69 | + { 0x3d400240, 0x6000610 }, | |
| 70 | + { 0x3d400244, 0x1323 }, | |
| 71 | + { 0x3d400400, 0x100 }, | |
| 72 | + | |
| 73 | + /* performance setting */ | |
| 74 | + { 0x3d400250, 0x00001f05 }, | |
| 75 | + { 0x3d400254, 0x1f }, | |
| 76 | + { 0x3d400264, 0x900003ff }, | |
| 77 | + { 0x3d40026c, 0x200003ff }, | |
| 78 | + { 0x3d400494, 0x01000e00 }, | |
| 79 | + { 0x3d400498, 0x03ff0000 }, | |
| 80 | + { 0x3d40049c, 0x01000e00 }, | |
| 81 | + { 0x3d4004a0, 0x03ff0000 }, | |
| 82 | + | |
| 83 | + { 0x3d402050, 0x210070 }, | |
| 84 | + { 0x3d402064, 0x400093 }, | |
| 85 | + { 0x3d4020dc, 0x105 }, | |
| 86 | + { 0x3d4020e0, 0x0 }, | |
| 87 | + { 0x3d4020e8, 0x2000600 }, | |
| 88 | + { 0x3d4020ec, 0x10 }, | |
| 89 | + { 0x3d402100, 0xb081209 }, | |
| 90 | + { 0x3d402104, 0x2020d }, | |
| 91 | + { 0x3d402108, 0x5050309 }, | |
| 92 | + { 0x3d40210c, 0x400c }, | |
| 93 | + { 0x3d402110, 0x5030206 }, | |
| 94 | + { 0x3d402114, 0x3030202 }, | |
| 95 | + { 0x3d40211c, 0x303 }, | |
| 96 | + { 0x3d402120, 0x4040d06 }, | |
| 97 | + { 0x3d402124, 0x20208 }, | |
| 98 | + { 0x3d40212c, 0x1205010e }, | |
| 99 | + { 0x3d402130, 0x8 }, | |
| 100 | + { 0x3d40213c, 0x0 }, | |
| 101 | + { 0x3d402180, 0x1000040 }, | |
| 102 | + { 0x3d402190, 0x3848204 }, | |
| 103 | + { 0x3d402194, 0x2020303 }, | |
| 104 | + { 0x3d4021b4, 0x404 }, | |
| 105 | + { 0x3d4021b8, 0x4 }, | |
| 106 | + { 0x3d402240, 0x6000600 }, | |
| 107 | + { 0x3d4020f4, 0xec7 }, | |
| 108 | +}; | |
| 109 | + | |
| 110 | +/* PHY Initialize Configuration */ | |
| 111 | +struct dram_cfg_param ddr_ddrphy_cfg[] = { | |
| 112 | + { 0x1005f, 0x2fd }, | |
| 113 | + { 0x1015f, 0x2fd }, | |
| 114 | + { 0x1105f, 0x2fd }, | |
| 115 | + { 0x1115f, 0x2fd }, | |
| 116 | + { 0x11005f, 0x2fd }, | |
| 117 | + { 0x11015f, 0x2fd }, | |
| 118 | + { 0x11105f, 0x2fd }, | |
| 119 | + { 0x11115f, 0x2fd }, | |
| 120 | + { 0x55, 0x355 }, | |
| 121 | + { 0x1055, 0x355 }, | |
| 122 | + { 0x2055, 0x355 }, | |
| 123 | + { 0x3055, 0x355 }, | |
| 124 | + { 0x4055, 0x55 }, | |
| 125 | + { 0x5055, 0x55 }, | |
| 126 | + { 0x6055, 0x355 }, | |
| 127 | + { 0x7055, 0x355 }, | |
| 128 | + { 0x8055, 0x355 }, | |
| 129 | + { 0x9055, 0x355 }, | |
| 130 | + { 0x200c5, 0xa }, | |
| 131 | + { 0x1200c5, 0x6 }, | |
| 132 | + { 0x2002e, 0x2 }, | |
| 133 | + { 0x12002e, 0x1 }, | |
| 134 | + { 0x20024, 0x8 }, | |
| 135 | + { 0x2003a, 0x2 }, | |
| 136 | + { 0x120024, 0x8 }, | |
| 137 | + { 0x2003a, 0x2 }, | |
| 138 | + { 0x20056, 0x6 }, | |
| 139 | + { 0x120056, 0xa }, | |
| 140 | + { 0x1004d, 0x1a }, | |
| 141 | + { 0x1014d, 0x1a }, | |
| 142 | + { 0x1104d, 0x1a }, | |
| 143 | + { 0x1114d, 0x1a }, | |
| 144 | + { 0x11004d, 0x1a }, | |
| 145 | + { 0x11014d, 0x1a }, | |
| 146 | + { 0x11104d, 0x1a }, | |
| 147 | + { 0x11114d, 0x1a }, | |
| 148 | + { 0x10049, 0xe38 }, | |
| 149 | + { 0x10149, 0xe38 }, | |
| 150 | + { 0x11049, 0xe38 }, | |
| 151 | + { 0x11149, 0xe38 }, | |
| 152 | + { 0x110049, 0xe38 }, | |
| 153 | + { 0x110149, 0xe38 }, | |
| 154 | + { 0x111049, 0xe38 }, | |
| 155 | + { 0x111149, 0xe38 }, | |
| 156 | + { 0x43, 0x63 }, | |
| 157 | + { 0x1043, 0x63 }, | |
| 158 | + { 0x2043, 0x63 }, | |
| 159 | + { 0x3043, 0x63 }, | |
| 160 | + { 0x4043, 0x63 }, | |
| 161 | + { 0x5043, 0x63 }, | |
| 162 | + { 0x6043, 0x63 }, | |
| 163 | + { 0x7043, 0x63 }, | |
| 164 | + { 0x8043, 0x63 }, | |
| 165 | + { 0x9043, 0x63 }, | |
| 166 | + { 0x20018, 0x1 }, | |
| 167 | + { 0x20075, 0x2 }, | |
| 168 | + { 0x20050, 0x0 }, | |
| 169 | + { 0x20008, 0x258 }, | |
| 170 | + { 0x120008, 0x10a }, | |
| 171 | + { 0x20088, 0x9 }, | |
| 172 | + { 0x200b2, 0x268 }, | |
| 173 | + { 0x10043, 0x5b1 }, | |
| 174 | + { 0x10143, 0x5b1 }, | |
| 175 | + { 0x11043, 0x5b1 }, | |
| 176 | + { 0x11143, 0x5b1 }, | |
| 177 | + { 0x1200b2, 0x268 }, | |
| 178 | + { 0x110043, 0x5b1 }, | |
| 179 | + { 0x110143, 0x5b1 }, | |
| 180 | + { 0x111043, 0x5b1 }, | |
| 181 | + { 0x111143, 0x5b1 }, | |
| 182 | + { 0x200fa, 0x1 }, | |
| 183 | + { 0x1200fa, 0x1 }, | |
| 184 | + { 0x20019, 0x5 }, | |
| 185 | + { 0x120019, 0x5 }, | |
| 186 | + { 0x200f0, 0x5555 }, | |
| 187 | + { 0x200f1, 0x5555 }, | |
| 188 | + { 0x200f2, 0x5555 }, | |
| 189 | + { 0x200f3, 0x5555 }, | |
| 190 | + { 0x200f4, 0x5555 }, | |
| 191 | + { 0x200f5, 0x5555 }, | |
| 192 | + { 0x200f6, 0x5555 }, | |
| 193 | + { 0x200f7, 0xf000 }, | |
| 194 | + { 0x20025, 0x0 }, | |
| 195 | + { 0x2002d, 0x0 }, | |
| 196 | + { 0x12002d, 0x0 }, | |
| 197 | + { 0x2005b, 0x7529 }, | |
| 198 | + { 0x2005c, 0x0 }, | |
| 199 | + { 0x200c7, 0x21 }, | |
| 200 | + { 0x200ca, 0x24 }, | |
| 201 | + { 0x200cc, 0x1f7 }, | |
| 202 | + { 0x1200c7, 0x21 }, | |
| 203 | + { 0x1200ca, 0x24 }, | |
| 204 | + { 0x1200cc, 0x1f7 }, | |
| 205 | + { 0x2007d, 0x212 }, | |
| 206 | + { 0x12007d, 0x212 }, | |
| 207 | + { 0x2007c, 0x61 }, | |
| 208 | + { 0x12007c, 0x61 }, | |
| 209 | + { 0x1004a, 0x500 }, | |
| 210 | + { 0x1104a, 0x500 }, | |
| 211 | + { 0x2002c, 0x0 }, | |
| 212 | +}; | |
| 213 | + | |
| 214 | +/* ddr phy trained csr */ | |
| 215 | +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | |
| 216 | + {0x0200b2, 0x0}, | |
| 217 | + {0x1200b2, 0x0}, | |
| 218 | + {0x2200b2, 0x0}, | |
| 219 | + {0x0200cb, 0x0}, | |
| 220 | + {0x010043, 0x0}, | |
| 221 | + {0x110043, 0x0}, | |
| 222 | + {0x210043, 0x0}, | |
| 223 | + {0x010143, 0x0}, | |
| 224 | + {0x110143, 0x0}, | |
| 225 | + {0x210143, 0x0}, | |
| 226 | + {0x011043, 0x0}, | |
| 227 | + {0x111043, 0x0}, | |
| 228 | + {0x211043, 0x0}, | |
| 229 | + {0x011143, 0x0}, | |
| 230 | + {0x111143, 0x0}, | |
| 231 | + {0x211143, 0x0}, | |
| 232 | + {0x000080, 0x0}, | |
| 233 | + {0x100080, 0x0}, | |
| 234 | + {0x200080, 0x0}, | |
| 235 | + {0x001080, 0x0}, | |
| 236 | + {0x101080, 0x0}, | |
| 237 | + {0x201080, 0x0}, | |
| 238 | + {0x002080, 0x0}, | |
| 239 | + {0x102080, 0x0}, | |
| 240 | + {0x202080, 0x0}, | |
| 241 | + {0x003080, 0x0}, | |
| 242 | + {0x103080, 0x0}, | |
| 243 | + {0x203080, 0x0}, | |
| 244 | + {0x004080, 0x0}, | |
| 245 | + {0x104080, 0x0}, | |
| 246 | + {0x204080, 0x0}, | |
| 247 | + {0x005080, 0x0}, | |
| 248 | + {0x105080, 0x0}, | |
| 249 | + {0x205080, 0x0}, | |
| 250 | + {0x006080, 0x0}, | |
| 251 | + {0x106080, 0x0}, | |
| 252 | + {0x206080, 0x0}, | |
| 253 | + {0x007080, 0x0}, | |
| 254 | + {0x107080, 0x0}, | |
| 255 | + {0x207080, 0x0}, | |
| 256 | + {0x008080, 0x0}, | |
| 257 | + {0x108080, 0x0}, | |
| 258 | + {0x208080, 0x0}, | |
| 259 | + {0x009080, 0x0}, | |
| 260 | + {0x109080, 0x0}, | |
| 261 | + {0x209080, 0x0}, | |
| 262 | + {0x010080, 0x0}, | |
| 263 | + {0x110080, 0x0}, | |
| 264 | + {0x210080, 0x0}, | |
| 265 | + {0x010180, 0x0}, | |
| 266 | + {0x110180, 0x0}, | |
| 267 | + {0x210180, 0x0}, | |
| 268 | + {0x010081, 0x0}, | |
| 269 | + {0x110081, 0x0}, | |
| 270 | + {0x210081, 0x0}, | |
| 271 | + {0x010181, 0x0}, | |
| 272 | + {0x110181, 0x0}, | |
| 273 | + {0x210181, 0x0}, | |
| 274 | + {0x010082, 0x0}, | |
| 275 | + {0x110082, 0x0}, | |
| 276 | + {0x210082, 0x0}, | |
| 277 | + {0x010182, 0x0}, | |
| 278 | + {0x110182, 0x0}, | |
| 279 | + {0x210182, 0x0}, | |
| 280 | + {0x010083, 0x0}, | |
| 281 | + {0x110083, 0x0}, | |
| 282 | + {0x210083, 0x0}, | |
| 283 | + {0x010183, 0x0}, | |
| 284 | + {0x110183, 0x0}, | |
| 285 | + {0x210183, 0x0}, | |
| 286 | + {0x011080, 0x0}, | |
| 287 | + {0x111080, 0x0}, | |
| 288 | + {0x211080, 0x0}, | |
| 289 | + {0x011180, 0x0}, | |
| 290 | + {0x111180, 0x0}, | |
| 291 | + {0x211180, 0x0}, | |
| 292 | + {0x011081, 0x0}, | |
| 293 | + {0x111081, 0x0}, | |
| 294 | + {0x211081, 0x0}, | |
| 295 | + {0x011181, 0x0}, | |
| 296 | + {0x111181, 0x0}, | |
| 297 | + {0x211181, 0x0}, | |
| 298 | + {0x011082, 0x0}, | |
| 299 | + {0x111082, 0x0}, | |
| 300 | + {0x211082, 0x0}, | |
| 301 | + {0x011182, 0x0}, | |
| 302 | + {0x111182, 0x0}, | |
| 303 | + {0x211182, 0x0}, | |
| 304 | + {0x011083, 0x0}, | |
| 305 | + {0x111083, 0x0}, | |
| 306 | + {0x211083, 0x0}, | |
| 307 | + {0x011183, 0x0}, | |
| 308 | + {0x111183, 0x0}, | |
| 309 | + {0x211183, 0x0}, | |
| 310 | + {0x0100d0, 0x0}, | |
| 311 | + {0x1100d0, 0x0}, | |
| 312 | + {0x2100d0, 0x0}, | |
| 313 | + {0x0101d0, 0x0}, | |
| 314 | + {0x1101d0, 0x0}, | |
| 315 | + {0x2101d0, 0x0}, | |
| 316 | + {0x0100d1, 0x0}, | |
| 317 | + {0x1100d1, 0x0}, | |
| 318 | + {0x2100d1, 0x0}, | |
| 319 | + {0x0101d1, 0x0}, | |
| 320 | + {0x1101d1, 0x0}, | |
| 321 | + {0x2101d1, 0x0}, | |
| 322 | + {0x0100d2, 0x0}, | |
| 323 | + {0x1100d2, 0x0}, | |
| 324 | + {0x2100d2, 0x0}, | |
| 325 | + {0x0101d2, 0x0}, | |
| 326 | + {0x1101d2, 0x0}, | |
| 327 | + {0x2101d2, 0x0}, | |
| 328 | + {0x0100d3, 0x0}, | |
| 329 | + {0x1100d3, 0x0}, | |
| 330 | + {0x2100d3, 0x0}, | |
| 331 | + {0x0101d3, 0x0}, | |
| 332 | + {0x1101d3, 0x0}, | |
| 333 | + {0x2101d3, 0x0}, | |
| 334 | + {0x0110d0, 0x0}, | |
| 335 | + {0x1110d0, 0x0}, | |
| 336 | + {0x2110d0, 0x0}, | |
| 337 | + {0x0111d0, 0x0}, | |
| 338 | + {0x1111d0, 0x0}, | |
| 339 | + {0x2111d0, 0x0}, | |
| 340 | + {0x0110d1, 0x0}, | |
| 341 | + {0x1110d1, 0x0}, | |
| 342 | + {0x2110d1, 0x0}, | |
| 343 | + {0x0111d1, 0x0}, | |
| 344 | + {0x1111d1, 0x0}, | |
| 345 | + {0x2111d1, 0x0}, | |
| 346 | + {0x0110d2, 0x0}, | |
| 347 | + {0x1110d2, 0x0}, | |
| 348 | + {0x2110d2, 0x0}, | |
| 349 | + {0x0111d2, 0x0}, | |
| 350 | + {0x1111d2, 0x0}, | |
| 351 | + {0x2111d2, 0x0}, | |
| 352 | + {0x0110d3, 0x0}, | |
| 353 | + {0x1110d3, 0x0}, | |
| 354 | + {0x2110d3, 0x0}, | |
| 355 | + {0x0111d3, 0x0}, | |
| 356 | + {0x1111d3, 0x0}, | |
| 357 | + {0x2111d3, 0x0}, | |
| 358 | + {0x010068, 0x0}, | |
| 359 | + {0x010168, 0x0}, | |
| 360 | + {0x010268, 0x0}, | |
| 361 | + {0x010368, 0x0}, | |
| 362 | + {0x010468, 0x0}, | |
| 363 | + {0x010568, 0x0}, | |
| 364 | + {0x010668, 0x0}, | |
| 365 | + {0x010768, 0x0}, | |
| 366 | + {0x010868, 0x0}, | |
| 367 | + {0x010069, 0x0}, | |
| 368 | + {0x010169, 0x0}, | |
| 369 | + {0x010269, 0x0}, | |
| 370 | + {0x010369, 0x0}, | |
| 371 | + {0x010469, 0x0}, | |
| 372 | + {0x010569, 0x0}, | |
| 373 | + {0x010669, 0x0}, | |
| 374 | + {0x010769, 0x0}, | |
| 375 | + {0x010869, 0x0}, | |
| 376 | + {0x01006a, 0x0}, | |
| 377 | + {0x01016a, 0x0}, | |
| 378 | + {0x01026a, 0x0}, | |
| 379 | + {0x01036a, 0x0}, | |
| 380 | + {0x01046a, 0x0}, | |
| 381 | + {0x01056a, 0x0}, | |
| 382 | + {0x01066a, 0x0}, | |
| 383 | + {0x01076a, 0x0}, | |
| 384 | + {0x01086a, 0x0}, | |
| 385 | + {0x01006b, 0x0}, | |
| 386 | + {0x01016b, 0x0}, | |
| 387 | + {0x01026b, 0x0}, | |
| 388 | + {0x01036b, 0x0}, | |
| 389 | + {0x01046b, 0x0}, | |
| 390 | + {0x01056b, 0x0}, | |
| 391 | + {0x01066b, 0x0}, | |
| 392 | + {0x01076b, 0x0}, | |
| 393 | + {0x01086b, 0x0}, | |
| 394 | + {0x011068, 0x0}, | |
| 395 | + {0x011168, 0x0}, | |
| 396 | + {0x011268, 0x0}, | |
| 397 | + {0x011368, 0x0}, | |
| 398 | + {0x011468, 0x0}, | |
| 399 | + {0x011568, 0x0}, | |
| 400 | + {0x011668, 0x0}, | |
| 401 | + {0x011768, 0x0}, | |
| 402 | + {0x011868, 0x0}, | |
| 403 | + {0x011069, 0x0}, | |
| 404 | + {0x011169, 0x0}, | |
| 405 | + {0x011269, 0x0}, | |
| 406 | + {0x011369, 0x0}, | |
| 407 | + {0x011469, 0x0}, | |
| 408 | + {0x011569, 0x0}, | |
| 409 | + {0x011669, 0x0}, | |
| 410 | + {0x011769, 0x0}, | |
| 411 | + {0x011869, 0x0}, | |
| 412 | + {0x01106a, 0x0}, | |
| 413 | + {0x01116a, 0x0}, | |
| 414 | + {0x01126a, 0x0}, | |
| 415 | + {0x01136a, 0x0}, | |
| 416 | + {0x01146a, 0x0}, | |
| 417 | + {0x01156a, 0x0}, | |
| 418 | + {0x01166a, 0x0}, | |
| 419 | + {0x01176a, 0x0}, | |
| 420 | + {0x01186a, 0x0}, | |
| 421 | + {0x01106b, 0x0}, | |
| 422 | + {0x01116b, 0x0}, | |
| 423 | + {0x01126b, 0x0}, | |
| 424 | + {0x01136b, 0x0}, | |
| 425 | + {0x01146b, 0x0}, | |
| 426 | + {0x01156b, 0x0}, | |
| 427 | + {0x01166b, 0x0}, | |
| 428 | + {0x01176b, 0x0}, | |
| 429 | + {0x01186b, 0x0}, | |
| 430 | + {0x01008c, 0x0}, | |
| 431 | + {0x11008c, 0x0}, | |
| 432 | + {0x21008c, 0x0}, | |
| 433 | + {0x01018c, 0x0}, | |
| 434 | + {0x11018c, 0x0}, | |
| 435 | + {0x21018c, 0x0}, | |
| 436 | + {0x01008d, 0x0}, | |
| 437 | + {0x11008d, 0x0}, | |
| 438 | + {0x21008d, 0x0}, | |
| 439 | + {0x01018d, 0x0}, | |
| 440 | + {0x11018d, 0x0}, | |
| 441 | + {0x21018d, 0x0}, | |
| 442 | + {0x01008e, 0x0}, | |
| 443 | + {0x11008e, 0x0}, | |
| 444 | + {0x21008e, 0x0}, | |
| 445 | + {0x01018e, 0x0}, | |
| 446 | + {0x11018e, 0x0}, | |
| 447 | + {0x21018e, 0x0}, | |
| 448 | + {0x01008f, 0x0}, | |
| 449 | + {0x11008f, 0x0}, | |
| 450 | + {0x21008f, 0x0}, | |
| 451 | + {0x01018f, 0x0}, | |
| 452 | + {0x11018f, 0x0}, | |
| 453 | + {0x21018f, 0x0}, | |
| 454 | + {0x01108c, 0x0}, | |
| 455 | + {0x11108c, 0x0}, | |
| 456 | + {0x21108c, 0x0}, | |
| 457 | + {0x01118c, 0x0}, | |
| 458 | + {0x11118c, 0x0}, | |
| 459 | + {0x21118c, 0x0}, | |
| 460 | + {0x01108d, 0x0}, | |
| 461 | + {0x11108d, 0x0}, | |
| 462 | + {0x21108d, 0x0}, | |
| 463 | + {0x01118d, 0x0}, | |
| 464 | + {0x11118d, 0x0}, | |
| 465 | + {0x21118d, 0x0}, | |
| 466 | + {0x01108e, 0x0}, | |
| 467 | + {0x11108e, 0x0}, | |
| 468 | + {0x21108e, 0x0}, | |
| 469 | + {0x01118e, 0x0}, | |
| 470 | + {0x11118e, 0x0}, | |
| 471 | + {0x21118e, 0x0}, | |
| 472 | + {0x01108f, 0x0}, | |
| 473 | + {0x11108f, 0x0}, | |
| 474 | + {0x21108f, 0x0}, | |
| 475 | + {0x01118f, 0x0}, | |
| 476 | + {0x11118f, 0x0}, | |
| 477 | + {0x21118f, 0x0}, | |
| 478 | + {0x0100c0, 0x0}, | |
| 479 | + {0x1100c0, 0x0}, | |
| 480 | + {0x2100c0, 0x0}, | |
| 481 | + {0x0101c0, 0x0}, | |
| 482 | + {0x1101c0, 0x0}, | |
| 483 | + {0x2101c0, 0x0}, | |
| 484 | + {0x0102c0, 0x0}, | |
| 485 | + {0x1102c0, 0x0}, | |
| 486 | + {0x2102c0, 0x0}, | |
| 487 | + {0x0103c0, 0x0}, | |
| 488 | + {0x1103c0, 0x0}, | |
| 489 | + {0x2103c0, 0x0}, | |
| 490 | + {0x0104c0, 0x0}, | |
| 491 | + {0x1104c0, 0x0}, | |
| 492 | + {0x2104c0, 0x0}, | |
| 493 | + {0x0105c0, 0x0}, | |
| 494 | + {0x1105c0, 0x0}, | |
| 495 | + {0x2105c0, 0x0}, | |
| 496 | + {0x0106c0, 0x0}, | |
| 497 | + {0x1106c0, 0x0}, | |
| 498 | + {0x2106c0, 0x0}, | |
| 499 | + {0x0107c0, 0x0}, | |
| 500 | + {0x1107c0, 0x0}, | |
| 501 | + {0x2107c0, 0x0}, | |
| 502 | + {0x0108c0, 0x0}, | |
| 503 | + {0x1108c0, 0x0}, | |
| 504 | + {0x2108c0, 0x0}, | |
| 505 | + {0x0100c1, 0x0}, | |
| 506 | + {0x1100c1, 0x0}, | |
| 507 | + {0x2100c1, 0x0}, | |
| 508 | + {0x0101c1, 0x0}, | |
| 509 | + {0x1101c1, 0x0}, | |
| 510 | + {0x2101c1, 0x0}, | |
| 511 | + {0x0102c1, 0x0}, | |
| 512 | + {0x1102c1, 0x0}, | |
| 513 | + {0x2102c1, 0x0}, | |
| 514 | + {0x0103c1, 0x0}, | |
| 515 | + {0x1103c1, 0x0}, | |
| 516 | + {0x2103c1, 0x0}, | |
| 517 | + {0x0104c1, 0x0}, | |
| 518 | + {0x1104c1, 0x0}, | |
| 519 | + {0x2104c1, 0x0}, | |
| 520 | + {0x0105c1, 0x0}, | |
| 521 | + {0x1105c1, 0x0}, | |
| 522 | + {0x2105c1, 0x0}, | |
| 523 | + {0x0106c1, 0x0}, | |
| 524 | + {0x1106c1, 0x0}, | |
| 525 | + {0x2106c1, 0x0}, | |
| 526 | + {0x0107c1, 0x0}, | |
| 527 | + {0x1107c1, 0x0}, | |
| 528 | + {0x2107c1, 0x0}, | |
| 529 | + {0x0108c1, 0x0}, | |
| 530 | + {0x1108c1, 0x0}, | |
| 531 | + {0x2108c1, 0x0}, | |
| 532 | + {0x0100c2, 0x0}, | |
| 533 | + {0x1100c2, 0x0}, | |
| 534 | + {0x2100c2, 0x0}, | |
| 535 | + {0x0101c2, 0x0}, | |
| 536 | + {0x1101c2, 0x0}, | |
| 537 | + {0x2101c2, 0x0}, | |
| 538 | + {0x0102c2, 0x0}, | |
| 539 | + {0x1102c2, 0x0}, | |
| 540 | + {0x2102c2, 0x0}, | |
| 541 | + {0x0103c2, 0x0}, | |
| 542 | + {0x1103c2, 0x0}, | |
| 543 | + {0x2103c2, 0x0}, | |
| 544 | + {0x0104c2, 0x0}, | |
| 545 | + {0x1104c2, 0x0}, | |
| 546 | + {0x2104c2, 0x0}, | |
| 547 | + {0x0105c2, 0x0}, | |
| 548 | + {0x1105c2, 0x0}, | |
| 549 | + {0x2105c2, 0x0}, | |
| 550 | + {0x0106c2, 0x0}, | |
| 551 | + {0x1106c2, 0x0}, | |
| 552 | + {0x2106c2, 0x0}, | |
| 553 | + {0x0107c2, 0x0}, | |
| 554 | + {0x1107c2, 0x0}, | |
| 555 | + {0x2107c2, 0x0}, | |
| 556 | + {0x0108c2, 0x0}, | |
| 557 | + {0x1108c2, 0x0}, | |
| 558 | + {0x2108c2, 0x0}, | |
| 559 | + {0x0100c3, 0x0}, | |
| 560 | + {0x1100c3, 0x0}, | |
| 561 | + {0x2100c3, 0x0}, | |
| 562 | + {0x0101c3, 0x0}, | |
| 563 | + {0x1101c3, 0x0}, | |
| 564 | + {0x2101c3, 0x0}, | |
| 565 | + {0x0102c3, 0x0}, | |
| 566 | + {0x1102c3, 0x0}, | |
| 567 | + {0x2102c3, 0x0}, | |
| 568 | + {0x0103c3, 0x0}, | |
| 569 | + {0x1103c3, 0x0}, | |
| 570 | + {0x2103c3, 0x0}, | |
| 571 | + {0x0104c3, 0x0}, | |
| 572 | + {0x1104c3, 0x0}, | |
| 573 | + {0x2104c3, 0x0}, | |
| 574 | + {0x0105c3, 0x0}, | |
| 575 | + {0x1105c3, 0x0}, | |
| 576 | + {0x2105c3, 0x0}, | |
| 577 | + {0x0106c3, 0x0}, | |
| 578 | + {0x1106c3, 0x0}, | |
| 579 | + {0x2106c3, 0x0}, | |
| 580 | + {0x0107c3, 0x0}, | |
| 581 | + {0x1107c3, 0x0}, | |
| 582 | + {0x2107c3, 0x0}, | |
| 583 | + {0x0108c3, 0x0}, | |
| 584 | + {0x1108c3, 0x0}, | |
| 585 | + {0x2108c3, 0x0}, | |
| 586 | + {0x0110c0, 0x0}, | |
| 587 | + {0x1110c0, 0x0}, | |
| 588 | + {0x2110c0, 0x0}, | |
| 589 | + {0x0111c0, 0x0}, | |
| 590 | + {0x1111c0, 0x0}, | |
| 591 | + {0x2111c0, 0x0}, | |
| 592 | + {0x0112c0, 0x0}, | |
| 593 | + {0x1112c0, 0x0}, | |
| 594 | + {0x2112c0, 0x0}, | |
| 595 | + {0x0113c0, 0x0}, | |
| 596 | + {0x1113c0, 0x0}, | |
| 597 | + {0x2113c0, 0x0}, | |
| 598 | + {0x0114c0, 0x0}, | |
| 599 | + {0x1114c0, 0x0}, | |
| 600 | + {0x2114c0, 0x0}, | |
| 601 | + {0x0115c0, 0x0}, | |
| 602 | + {0x1115c0, 0x0}, | |
| 603 | + {0x2115c0, 0x0}, | |
| 604 | + {0x0116c0, 0x0}, | |
| 605 | + {0x1116c0, 0x0}, | |
| 606 | + {0x2116c0, 0x0}, | |
| 607 | + {0x0117c0, 0x0}, | |
| 608 | + {0x1117c0, 0x0}, | |
| 609 | + {0x2117c0, 0x0}, | |
| 610 | + {0x0118c0, 0x0}, | |
| 611 | + {0x1118c0, 0x0}, | |
| 612 | + {0x2118c0, 0x0}, | |
| 613 | + {0x0110c1, 0x0}, | |
| 614 | + {0x1110c1, 0x0}, | |
| 615 | + {0x2110c1, 0x0}, | |
| 616 | + {0x0111c1, 0x0}, | |
| 617 | + {0x1111c1, 0x0}, | |
| 618 | + {0x2111c1, 0x0}, | |
| 619 | + {0x0112c1, 0x0}, | |
| 620 | + {0x1112c1, 0x0}, | |
| 621 | + {0x2112c1, 0x0}, | |
| 622 | + {0x0113c1, 0x0}, | |
| 623 | + {0x1113c1, 0x0}, | |
| 624 | + {0x2113c1, 0x0}, | |
| 625 | + {0x0114c1, 0x0}, | |
| 626 | + {0x1114c1, 0x0}, | |
| 627 | + {0x2114c1, 0x0}, | |
| 628 | + {0x0115c1, 0x0}, | |
| 629 | + {0x1115c1, 0x0}, | |
| 630 | + {0x2115c1, 0x0}, | |
| 631 | + {0x0116c1, 0x0}, | |
| 632 | + {0x1116c1, 0x0}, | |
| 633 | + {0x2116c1, 0x0}, | |
| 634 | + {0x0117c1, 0x0}, | |
| 635 | + {0x1117c1, 0x0}, | |
| 636 | + {0x2117c1, 0x0}, | |
| 637 | + {0x0118c1, 0x0}, | |
| 638 | + {0x1118c1, 0x0}, | |
| 639 | + {0x2118c1, 0x0}, | |
| 640 | + {0x0110c2, 0x0}, | |
| 641 | + {0x1110c2, 0x0}, | |
| 642 | + {0x2110c2, 0x0}, | |
| 643 | + {0x0111c2, 0x0}, | |
| 644 | + {0x1111c2, 0x0}, | |
| 645 | + {0x2111c2, 0x0}, | |
| 646 | + {0x0112c2, 0x0}, | |
| 647 | + {0x1112c2, 0x0}, | |
| 648 | + {0x2112c2, 0x0}, | |
| 649 | + {0x0113c2, 0x0}, | |
| 650 | + {0x1113c2, 0x0}, | |
| 651 | + {0x2113c2, 0x0}, | |
| 652 | + {0x0114c2, 0x0}, | |
| 653 | + {0x1114c2, 0x0}, | |
| 654 | + {0x2114c2, 0x0}, | |
| 655 | + {0x0115c2, 0x0}, | |
| 656 | + {0x1115c2, 0x0}, | |
| 657 | + {0x2115c2, 0x0}, | |
| 658 | + {0x0116c2, 0x0}, | |
| 659 | + {0x1116c2, 0x0}, | |
| 660 | + {0x2116c2, 0x0}, | |
| 661 | + {0x0117c2, 0x0}, | |
| 662 | + {0x1117c2, 0x0}, | |
| 663 | + {0x2117c2, 0x0}, | |
| 664 | + {0x0118c2, 0x0}, | |
| 665 | + {0x1118c2, 0x0}, | |
| 666 | + {0x2118c2, 0x0}, | |
| 667 | + {0x0110c3, 0x0}, | |
| 668 | + {0x1110c3, 0x0}, | |
| 669 | + {0x2110c3, 0x0}, | |
| 670 | + {0x0111c3, 0x0}, | |
| 671 | + {0x1111c3, 0x0}, | |
| 672 | + {0x2111c3, 0x0}, | |
| 673 | + {0x0112c3, 0x0}, | |
| 674 | + {0x1112c3, 0x0}, | |
| 675 | + {0x2112c3, 0x0}, | |
| 676 | + {0x0113c3, 0x0}, | |
| 677 | + {0x1113c3, 0x0}, | |
| 678 | + {0x2113c3, 0x0}, | |
| 679 | + {0x0114c3, 0x0}, | |
| 680 | + {0x1114c3, 0x0}, | |
| 681 | + {0x2114c3, 0x0}, | |
| 682 | + {0x0115c3, 0x0}, | |
| 683 | + {0x1115c3, 0x0}, | |
| 684 | + {0x2115c3, 0x0}, | |
| 685 | + {0x0116c3, 0x0}, | |
| 686 | + {0x1116c3, 0x0}, | |
| 687 | + {0x2116c3, 0x0}, | |
| 688 | + {0x0117c3, 0x0}, | |
| 689 | + {0x1117c3, 0x0}, | |
| 690 | + {0x2117c3, 0x0}, | |
| 691 | + {0x0118c3, 0x0}, | |
| 692 | + {0x1118c3, 0x0}, | |
| 693 | + {0x2118c3, 0x0}, | |
| 694 | + {0x010020, 0x0}, | |
| 695 | + {0x110020, 0x0}, | |
| 696 | + {0x210020, 0x0}, | |
| 697 | + {0x011020, 0x0}, | |
| 698 | + {0x111020, 0x0}, | |
| 699 | + {0x211020, 0x0}, | |
| 700 | + {0x02007d, 0x0}, | |
| 701 | + {0x12007d, 0x0}, | |
| 702 | + {0x22007d, 0x0}, | |
| 703 | + {0x010040, 0x0}, | |
| 704 | + {0x010140, 0x0}, | |
| 705 | + {0x010240, 0x0}, | |
| 706 | + {0x010340, 0x0}, | |
| 707 | + {0x010440, 0x0}, | |
| 708 | + {0x010540, 0x0}, | |
| 709 | + {0x010640, 0x0}, | |
| 710 | + {0x010740, 0x0}, | |
| 711 | + {0x010840, 0x0}, | |
| 712 | + {0x010030, 0x0}, | |
| 713 | + {0x010130, 0x0}, | |
| 714 | + {0x010230, 0x0}, | |
| 715 | + {0x010330, 0x0}, | |
| 716 | + {0x010430, 0x0}, | |
| 717 | + {0x010530, 0x0}, | |
| 718 | + {0x010630, 0x0}, | |
| 719 | + {0x010730, 0x0}, | |
| 720 | + {0x010830, 0x0}, | |
| 721 | + {0x011040, 0x0}, | |
| 722 | + {0x011140, 0x0}, | |
| 723 | + {0x011240, 0x0}, | |
| 724 | + {0x011340, 0x0}, | |
| 725 | + {0x011440, 0x0}, | |
| 726 | + {0x011540, 0x0}, | |
| 727 | + {0x011640, 0x0}, | |
| 728 | + {0x011740, 0x0}, | |
| 729 | + {0x011840, 0x0}, | |
| 730 | + {0x011030, 0x0}, | |
| 731 | + {0x011130, 0x0}, | |
| 732 | + {0x011230, 0x0}, | |
| 733 | + {0x011330, 0x0}, | |
| 734 | + {0x011430, 0x0}, | |
| 735 | + {0x011530, 0x0}, | |
| 736 | + {0x011630, 0x0}, | |
| 737 | + {0x011730, 0x0}, | |
| 738 | + {0x011830, 0x0}, | |
| 739 | +}; | |
| 740 | + | |
| 741 | +/* P0 message block paremeter for training firmware */ | |
| 742 | +struct dram_cfg_param ddr_fsp0_cfg[] = { | |
| 743 | + { 0xd0000, 0x0 }, | |
| 744 | + { 0x54003, 0x960 }, | |
| 745 | + { 0x54004, 0x2 }, | |
| 746 | + { 0x54005, 0x2830 }, | |
| 747 | + { 0x54006, 0x25e }, | |
| 748 | + { 0x54007, 0x1000 }, | |
| 749 | + { 0x54008, 0x101 }, | |
| 750 | + { 0x5400b, 0x31f }, | |
| 751 | + { 0x5400c, 0xc8 }, | |
| 752 | + { 0x5400d, 0x100 }, | |
| 753 | + { 0x54012, 0x1 }, | |
| 754 | + { 0x5402f, 0x834 }, | |
| 755 | + { 0x54030, 0x105 }, | |
| 756 | + { 0x54031, 0x18 }, | |
| 757 | + { 0x54032, 0x200 }, | |
| 758 | + { 0x54033, 0x200 }, | |
| 759 | + { 0x54034, 0x600 }, | |
| 760 | + { 0x54035, 0x810 }, | |
| 761 | + { 0x54036, 0x101 }, | |
| 762 | + { 0x5403f, 0x1221 }, | |
| 763 | + { 0x541fc, 0x100 }, | |
| 764 | + { 0xd0000, 0x1 }, | |
| 765 | +}; | |
| 766 | + | |
| 767 | + | |
| 768 | +/* P1 message block paremeter for training firmware */ | |
| 769 | +struct dram_cfg_param ddr_fsp1_cfg[] = { | |
| 770 | + { 0xd0000, 0x0 }, | |
| 771 | + { 0x54002, 0x1 }, | |
| 772 | + { 0x54003, 0x42a }, | |
| 773 | + { 0x54004, 0x2 }, | |
| 774 | + { 0x54005, 0x2830 }, | |
| 775 | + { 0x54006, 0x25e }, | |
| 776 | + { 0x54007, 0x1000 }, | |
| 777 | + { 0x54008, 0x101 }, | |
| 778 | + { 0x5400b, 0x21f }, | |
| 779 | + { 0x5400c, 0xc8 }, | |
| 780 | + { 0x5400d, 0x100 }, | |
| 781 | + { 0x54012, 0x1 }, | |
| 782 | + { 0x54030, 0x105 }, | |
| 783 | + { 0x54033, 0x200 }, | |
| 784 | + { 0x54034, 0x600 }, | |
| 785 | + { 0x54035, 0x10 }, | |
| 786 | + { 0x54036, 0x101 }, | |
| 787 | + { 0x5403f, 0x1221 }, | |
| 788 | + { 0x541fc, 0x100 }, | |
| 789 | + { 0xd0000, 0x1 }, | |
| 790 | +}; | |
| 791 | + | |
| 792 | + | |
| 793 | +/* P0 2D message block paremeter for training firmware */ | |
| 794 | +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | |
| 795 | + { 0xd0000, 0x0 }, | |
| 796 | + { 0x54003, 0x960 }, | |
| 797 | + { 0x54004, 0x2 }, | |
| 798 | + { 0x54005, 0x2830 }, | |
| 799 | + { 0x54006, 0x25e }, | |
| 800 | + { 0x54007, 0x1000 }, | |
| 801 | + { 0x54008, 0x101 }, | |
| 802 | + { 0x5400b, 0x61 }, | |
| 803 | + { 0x5400c, 0xc8 }, | |
| 804 | + { 0x5400d, 0x100 }, | |
| 805 | + { 0x5400e, 0x1f7f }, | |
| 806 | + { 0x54012, 0x1 }, | |
| 807 | + { 0x5402f, 0x834 }, | |
| 808 | + { 0x54030, 0x105 }, | |
| 809 | + { 0x54031, 0x18 }, | |
| 810 | + { 0x54032, 0x200 }, | |
| 811 | + { 0x54033, 0x200 }, | |
| 812 | + { 0x54034, 0x600 }, | |
| 813 | + { 0x54035, 0x810 }, | |
| 814 | + { 0x54036, 0x101 }, | |
| 815 | + { 0x5403f, 0x1221 }, | |
| 816 | + { 0x541fc, 0x100 }, | |
| 817 | + { 0xd0000, 0x1 }, | |
| 818 | +}; | |
| 819 | + | |
| 820 | +/* DRAM PHY init engine image */ | |
| 821 | +struct dram_cfg_param ddr_phy_pie[] = { | |
| 822 | + { 0xd0000, 0x0 }, | |
| 823 | + { 0x90000, 0x10 }, | |
| 824 | + { 0x90001, 0x400 }, | |
| 825 | + { 0x90002, 0x10e }, | |
| 826 | + { 0x90003, 0x0 }, | |
| 827 | + { 0x90004, 0x0 }, | |
| 828 | + { 0x90005, 0x8 }, | |
| 829 | + { 0x90029, 0xb }, | |
| 830 | + { 0x9002a, 0x480 }, | |
| 831 | + { 0x9002b, 0x109 }, | |
| 832 | + { 0x9002c, 0x8 }, | |
| 833 | + { 0x9002d, 0x448 }, | |
| 834 | + { 0x9002e, 0x139 }, | |
| 835 | + { 0x9002f, 0x8 }, | |
| 836 | + { 0x90030, 0x478 }, | |
| 837 | + { 0x90031, 0x109 }, | |
| 838 | + { 0x90032, 0x2 }, | |
| 839 | + { 0x90033, 0x10 }, | |
| 840 | + { 0x90034, 0x139 }, | |
| 841 | + { 0x90035, 0xb }, | |
| 842 | + { 0x90036, 0x7c0 }, | |
| 843 | + { 0x90037, 0x139 }, | |
| 844 | + { 0x90038, 0x44 }, | |
| 845 | + { 0x90039, 0x633 }, | |
| 846 | + { 0x9003a, 0x159 }, | |
| 847 | + { 0x9003b, 0x14f }, | |
| 848 | + { 0x9003c, 0x630 }, | |
| 849 | + { 0x9003d, 0x159 }, | |
| 850 | + { 0x9003e, 0x47 }, | |
| 851 | + { 0x9003f, 0x633 }, | |
| 852 | + { 0x90040, 0x149 }, | |
| 853 | + { 0x90041, 0x4f }, | |
| 854 | + { 0x90042, 0x633 }, | |
| 855 | + { 0x90043, 0x179 }, | |
| 856 | + { 0x90044, 0x8 }, | |
| 857 | + { 0x90045, 0xe0 }, | |
| 858 | + { 0x90046, 0x109 }, | |
| 859 | + { 0x90047, 0x0 }, | |
| 860 | + { 0x90048, 0x7c8 }, | |
| 861 | + { 0x90049, 0x109 }, | |
| 862 | + { 0x9004a, 0x0 }, | |
| 863 | + { 0x9004b, 0x1 }, | |
| 864 | + { 0x9004c, 0x8 }, | |
| 865 | + { 0x9004d, 0x0 }, | |
| 866 | + { 0x9004e, 0x45a }, | |
| 867 | + { 0x9004f, 0x9 }, | |
| 868 | + { 0x90050, 0x0 }, | |
| 869 | + { 0x90051, 0x448 }, | |
| 870 | + { 0x90052, 0x109 }, | |
| 871 | + { 0x90053, 0x40 }, | |
| 872 | + { 0x90054, 0x633 }, | |
| 873 | + { 0x90055, 0x179 }, | |
| 874 | + { 0x90056, 0x1 }, | |
| 875 | + { 0x90057, 0x618 }, | |
| 876 | + { 0x90058, 0x109 }, | |
| 877 | + { 0x90059, 0x40c0 }, | |
| 878 | + { 0x9005a, 0x633 }, | |
| 879 | + { 0x9005b, 0x149 }, | |
| 880 | + { 0x9005c, 0x8 }, | |
| 881 | + { 0x9005d, 0x4 }, | |
| 882 | + { 0x9005e, 0x48 }, | |
| 883 | + { 0x9005f, 0x4040 }, | |
| 884 | + { 0x90060, 0x633 }, | |
| 885 | + { 0x90061, 0x149 }, | |
| 886 | + { 0x90062, 0x0 }, | |
| 887 | + { 0x90063, 0x4 }, | |
| 888 | + { 0x90064, 0x48 }, | |
| 889 | + { 0x90065, 0x40 }, | |
| 890 | + { 0x90066, 0x633 }, | |
| 891 | + { 0x90067, 0x149 }, | |
| 892 | + { 0x90068, 0x10 }, | |
| 893 | + { 0x90069, 0x4 }, | |
| 894 | + { 0x9006a, 0x18 }, | |
| 895 | + { 0x9006b, 0x0 }, | |
| 896 | + { 0x9006c, 0x4 }, | |
| 897 | + { 0x9006d, 0x78 }, | |
| 898 | + { 0x9006e, 0x549 }, | |
| 899 | + { 0x9006f, 0x633 }, | |
| 900 | + { 0x90070, 0x159 }, | |
| 901 | + { 0x90071, 0xd49 }, | |
| 902 | + { 0x90072, 0x633 }, | |
| 903 | + { 0x90073, 0x159 }, | |
| 904 | + { 0x90074, 0x94a }, | |
| 905 | + { 0x90075, 0x633 }, | |
| 906 | + { 0x90076, 0x159 }, | |
| 907 | + { 0x90077, 0x441 }, | |
| 908 | + { 0x90078, 0x633 }, | |
| 909 | + { 0x90079, 0x149 }, | |
| 910 | + { 0x9007a, 0x42 }, | |
| 911 | + { 0x9007b, 0x633 }, | |
| 912 | + { 0x9007c, 0x149 }, | |
| 913 | + { 0x9007d, 0x1 }, | |
| 914 | + { 0x9007e, 0x633 }, | |
| 915 | + { 0x9007f, 0x149 }, | |
| 916 | + { 0x90080, 0x0 }, | |
| 917 | + { 0x90081, 0xe0 }, | |
| 918 | + { 0x90082, 0x109 }, | |
| 919 | + { 0x90083, 0xa }, | |
| 920 | + { 0x90084, 0x10 }, | |
| 921 | + { 0x90085, 0x109 }, | |
| 922 | + { 0x90086, 0x9 }, | |
| 923 | + { 0x90087, 0x3c0 }, | |
| 924 | + { 0x90088, 0x149 }, | |
| 925 | + { 0x90089, 0x9 }, | |
| 926 | + { 0x9008a, 0x3c0 }, | |
| 927 | + { 0x9008b, 0x159 }, | |
| 928 | + { 0x9008c, 0x18 }, | |
| 929 | + { 0x9008d, 0x10 }, | |
| 930 | + { 0x9008e, 0x109 }, | |
| 931 | + { 0x9008f, 0x0 }, | |
| 932 | + { 0x90090, 0x3c0 }, | |
| 933 | + { 0x90091, 0x109 }, | |
| 934 | + { 0x90092, 0x18 }, | |
| 935 | + { 0x90093, 0x4 }, | |
| 936 | + { 0x90094, 0x48 }, | |
| 937 | + { 0x90095, 0x18 }, | |
| 938 | + { 0x90096, 0x4 }, | |
| 939 | + { 0x90097, 0x58 }, | |
| 940 | + { 0x90098, 0xb }, | |
| 941 | + { 0x90099, 0x10 }, | |
| 942 | + { 0x9009a, 0x109 }, | |
| 943 | + { 0x9009b, 0x1 }, | |
| 944 | + { 0x9009c, 0x10 }, | |
| 945 | + { 0x9009d, 0x109 }, | |
| 946 | + { 0x9009e, 0x5 }, | |
| 947 | + { 0x9009f, 0x7c0 }, | |
| 948 | + { 0x900a0, 0x109 }, | |
| 949 | + { 0x900a1, 0x0 }, | |
| 950 | + { 0x900a2, 0x8140 }, | |
| 951 | + { 0x900a3, 0x10c }, | |
| 952 | + { 0x900a4, 0x10 }, | |
| 953 | + { 0x900a5, 0x8138 }, | |
| 954 | + { 0x900a6, 0x10c }, | |
| 955 | + { 0x900a7, 0x8 }, | |
| 956 | + { 0x900a8, 0x7c8 }, | |
| 957 | + { 0x900a9, 0x101 }, | |
| 958 | + { 0x900aa, 0x8 }, | |
| 959 | + { 0x900ab, 0x448 }, | |
| 960 | + { 0x900ac, 0x109 }, | |
| 961 | + { 0x900ad, 0xf }, | |
| 962 | + { 0x900ae, 0x7c0 }, | |
| 963 | + { 0x900af, 0x109 }, | |
| 964 | + { 0x900b0, 0x47 }, | |
| 965 | + { 0x900b1, 0x630 }, | |
| 966 | + { 0x900b2, 0x109 }, | |
| 967 | + { 0x900b3, 0x8 }, | |
| 968 | + { 0x900b4, 0x618 }, | |
| 969 | + { 0x900b5, 0x109 }, | |
| 970 | + { 0x900b6, 0x8 }, | |
| 971 | + { 0x900b7, 0xe0 }, | |
| 972 | + { 0x900b8, 0x109 }, | |
| 973 | + { 0x900b9, 0x0 }, | |
| 974 | + { 0x900ba, 0x7c8 }, | |
| 975 | + { 0x900bb, 0x109 }, | |
| 976 | + { 0x900bc, 0x8 }, | |
| 977 | + { 0x900bd, 0x8140 }, | |
| 978 | + { 0x900be, 0x10c }, | |
| 979 | + { 0x900bf, 0x0 }, | |
| 980 | + { 0x900c0, 0x1 }, | |
| 981 | + { 0x900c1, 0x8 }, | |
| 982 | + { 0x900c2, 0x8 }, | |
| 983 | + { 0x900c3, 0x4 }, | |
| 984 | + { 0x900c4, 0x8 }, | |
| 985 | + { 0x900c5, 0x8 }, | |
| 986 | + { 0x900c6, 0x7c8 }, | |
| 987 | + { 0x900c7, 0x101 }, | |
| 988 | + { 0x90006, 0x0 }, | |
| 989 | + { 0x90007, 0x0 }, | |
| 990 | + { 0x90008, 0x8 }, | |
| 991 | + { 0x90009, 0x0 }, | |
| 992 | + { 0x9000a, 0x0 }, | |
| 993 | + { 0x9000b, 0x0 }, | |
| 994 | + { 0xd00e7, 0x400 }, | |
| 995 | + { 0x90017, 0x0 }, | |
| 996 | + { 0x90026, 0x2b }, | |
| 997 | + { 0x2000b, 0x4b }, | |
| 998 | + { 0x2000c, 0x96 }, | |
| 999 | + { 0x2000d, 0x5dc }, | |
| 1000 | + { 0x2000e, 0x2c }, | |
| 1001 | + { 0x12000b, 0x21 }, | |
| 1002 | + { 0x12000c, 0x42 }, | |
| 1003 | + { 0x12000d, 0x29a }, | |
| 1004 | + { 0x12000e, 0x21 }, | |
| 1005 | + { 0x9000c, 0x0 }, | |
| 1006 | + { 0x9000d, 0x173 }, | |
| 1007 | + { 0x9000e, 0x60 }, | |
| 1008 | + { 0x9000f, 0x6110 }, | |
| 1009 | + { 0x90010, 0x2152 }, | |
| 1010 | + { 0x90011, 0xdfbd }, | |
| 1011 | + { 0x90012, 0xffff }, | |
| 1012 | + { 0x90013, 0x6152 }, | |
| 1013 | + { 0x20089, 0x1 }, | |
| 1014 | + { 0x20088, 0x19 }, | |
| 1015 | + { 0xc0080, 0x0 }, | |
| 1016 | + { 0xd0000, 0x1 } | |
| 1017 | +}; | |
| 1018 | + | |
| 1019 | +struct dram_fsp_msg ddr_dram_fsp_msg[] = { | |
| 1020 | + { | |
| 1021 | + /* P0 2400mts 1D */ | |
| 1022 | + .drate = 2400, | |
| 1023 | + .fw_type = FW_1D_IMAGE, | |
| 1024 | + .fsp_cfg = ddr_fsp0_cfg, | |
| 1025 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | |
| 1026 | + }, | |
| 1027 | + { | |
| 1028 | + /* P1 1066mts 1D */ | |
| 1029 | + .drate = 1066, | |
| 1030 | + .fw_type = FW_1D_IMAGE, | |
| 1031 | + .fsp_cfg = ddr_fsp1_cfg, | |
| 1032 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | |
| 1033 | + }, | |
| 1034 | + { | |
| 1035 | + /* P0 2400mts 2D */ | |
| 1036 | + .drate = 2400, | |
| 1037 | + .fw_type = FW_2D_IMAGE, | |
| 1038 | + .fsp_cfg = ddr_fsp0_2d_cfg, | |
| 1039 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | |
| 1040 | + }, | |
| 1041 | +}; | |
| 1042 | + | |
| 1043 | +/* ddr timing config params */ | |
| 1044 | +struct dram_timing_info dram_timing = { | |
| 1045 | + .ddrc_cfg = ddr_ddrc_cfg, | |
| 1046 | + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | |
| 1047 | + .ddrphy_cfg = ddr_ddrphy_cfg, | |
| 1048 | + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | |
| 1049 | + .fsp_msg = ddr_dram_fsp_msg, | |
| 1050 | + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | |
| 1051 | + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | |
| 1052 | + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | |
| 1053 | + .ddrphy_pie = ddr_phy_pie, | |
| 1054 | + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | |
| 1055 | + .fsp_table = { 2400, 1066, }, | |
| 1056 | +}; |
board/freescale/imx8mm_ab2/imx8mm_ab2.c
| ... | ... | @@ -14,6 +14,8 @@ |
| 14 | 14 | #include <asm/arch/clock.h> |
| 15 | 15 | #ifdef CONFIG_TARGET_IMX8MM_AB2 |
| 16 | 16 | #include <asm/arch/imx8mm_pins.h> |
| 17 | +#else | |
| 18 | +#include <asm/arch/imx8mn_pins.h> | |
| 17 | 19 | #endif |
| 18 | 20 | #include <asm/arch/sys_proto.h> |
| 19 | 21 | #include <asm-generic/gpio.h> |
| ... | ... | @@ -49,6 +51,25 @@ |
| 49 | 51 | }; |
| 50 | 52 | #endif |
| 51 | 53 | |
| 54 | +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) | |
| 55 | +static iomux_v3_cfg_t const uart_pads[] = { | |
| 56 | + IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 57 | + IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 58 | +}; | |
| 59 | + | |
| 60 | +static iomux_v3_cfg_t const wdog_pads[] = { | |
| 61 | + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), | |
| 62 | +}; | |
| 63 | + | |
| 64 | +static iomux_v3_cfg_t const pwr_en_5v0[] = { | |
| 65 | + IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
| 66 | +}; | |
| 67 | + | |
| 68 | +static iomux_v3_cfg_t const pwr_en_ana[] = { | |
| 69 | + IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
| 70 | +}; | |
| 71 | +#endif | |
| 72 | + | |
| 52 | 73 | #ifdef CONFIG_NAND_MXS |
| 53 | 74 | static void setup_gpmi_nand(void) |
| 54 | 75 | { |
| 55 | 76 | |
| ... | ... | @@ -118,7 +139,11 @@ |
| 118 | 139 | #endif |
| 119 | 140 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 120 | 141 | env_set("board_name", "AB2"); |
| 142 | +#ifdef CONFIG_TARGET_IMX8MM_AB2 | |
| 121 | 143 | env_set("board_rev", "iMX8MM"); |
| 144 | +#else | |
| 145 | + env_set("board_rev", "iMX8MN"); | |
| 146 | +#endif | |
| 122 | 147 | #endif |
| 123 | 148 | return 0; |
| 124 | 149 | } |
board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c
Changes suppressed. Click to show
| 1 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 2 | +/* | |
| 3 | + * Copyright 2019 NXP | |
| 4 | + * | |
| 5 | + * Generated code from MX8M_DDR_tool | |
| 6 | + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#include <linux/kernel.h> | |
| 10 | +#include <asm/arch/ddr.h> | |
| 11 | + | |
| 12 | +struct dram_cfg_param ddr_ddrc_cfg[] = { | |
| 13 | + {0x3d400020, 0x00000213}, | |
| 14 | + {0x3d400024, 0x0003e800}, | |
| 15 | + {0x3d400030, 0x00000120}, | |
| 16 | + {0x3d400000, 0xa3080020}, | |
| 17 | + {0x3d400064, 0x006100e0}, | |
| 18 | + {0x3d4000d0, 0xc003061c}, | |
| 19 | + {0x3d4000d4, 0x009e0000}, | |
| 20 | + {0x3d4000dc, 0x00d4002d}, | |
| 21 | + {0x3d4000e0, 0x00310000}, | |
| 22 | + {0x3d4000e8, 0x0066004d}, | |
| 23 | + {0x3d4000ec, 0x0016004a}, | |
| 24 | + {0x3d400100, 0x1a201b22}, | |
| 25 | + {0x3d400104, 0x00060633}, | |
| 26 | + {0x3d40010c, 0x00c0c000}, | |
| 27 | + {0x3d400110, 0x0f04080f}, | |
| 28 | + {0x3d400114, 0x02040c0c}, | |
| 29 | + {0x3d400118, 0x01010007}, | |
| 30 | + {0x3d40011c, 0x00000401}, | |
| 31 | + {0x3d400130, 0x00020600}, | |
| 32 | + {0x3d400134, 0x0c100002}, | |
| 33 | + {0x3d400138, 0x000000e6}, | |
| 34 | + {0x3d400144, 0x00a00050}, | |
| 35 | + {0x3d400180, 0x03200018}, | |
| 36 | + {0x3d400184, 0x028061a8}, | |
| 37 | + {0x3d400188, 0x00000000}, | |
| 38 | + {0x3d400190, 0x0497820a}, | |
| 39 | + {0x3d4001b4, 0x0000170a}, | |
| 40 | + {0x3d400108, 0x070e1617}, | |
| 41 | + {0x3d4001c0, 0x00000001}, | |
| 42 | + {0x3d400194, 0x00080303}, | |
| 43 | + {0x3d4001a0, 0xe0400018}, | |
| 44 | + {0x3d4001a4, 0x00df00e4}, | |
| 45 | + {0x3d4001a8, 0x80000000}, | |
| 46 | + {0x3d4001b0, 0x00000011}, | |
| 47 | + {0x3d4001c4, 0x00000001}, | |
| 48 | + {0x3d4000f4, 0x00000c99}, | |
| 49 | + {0x3d400200, 0x00000017}, | |
| 50 | + {0x3d400204, 0x00080808}, | |
| 51 | + {0x3d400208, 0x00000000}, | |
| 52 | + {0x3d40020c, 0x00000000}, | |
| 53 | + {0x3d400210, 0x00001f1f}, | |
| 54 | + {0x3d400214, 0x07070707}, | |
| 55 | + {0x3d400218, 0x07070707}, | |
| 56 | + {0x3d40021c, 0x00000f0f}, | |
| 57 | + {0x3d400250, 0x29001701}, | |
| 58 | + {0x3d400254, 0x0000002c}, | |
| 59 | + {0x3d40025c, 0x04000030}, | |
| 60 | + {0x3d400264, 0x900093e7}, | |
| 61 | + {0x3d40026c, 0x20005574}, | |
| 62 | + {0x3d400400, 0x00000111}, | |
| 63 | + {0x3d400408, 0x000072ff}, | |
| 64 | + {0x3d400494, 0x02100e07}, | |
| 65 | + {0x3d400498, 0x00620096}, | |
| 66 | + {0x3d40049c, 0x01100e07}, | |
| 67 | + {0x3d4004a0, 0x00c8012c}, | |
| 68 | + {0x3d402020, 0x00000011}, | |
| 69 | + {0x3d402024, 0x00007d00}, | |
| 70 | + {0x3d402050, 0x0020d040}, | |
| 71 | + {0x3d402064, 0x000c001d}, | |
| 72 | + {0x3d4020f4, 0x00000c99}, | |
| 73 | + {0x3d402100, 0x0a040305}, | |
| 74 | + {0x3d402104, 0x00030407}, | |
| 75 | + {0x3d402108, 0x0203060b}, | |
| 76 | + {0x3d40210c, 0x00505000}, | |
| 77 | + {0x3d402110, 0x02040202}, | |
| 78 | + {0x3d402114, 0x02030202}, | |
| 79 | + {0x3d402118, 0x01010004}, | |
| 80 | + {0x3d40211c, 0x00000301}, | |
| 81 | + {0x3d402130, 0x00020300}, | |
| 82 | + {0x3d402134, 0x0a100002}, | |
| 83 | + {0x3d402138, 0x0000001d}, | |
| 84 | + {0x3d402144, 0x0014000a}, | |
| 85 | + {0x3d402180, 0x00650004}, | |
| 86 | + {0x3d402190, 0x03818200}, | |
| 87 | + {0x3d402194, 0x00080303}, | |
| 88 | + {0x3d4021b4, 0x00000100}, | |
| 89 | + {0x3d4020dc, 0x00840000}, | |
| 90 | + {0x3d4020e0, 0x00310000}, | |
| 91 | + {0x3d4020e8, 0x0066004d}, | |
| 92 | + {0x3d4020ec, 0x0016004a}, | |
| 93 | + {0x3d403020, 0x00000011}, | |
| 94 | + {0x3d403024, 0x00001f40}, | |
| 95 | + {0x3d403050, 0x0020d040}, | |
| 96 | + {0x3d403064, 0x00030007}, | |
| 97 | + {0x3d4030f4, 0x00000c99}, | |
| 98 | + {0x3d403100, 0x0a010102}, | |
| 99 | + {0x3d403104, 0x00030404}, | |
| 100 | + {0x3d403108, 0x0203060b}, | |
| 101 | + {0x3d40310c, 0x00505000}, | |
| 102 | + {0x3d403110, 0x02040202}, | |
| 103 | + {0x3d403114, 0x02030202}, | |
| 104 | + {0x3d403118, 0x01010004}, | |
| 105 | + {0x3d40311c, 0x00000301}, | |
| 106 | + {0x3d403130, 0x00020300}, | |
| 107 | + {0x3d403134, 0x0a100002}, | |
| 108 | + {0x3d403138, 0x00000008}, | |
| 109 | + {0x3d403144, 0x00050003}, | |
| 110 | + {0x3d403180, 0x00190004}, | |
| 111 | + {0x3d403190, 0x03818200}, | |
| 112 | + {0x3d403194, 0x00080303}, | |
| 113 | + {0x3d4031b4, 0x00000100}, | |
| 114 | + {0x3d4030dc, 0x00840000}, | |
| 115 | + {0x3d4030e0, 0x00310000}, | |
| 116 | + {0x3d4030e8, 0x0066004d}, | |
| 117 | + {0x3d4030ec, 0x0016004a}, | |
| 118 | + | |
| 119 | + /* default boot point */ | |
| 120 | + { 0x3d400028, 0x0 }, | |
| 121 | +}; | |
| 122 | + | |
| 123 | +/* PHY Initialize Configuration */ | |
| 124 | +struct dram_cfg_param ddr_ddrphy_cfg[] = { | |
| 125 | + {0x000100a0, 0x00000000}, | |
| 126 | + {0x000100a1, 0x00000001}, | |
| 127 | + {0x000100a2, 0x00000002}, | |
| 128 | + {0x000100a3, 0x00000003}, | |
| 129 | + {0x000100a4, 0x00000004}, | |
| 130 | + {0x000100a5, 0x00000005}, | |
| 131 | + {0x000100a6, 0x00000006}, | |
| 132 | + {0x000100a7, 0x00000007}, | |
| 133 | + {0x000110a0, 0x00000000}, | |
| 134 | + {0x000110a1, 0x00000001}, | |
| 135 | + {0x000110a2, 0x00000003}, | |
| 136 | + {0x000110a3, 0x00000004}, | |
| 137 | + {0x000110a4, 0x00000005}, | |
| 138 | + {0x000110a5, 0x00000002}, | |
| 139 | + {0x000110a6, 0x00000007}, | |
| 140 | + {0x000110a7, 0x00000006}, | |
| 141 | + {0x0001005f, 0x0000015f}, | |
| 142 | + {0x0001015f, 0x0000015f}, | |
| 143 | + {0x0001105f, 0x0000015f}, | |
| 144 | + {0x0001115f, 0x0000015f}, | |
| 145 | + {0x0011005f, 0x0000015f}, | |
| 146 | + {0x0011015f, 0x0000015f}, | |
| 147 | + {0x0011105f, 0x0000015f}, | |
| 148 | + {0x0011115f, 0x0000015f}, | |
| 149 | + {0x0021005f, 0x0000015f}, | |
| 150 | + {0x0021015f, 0x0000015f}, | |
| 151 | + {0x0021105f, 0x0000015f}, | |
| 152 | + {0x0021115f, 0x0000015f}, | |
| 153 | + {0x00000055, 0x0000016f}, | |
| 154 | + {0x00001055, 0x0000016f}, | |
| 155 | + {0x00002055, 0x0000016f}, | |
| 156 | + {0x00003055, 0x0000016f}, | |
| 157 | + {0x00004055, 0x0000016f}, | |
| 158 | + {0x00005055, 0x0000016f}, | |
| 159 | + {0x00006055, 0x0000016f}, | |
| 160 | + {0x00007055, 0x0000016f}, | |
| 161 | + {0x00008055, 0x0000016f}, | |
| 162 | + {0x00009055, 0x0000016f}, | |
| 163 | + {0x000200c5, 0x00000019}, | |
| 164 | + {0x001200c5, 0x00000007}, | |
| 165 | + {0x002200c5, 0x00000007}, | |
| 166 | + {0x0002002e, 0x00000002}, | |
| 167 | + {0x0012002e, 0x00000002}, | |
| 168 | + {0x0022002e, 0x00000002}, | |
| 169 | + {0x00090204, 0x00000000}, | |
| 170 | + {0x00190204, 0x00000000}, | |
| 171 | + {0x00290204, 0x00000000}, | |
| 172 | + {0x00020024, 0x000001a3}, | |
| 173 | + {0x0002003a, 0x00000002}, | |
| 174 | + {0x0002007d, 0x00000212}, | |
| 175 | + {0x0002007c, 0x00000061}, | |
| 176 | + {0x00120024, 0x000001a3}, | |
| 177 | + {0x0002003a, 0x00000002}, | |
| 178 | + {0x0012007d, 0x00000212}, | |
| 179 | + {0x0012007c, 0x00000061}, | |
| 180 | + {0x00220024, 0x000001a3}, | |
| 181 | + {0x0002003a, 0x00000002}, | |
| 182 | + {0x0022007d, 0x00000212}, | |
| 183 | + {0x0022007c, 0x00000061}, | |
| 184 | + {0x00020056, 0x00000003}, | |
| 185 | + {0x00120056, 0x00000003}, | |
| 186 | + {0x00220056, 0x00000003}, | |
| 187 | + {0x0001004d, 0x00000f80}, | |
| 188 | + {0x0001014d, 0x00000f80}, | |
| 189 | + {0x0001104d, 0x00000f80}, | |
| 190 | + {0x0001114d, 0x00000f80}, | |
| 191 | + {0x0011004d, 0x00000f80}, | |
| 192 | + {0x0011014d, 0x00000f80}, | |
| 193 | + {0x0011104d, 0x00000f80}, | |
| 194 | + {0x0011114d, 0x00000f80}, | |
| 195 | + {0x0021004d, 0x00000f80}, | |
| 196 | + {0x0021014d, 0x00000f80}, | |
| 197 | + {0x0021104d, 0x00000f80}, | |
| 198 | + {0x0021114d, 0x00000f80}, | |
| 199 | + {0x00010049, 0x00000fbe}, | |
| 200 | + {0x00010149, 0x00000fbe}, | |
| 201 | + {0x00011049, 0x00000fbe}, | |
| 202 | + {0x00011149, 0x00000fbe}, | |
| 203 | + {0x00110049, 0x00000fbe}, | |
| 204 | + {0x00110149, 0x00000fbe}, | |
| 205 | + {0x00111049, 0x00000fbe}, | |
| 206 | + {0x00111149, 0x00000fbe}, | |
| 207 | + {0x00210049, 0x00000fbe}, | |
| 208 | + {0x00210149, 0x00000fbe}, | |
| 209 | + {0x00211049, 0x00000fbe}, | |
| 210 | + {0x00211149, 0x00000fbe}, | |
| 211 | + {0x00000043, 0x00000063}, | |
| 212 | + {0x00001043, 0x00000063}, | |
| 213 | + {0x00002043, 0x00000063}, | |
| 214 | + {0x00003043, 0x00000063}, | |
| 215 | + {0x00004043, 0x00000063}, | |
| 216 | + {0x00005043, 0x00000063}, | |
| 217 | + {0x00006043, 0x00000063}, | |
| 218 | + {0x00007043, 0x00000063}, | |
| 219 | + {0x00008043, 0x00000063}, | |
| 220 | + {0x00009043, 0x00000063}, | |
| 221 | + {0x00020018, 0x00000001}, | |
| 222 | + {0x00020075, 0x00000004}, | |
| 223 | + {0x00020050, 0x00000000}, | |
| 224 | + {0x00020008, 0x00000320}, | |
| 225 | + {0x00120008, 0x00000064}, | |
| 226 | + {0x00220008, 0x00000019}, | |
| 227 | + {0x00020088, 0x00000009}, | |
| 228 | + {0x000200b2, 0x000000dc}, | |
| 229 | + {0x00010043, 0x000005a1}, | |
| 230 | + {0x00010143, 0x000005a1}, | |
| 231 | + {0x00011043, 0x000005a1}, | |
| 232 | + {0x00011143, 0x000005a1}, | |
| 233 | + {0x001200b2, 0x000000dc}, | |
| 234 | + {0x00110043, 0x000005a1}, | |
| 235 | + {0x00110143, 0x000005a1}, | |
| 236 | + {0x00111043, 0x000005a1}, | |
| 237 | + {0x00111143, 0x000005a1}, | |
| 238 | + {0x002200b2, 0x000000dc}, | |
| 239 | + {0x00210043, 0x000005a1}, | |
| 240 | + {0x00210143, 0x000005a1}, | |
| 241 | + {0x00211043, 0x000005a1}, | |
| 242 | + {0x00211143, 0x000005a1}, | |
| 243 | + {0x000200fa, 0x00000001}, | |
| 244 | + {0x001200fa, 0x00000001}, | |
| 245 | + {0x002200fa, 0x00000001}, | |
| 246 | + {0x00020019, 0x00000001}, | |
| 247 | + {0x00120019, 0x00000001}, | |
| 248 | + {0x00220019, 0x00000001}, | |
| 249 | + {0x000200f0, 0x00000660}, | |
| 250 | + {0x000200f1, 0x00000000}, | |
| 251 | + {0x000200f2, 0x00004444}, | |
| 252 | + {0x000200f3, 0x00008888}, | |
| 253 | + {0x000200f4, 0x00005665}, | |
| 254 | + {0x000200f5, 0x00000000}, | |
| 255 | + {0x000200f6, 0x00000000}, | |
| 256 | + {0x000200f7, 0x0000f000}, | |
| 257 | + {0x0001004a, 0x00000500}, | |
| 258 | + {0x0001104a, 0x00000500}, | |
| 259 | + {0x00020025, 0x00000000}, | |
| 260 | + {0x0002002d, 0x00000000}, | |
| 261 | + {0x0012002d, 0x00000000}, | |
| 262 | + {0x0022002d, 0x00000000}, | |
| 263 | + {0x0002002c, 0x00000000}, | |
| 264 | + {0x000200c7, 0x00000021}, | |
| 265 | + {0x000200ca, 0x00000024}, | |
| 266 | + {0x000200cc, 0x000001f7}, | |
| 267 | + {0x001200c7, 0x00000021}, | |
| 268 | + {0x001200ca, 0x00000024}, | |
| 269 | + {0x001200cc, 0x000001f7}, | |
| 270 | + {0x002200c7, 0x00000021}, | |
| 271 | + {0x002200ca, 0x00000024}, | |
| 272 | + {0x002200cc, 0x000001f7}, | |
| 273 | +}; | |
| 274 | + | |
| 275 | +/* ddr phy trained csr */ | |
| 276 | +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | |
| 277 | + {0x0200b2, 0x0}, | |
| 278 | + {0x1200b2, 0x0}, | |
| 279 | + {0x2200b2, 0x0}, | |
| 280 | + {0x0200cb, 0x0}, | |
| 281 | + {0x010043, 0x0}, | |
| 282 | + {0x110043, 0x0}, | |
| 283 | + {0x210043, 0x0}, | |
| 284 | + {0x010143, 0x0}, | |
| 285 | + {0x110143, 0x0}, | |
| 286 | + {0x210143, 0x0}, | |
| 287 | + {0x011043, 0x0}, | |
| 288 | + {0x111043, 0x0}, | |
| 289 | + {0x211043, 0x0}, | |
| 290 | + {0x011143, 0x0}, | |
| 291 | + {0x111143, 0x0}, | |
| 292 | + {0x211143, 0x0}, | |
| 293 | + {0x000080, 0x0}, | |
| 294 | + {0x100080, 0x0}, | |
| 295 | + {0x200080, 0x0}, | |
| 296 | + {0x001080, 0x0}, | |
| 297 | + {0x101080, 0x0}, | |
| 298 | + {0x201080, 0x0}, | |
| 299 | + {0x002080, 0x0}, | |
| 300 | + {0x102080, 0x0}, | |
| 301 | + {0x202080, 0x0}, | |
| 302 | + {0x003080, 0x0}, | |
| 303 | + {0x103080, 0x0}, | |
| 304 | + {0x203080, 0x0}, | |
| 305 | + {0x004080, 0x0}, | |
| 306 | + {0x104080, 0x0}, | |
| 307 | + {0x204080, 0x0}, | |
| 308 | + {0x005080, 0x0}, | |
| 309 | + {0x105080, 0x0}, | |
| 310 | + {0x205080, 0x0}, | |
| 311 | + {0x006080, 0x0}, | |
| 312 | + {0x106080, 0x0}, | |
| 313 | + {0x206080, 0x0}, | |
| 314 | + {0x007080, 0x0}, | |
| 315 | + {0x107080, 0x0}, | |
| 316 | + {0x207080, 0x0}, | |
| 317 | + {0x008080, 0x0}, | |
| 318 | + {0x108080, 0x0}, | |
| 319 | + {0x208080, 0x0}, | |
| 320 | + {0x009080, 0x0}, | |
| 321 | + {0x109080, 0x0}, | |
| 322 | + {0x209080, 0x0}, | |
| 323 | + {0x010080, 0x0}, | |
| 324 | + {0x110080, 0x0}, | |
| 325 | + {0x210080, 0x0}, | |
| 326 | + {0x010180, 0x0}, | |
| 327 | + {0x110180, 0x0}, | |
| 328 | + {0x210180, 0x0}, | |
| 329 | + {0x011080, 0x0}, | |
| 330 | + {0x111080, 0x0}, | |
| 331 | + {0x211080, 0x0}, | |
| 332 | + {0x011180, 0x0}, | |
| 333 | + {0x111180, 0x0}, | |
| 334 | + {0x211180, 0x0}, | |
| 335 | + {0x010081, 0x0}, | |
| 336 | + {0x110081, 0x0}, | |
| 337 | + {0x210081, 0x0}, | |
| 338 | + {0x010181, 0x0}, | |
| 339 | + {0x110181, 0x0}, | |
| 340 | + {0x210181, 0x0}, | |
| 341 | + {0x011081, 0x0}, | |
| 342 | + {0x111081, 0x0}, | |
| 343 | + {0x211081, 0x0}, | |
| 344 | + {0x011181, 0x0}, | |
| 345 | + {0x111181, 0x0}, | |
| 346 | + {0x211181, 0x0}, | |
| 347 | + {0x0100d0, 0x0}, | |
| 348 | + {0x1100d0, 0x0}, | |
| 349 | + {0x2100d0, 0x0}, | |
| 350 | + {0x0101d0, 0x0}, | |
| 351 | + {0x1101d0, 0x0}, | |
| 352 | + {0x2101d0, 0x0}, | |
| 353 | + {0x0110d0, 0x0}, | |
| 354 | + {0x1110d0, 0x0}, | |
| 355 | + {0x2110d0, 0x0}, | |
| 356 | + {0x0111d0, 0x0}, | |
| 357 | + {0x1111d0, 0x0}, | |
| 358 | + {0x2111d0, 0x0}, | |
| 359 | + {0x0100d1, 0x0}, | |
| 360 | + {0x1100d1, 0x0}, | |
| 361 | + {0x2100d1, 0x0}, | |
| 362 | + {0x0101d1, 0x0}, | |
| 363 | + {0x1101d1, 0x0}, | |
| 364 | + {0x2101d1, 0x0}, | |
| 365 | + {0x0110d1, 0x0}, | |
| 366 | + {0x1110d1, 0x0}, | |
| 367 | + {0x2110d1, 0x0}, | |
| 368 | + {0x0111d1, 0x0}, | |
| 369 | + {0x1111d1, 0x0}, | |
| 370 | + {0x2111d1, 0x0}, | |
| 371 | + {0x010068, 0x0}, | |
| 372 | + {0x010168, 0x0}, | |
| 373 | + {0x010268, 0x0}, | |
| 374 | + {0x010368, 0x0}, | |
| 375 | + {0x010468, 0x0}, | |
| 376 | + {0x010568, 0x0}, | |
| 377 | + {0x010668, 0x0}, | |
| 378 | + {0x010768, 0x0}, | |
| 379 | + {0x010868, 0x0}, | |
| 380 | + {0x011068, 0x0}, | |
| 381 | + {0x011168, 0x0}, | |
| 382 | + {0x011268, 0x0}, | |
| 383 | + {0x011368, 0x0}, | |
| 384 | + {0x011468, 0x0}, | |
| 385 | + {0x011568, 0x0}, | |
| 386 | + {0x011668, 0x0}, | |
| 387 | + {0x011768, 0x0}, | |
| 388 | + {0x011868, 0x0}, | |
| 389 | + {0x010069, 0x0}, | |
| 390 | + {0x010169, 0x0}, | |
| 391 | + {0x010269, 0x0}, | |
| 392 | + {0x010369, 0x0}, | |
| 393 | + {0x010469, 0x0}, | |
| 394 | + {0x010569, 0x0}, | |
| 395 | + {0x010669, 0x0}, | |
| 396 | + {0x010769, 0x0}, | |
| 397 | + {0x010869, 0x0}, | |
| 398 | + {0x011069, 0x0}, | |
| 399 | + {0x011169, 0x0}, | |
| 400 | + {0x011269, 0x0}, | |
| 401 | + {0x011369, 0x0}, | |
| 402 | + {0x011469, 0x0}, | |
| 403 | + {0x011569, 0x0}, | |
| 404 | + {0x011669, 0x0}, | |
| 405 | + {0x011769, 0x0}, | |
| 406 | + {0x011869, 0x0}, | |
| 407 | + {0x01008c, 0x0}, | |
| 408 | + {0x11008c, 0x0}, | |
| 409 | + {0x21008c, 0x0}, | |
| 410 | + {0x01018c, 0x0}, | |
| 411 | + {0x11018c, 0x0}, | |
| 412 | + {0x21018c, 0x0}, | |
| 413 | + {0x01108c, 0x0}, | |
| 414 | + {0x11108c, 0x0}, | |
| 415 | + {0x21108c, 0x0}, | |
| 416 | + {0x01118c, 0x0}, | |
| 417 | + {0x11118c, 0x0}, | |
| 418 | + {0x21118c, 0x0}, | |
| 419 | + {0x01008d, 0x0}, | |
| 420 | + {0x11008d, 0x0}, | |
| 421 | + {0x21008d, 0x0}, | |
| 422 | + {0x01018d, 0x0}, | |
| 423 | + {0x11018d, 0x0}, | |
| 424 | + {0x21018d, 0x0}, | |
| 425 | + {0x01108d, 0x0}, | |
| 426 | + {0x11108d, 0x0}, | |
| 427 | + {0x21108d, 0x0}, | |
| 428 | + {0x01118d, 0x0}, | |
| 429 | + {0x11118d, 0x0}, | |
| 430 | + {0x21118d, 0x0}, | |
| 431 | + {0x0100c0, 0x0}, | |
| 432 | + {0x1100c0, 0x0}, | |
| 433 | + {0x2100c0, 0x0}, | |
| 434 | + {0x0101c0, 0x0}, | |
| 435 | + {0x1101c0, 0x0}, | |
| 436 | + {0x2101c0, 0x0}, | |
| 437 | + {0x0102c0, 0x0}, | |
| 438 | + {0x1102c0, 0x0}, | |
| 439 | + {0x2102c0, 0x0}, | |
| 440 | + {0x0103c0, 0x0}, | |
| 441 | + {0x1103c0, 0x0}, | |
| 442 | + {0x2103c0, 0x0}, | |
| 443 | + {0x0104c0, 0x0}, | |
| 444 | + {0x1104c0, 0x0}, | |
| 445 | + {0x2104c0, 0x0}, | |
| 446 | + {0x0105c0, 0x0}, | |
| 447 | + {0x1105c0, 0x0}, | |
| 448 | + {0x2105c0, 0x0}, | |
| 449 | + {0x0106c0, 0x0}, | |
| 450 | + {0x1106c0, 0x0}, | |
| 451 | + {0x2106c0, 0x0}, | |
| 452 | + {0x0107c0, 0x0}, | |
| 453 | + {0x1107c0, 0x0}, | |
| 454 | + {0x2107c0, 0x0}, | |
| 455 | + {0x0108c0, 0x0}, | |
| 456 | + {0x1108c0, 0x0}, | |
| 457 | + {0x2108c0, 0x0}, | |
| 458 | + {0x0110c0, 0x0}, | |
| 459 | + {0x1110c0, 0x0}, | |
| 460 | + {0x2110c0, 0x0}, | |
| 461 | + {0x0111c0, 0x0}, | |
| 462 | + {0x1111c0, 0x0}, | |
| 463 | + {0x2111c0, 0x0}, | |
| 464 | + {0x0112c0, 0x0}, | |
| 465 | + {0x1112c0, 0x0}, | |
| 466 | + {0x2112c0, 0x0}, | |
| 467 | + {0x0113c0, 0x0}, | |
| 468 | + {0x1113c0, 0x0}, | |
| 469 | + {0x2113c0, 0x0}, | |
| 470 | + {0x0114c0, 0x0}, | |
| 471 | + {0x1114c0, 0x0}, | |
| 472 | + {0x2114c0, 0x0}, | |
| 473 | + {0x0115c0, 0x0}, | |
| 474 | + {0x1115c0, 0x0}, | |
| 475 | + {0x2115c0, 0x0}, | |
| 476 | + {0x0116c0, 0x0}, | |
| 477 | + {0x1116c0, 0x0}, | |
| 478 | + {0x2116c0, 0x0}, | |
| 479 | + {0x0117c0, 0x0}, | |
| 480 | + {0x1117c0, 0x0}, | |
| 481 | + {0x2117c0, 0x0}, | |
| 482 | + {0x0118c0, 0x0}, | |
| 483 | + {0x1118c0, 0x0}, | |
| 484 | + {0x2118c0, 0x0}, | |
| 485 | + {0x0100c1, 0x0}, | |
| 486 | + {0x1100c1, 0x0}, | |
| 487 | + {0x2100c1, 0x0}, | |
| 488 | + {0x0101c1, 0x0}, | |
| 489 | + {0x1101c1, 0x0}, | |
| 490 | + {0x2101c1, 0x0}, | |
| 491 | + {0x0102c1, 0x0}, | |
| 492 | + {0x1102c1, 0x0}, | |
| 493 | + {0x2102c1, 0x0}, | |
| 494 | + {0x0103c1, 0x0}, | |
| 495 | + {0x1103c1, 0x0}, | |
| 496 | + {0x2103c1, 0x0}, | |
| 497 | + {0x0104c1, 0x0}, | |
| 498 | + {0x1104c1, 0x0}, | |
| 499 | + {0x2104c1, 0x0}, | |
| 500 | + {0x0105c1, 0x0}, | |
| 501 | + {0x1105c1, 0x0}, | |
| 502 | + {0x2105c1, 0x0}, | |
| 503 | + {0x0106c1, 0x0}, | |
| 504 | + {0x1106c1, 0x0}, | |
| 505 | + {0x2106c1, 0x0}, | |
| 506 | + {0x0107c1, 0x0}, | |
| 507 | + {0x1107c1, 0x0}, | |
| 508 | + {0x2107c1, 0x0}, | |
| 509 | + {0x0108c1, 0x0}, | |
| 510 | + {0x1108c1, 0x0}, | |
| 511 | + {0x2108c1, 0x0}, | |
| 512 | + {0x0110c1, 0x0}, | |
| 513 | + {0x1110c1, 0x0}, | |
| 514 | + {0x2110c1, 0x0}, | |
| 515 | + {0x0111c1, 0x0}, | |
| 516 | + {0x1111c1, 0x0}, | |
| 517 | + {0x2111c1, 0x0}, | |
| 518 | + {0x0112c1, 0x0}, | |
| 519 | + {0x1112c1, 0x0}, | |
| 520 | + {0x2112c1, 0x0}, | |
| 521 | + {0x0113c1, 0x0}, | |
| 522 | + {0x1113c1, 0x0}, | |
| 523 | + {0x2113c1, 0x0}, | |
| 524 | + {0x0114c1, 0x0}, | |
| 525 | + {0x1114c1, 0x0}, | |
| 526 | + {0x2114c1, 0x0}, | |
| 527 | + {0x0115c1, 0x0}, | |
| 528 | + {0x1115c1, 0x0}, | |
| 529 | + {0x2115c1, 0x0}, | |
| 530 | + {0x0116c1, 0x0}, | |
| 531 | + {0x1116c1, 0x0}, | |
| 532 | + {0x2116c1, 0x0}, | |
| 533 | + {0x0117c1, 0x0}, | |
| 534 | + {0x1117c1, 0x0}, | |
| 535 | + {0x2117c1, 0x0}, | |
| 536 | + {0x0118c1, 0x0}, | |
| 537 | + {0x1118c1, 0x0}, | |
| 538 | + {0x2118c1, 0x0}, | |
| 539 | + {0x010020, 0x0}, | |
| 540 | + {0x110020, 0x0}, | |
| 541 | + {0x210020, 0x0}, | |
| 542 | + {0x011020, 0x0}, | |
| 543 | + {0x111020, 0x0}, | |
| 544 | + {0x211020, 0x0}, | |
| 545 | + {0x020072, 0x0}, | |
| 546 | + {0x020073, 0x0}, | |
| 547 | + {0x020074, 0x0}, | |
| 548 | + {0x0100aa, 0x0}, | |
| 549 | + {0x0110aa, 0x0}, | |
| 550 | + {0x020010, 0x0}, | |
| 551 | + {0x120010, 0x0}, | |
| 552 | + {0x220010, 0x0}, | |
| 553 | + {0x020011, 0x0}, | |
| 554 | + {0x120011, 0x0}, | |
| 555 | + {0x220011, 0x0}, | |
| 556 | + {0x0100ae, 0x0}, | |
| 557 | + {0x1100ae, 0x0}, | |
| 558 | + {0x2100ae, 0x0}, | |
| 559 | + {0x0100af, 0x0}, | |
| 560 | + {0x1100af, 0x0}, | |
| 561 | + {0x2100af, 0x0}, | |
| 562 | + {0x0110ae, 0x0}, | |
| 563 | + {0x1110ae, 0x0}, | |
| 564 | + {0x2110ae, 0x0}, | |
| 565 | + {0x0110af, 0x0}, | |
| 566 | + {0x1110af, 0x0}, | |
| 567 | + {0x2110af, 0x0}, | |
| 568 | + {0x020020, 0x0}, | |
| 569 | + {0x120020, 0x0}, | |
| 570 | + {0x220020, 0x0}, | |
| 571 | + {0x0100a0, 0x0}, | |
| 572 | + {0x0100a1, 0x0}, | |
| 573 | + {0x0100a2, 0x0}, | |
| 574 | + {0x0100a3, 0x0}, | |
| 575 | + {0x0100a4, 0x0}, | |
| 576 | + {0x0100a5, 0x0}, | |
| 577 | + {0x0100a6, 0x0}, | |
| 578 | + {0x0100a7, 0x0}, | |
| 579 | + {0x0110a0, 0x0}, | |
| 580 | + {0x0110a1, 0x0}, | |
| 581 | + {0x0110a2, 0x0}, | |
| 582 | + {0x0110a3, 0x0}, | |
| 583 | + {0x0110a4, 0x0}, | |
| 584 | + {0x0110a5, 0x0}, | |
| 585 | + {0x0110a6, 0x0}, | |
| 586 | + {0x0110a7, 0x0}, | |
| 587 | + {0x02007c, 0x0}, | |
| 588 | + {0x12007c, 0x0}, | |
| 589 | + {0x22007c, 0x0}, | |
| 590 | + {0x02007d, 0x0}, | |
| 591 | + {0x12007d, 0x0}, | |
| 592 | + {0x22007d, 0x0}, | |
| 593 | + {0x0400fd, 0x0}, | |
| 594 | + {0x0400c0, 0x0}, | |
| 595 | + {0x090201, 0x0}, | |
| 596 | + {0x190201, 0x0}, | |
| 597 | + {0x290201, 0x0}, | |
| 598 | + {0x090202, 0x0}, | |
| 599 | + {0x190202, 0x0}, | |
| 600 | + {0x290202, 0x0}, | |
| 601 | + {0x090203, 0x0}, | |
| 602 | + {0x190203, 0x0}, | |
| 603 | + {0x290203, 0x0}, | |
| 604 | + {0x090204, 0x0}, | |
| 605 | + {0x190204, 0x0}, | |
| 606 | + {0x290204, 0x0}, | |
| 607 | + {0x090205, 0x0}, | |
| 608 | + {0x190205, 0x0}, | |
| 609 | + {0x290205, 0x0}, | |
| 610 | + {0x090206, 0x0}, | |
| 611 | + {0x190206, 0x0}, | |
| 612 | + {0x290206, 0x0}, | |
| 613 | + {0x090207, 0x0}, | |
| 614 | + {0x190207, 0x0}, | |
| 615 | + {0x290207, 0x0}, | |
| 616 | + {0x090208, 0x0}, | |
| 617 | + {0x190208, 0x0}, | |
| 618 | + {0x290208, 0x0}, | |
| 619 | + {0x010062, 0x0}, | |
| 620 | + {0x010162, 0x0}, | |
| 621 | + {0x010262, 0x0}, | |
| 622 | + {0x010362, 0x0}, | |
| 623 | + {0x010462, 0x0}, | |
| 624 | + {0x010562, 0x0}, | |
| 625 | + {0x010662, 0x0}, | |
| 626 | + {0x010762, 0x0}, | |
| 627 | + {0x010862, 0x0}, | |
| 628 | + {0x011062, 0x0}, | |
| 629 | + {0x011162, 0x0}, | |
| 630 | + {0x011262, 0x0}, | |
| 631 | + {0x011362, 0x0}, | |
| 632 | + {0x011462, 0x0}, | |
| 633 | + {0x011562, 0x0}, | |
| 634 | + {0x011662, 0x0}, | |
| 635 | + {0x011762, 0x0}, | |
| 636 | + {0x011862, 0x0}, | |
| 637 | + {0x020077, 0x0}, | |
| 638 | + {0x010001, 0x0}, | |
| 639 | + {0x011001, 0x0}, | |
| 640 | + {0x010040, 0x0}, | |
| 641 | + {0x010140, 0x0}, | |
| 642 | + {0x010240, 0x0}, | |
| 643 | + {0x010340, 0x0}, | |
| 644 | + {0x010440, 0x0}, | |
| 645 | + {0x010540, 0x0}, | |
| 646 | + {0x010640, 0x0}, | |
| 647 | + {0x010740, 0x0}, | |
| 648 | + {0x010840, 0x0}, | |
| 649 | + {0x010030, 0x0}, | |
| 650 | + {0x010130, 0x0}, | |
| 651 | + {0x010230, 0x0}, | |
| 652 | + {0x010330, 0x0}, | |
| 653 | + {0x010430, 0x0}, | |
| 654 | + {0x010530, 0x0}, | |
| 655 | + {0x010630, 0x0}, | |
| 656 | + {0x010730, 0x0}, | |
| 657 | + {0x010830, 0x0}, | |
| 658 | + {0x011040, 0x0}, | |
| 659 | + {0x011140, 0x0}, | |
| 660 | + {0x011240, 0x0}, | |
| 661 | + {0x011340, 0x0}, | |
| 662 | + {0x011440, 0x0}, | |
| 663 | + {0x011540, 0x0}, | |
| 664 | + {0x011640, 0x0}, | |
| 665 | + {0x011740, 0x0}, | |
| 666 | + {0x011840, 0x0}, | |
| 667 | + {0x011030, 0x0}, | |
| 668 | + {0x011130, 0x0}, | |
| 669 | + {0x011230, 0x0}, | |
| 670 | + {0x011330, 0x0}, | |
| 671 | + {0x011430, 0x0}, | |
| 672 | + {0x011530, 0x0}, | |
| 673 | + {0x011630, 0x0}, | |
| 674 | + {0x011730, 0x0}, | |
| 675 | + {0x011830, 0x0}, | |
| 676 | +}; | |
| 677 | + | |
| 678 | +/* P0 message block paremeter for training firmware */ | |
| 679 | +struct dram_cfg_param ddr_fsp0_cfg[] = { | |
| 680 | + {0x000d0000, 0x00000000}, | |
| 681 | + {0x00054000, 0x00000000}, | |
| 682 | + {0x00054001, 0x00000000}, | |
| 683 | + {0x00054002, 0x00000000}, | |
| 684 | + {0x00054003, 0x00000c80}, | |
| 685 | + {0x00054004, 0x00000002}, | |
| 686 | + {0x00054005, 0x00000000}, | |
| 687 | + {0x00054006, 0x00000011}, | |
| 688 | + {0x00054007, 0x00000000}, | |
| 689 | + {0x00054008, 0x0000131f}, | |
| 690 | + {0x00054009, 0x000000c8}, | |
| 691 | + {0x0005400a, 0x00000000}, | |
| 692 | + {0x0005400b, 0x00000002}, | |
| 693 | + {0x0005400c, 0x00000000}, | |
| 694 | + {0x0005400d, 0x00000000}, | |
| 695 | + {0x0005400e, 0x00000000}, | |
| 696 | + {0x0005400f, 0x00000100}, | |
| 697 | + {0x00054010, 0x00000000}, | |
| 698 | + {0x00054011, 0x00000000}, | |
| 699 | + {0x00054012, 0x00000310}, | |
| 700 | + {0x00054013, 0x00000000}, | |
| 701 | + {0x00054014, 0x00000000}, | |
| 702 | + {0x00054015, 0x00000000}, | |
| 703 | + {0x00054016, 0x00000000}, | |
| 704 | + {0x00054017, 0x00000000}, | |
| 705 | + {0x00054018, 0x00000000}, | |
| 706 | + {0x00054019, 0x00002dd4}, | |
| 707 | + {0x0005401a, 0x00000031}, | |
| 708 | + {0x0005401b, 0x00004d66}, | |
| 709 | + {0x0005401c, 0x00004a00}, | |
| 710 | + {0x0005401d, 0x00000000}, | |
| 711 | + {0x0005401e, 0x00000016}, | |
| 712 | + {0x0005401f, 0x00002dd4}, | |
| 713 | + {0x00054020, 0x00000031}, | |
| 714 | + {0x00054021, 0x00004d66}, | |
| 715 | + {0x00054022, 0x00004a00}, | |
| 716 | + {0x00054023, 0x00000000}, | |
| 717 | + {0x00054024, 0x0000002e}, | |
| 718 | + {0x00054025, 0x00000000}, | |
| 719 | + {0x00054026, 0x00000000}, | |
| 720 | + {0x00054027, 0x00000000}, | |
| 721 | + {0x00054028, 0x00000000}, | |
| 722 | + {0x00054029, 0x00000000}, | |
| 723 | + {0x0005402a, 0x00000000}, | |
| 724 | + {0x0005402b, 0x00000000}, | |
| 725 | + {0x0005402c, 0x00000000}, | |
| 726 | + {0x0005402d, 0x00000000}, | |
| 727 | + {0x0005402e, 0x00000000}, | |
| 728 | + {0x0005402f, 0x00000000}, | |
| 729 | + {0x00054030, 0x00000000}, | |
| 730 | + {0x00054031, 0x00000000}, | |
| 731 | + {0x00054032, 0x0000d400}, | |
| 732 | + {0x00054033, 0x0000312d}, | |
| 733 | + {0x00054034, 0x00006600}, | |
| 734 | + {0x00054035, 0x0000004d}, | |
| 735 | + {0x00054036, 0x0000004a}, | |
| 736 | + {0x00054037, 0x00001600}, | |
| 737 | + {0x00054038, 0x0000d400}, | |
| 738 | + {0x00054039, 0x0000312d}, | |
| 739 | + {0x0005403a, 0x00006600}, | |
| 740 | + {0x0005403b, 0x0000004d}, | |
| 741 | + {0x0005403c, 0x0000004a}, | |
| 742 | + {0x0005403d, 0x00002e00}, | |
| 743 | + {0x0005403e, 0x00000000}, | |
| 744 | + {0x0005403f, 0x00000000}, | |
| 745 | + {0x00054040, 0x00000000}, | |
| 746 | + {0x00054041, 0x00000000}, | |
| 747 | + {0x00054042, 0x00000000}, | |
| 748 | + {0x00054043, 0x00000000}, | |
| 749 | + {0x00054044, 0x00000000}, | |
| 750 | + {0x000d0000, 0x00000001}, | |
| 751 | +}; | |
| 752 | + | |
| 753 | +/* P1 message block paremeter for training firmware */ | |
| 754 | +struct dram_cfg_param ddr_fsp1_cfg[] = { | |
| 755 | + {0x000d0000, 0x00000000}, | |
| 756 | + {0x00054000, 0x00000000}, | |
| 757 | + {0x00054001, 0x00000000}, | |
| 758 | + {0x00054002, 0x00000101}, | |
| 759 | + {0x00054003, 0x00000190}, | |
| 760 | + {0x00054004, 0x00000002}, | |
| 761 | + {0x00054005, 0x00000000}, | |
| 762 | + {0x00054006, 0x00000011}, | |
| 763 | + {0x00054007, 0x00000000}, | |
| 764 | + {0x00054008, 0x0000121f}, | |
| 765 | + {0x00054009, 0x000000c8}, | |
| 766 | + {0x0005400a, 0x00000000}, | |
| 767 | + {0x0005400b, 0x00000002}, | |
| 768 | + {0x0005400c, 0x00000000}, | |
| 769 | + {0x0005400d, 0x00000000}, | |
| 770 | + {0x0005400e, 0x00000000}, | |
| 771 | + {0x0005400f, 0x00000100}, | |
| 772 | + {0x00054010, 0x00000000}, | |
| 773 | + {0x00054011, 0x00000000}, | |
| 774 | + {0x00054012, 0x00000310}, | |
| 775 | + {0x00054013, 0x00000000}, | |
| 776 | + {0x00054014, 0x00000000}, | |
| 777 | + {0x00054015, 0x00000000}, | |
| 778 | + {0x00054016, 0x00000000}, | |
| 779 | + {0x00054017, 0x00000000}, | |
| 780 | + {0x00054018, 0x00000000}, | |
| 781 | + {0x00054019, 0x00000084}, | |
| 782 | + {0x0005401a, 0x00000031}, | |
| 783 | + {0x0005401b, 0x00004d66}, | |
| 784 | + {0x0005401c, 0x00004a00}, | |
| 785 | + {0x0005401d, 0x00000000}, | |
| 786 | + {0x0005401e, 0x00000016}, | |
| 787 | + {0x0005401f, 0x00000084}, | |
| 788 | + {0x00054020, 0x00000031}, | |
| 789 | + {0x00054021, 0x00004d66}, | |
| 790 | + {0x00054022, 0x00004a00}, | |
| 791 | + {0x00054023, 0x00000000}, | |
| 792 | + {0x00054024, 0x0000002e}, | |
| 793 | + {0x00054025, 0x00000000}, | |
| 794 | + {0x00054026, 0x00000000}, | |
| 795 | + {0x00054027, 0x00000000}, | |
| 796 | + {0x00054028, 0x00000000}, | |
| 797 | + {0x00054029, 0x00000000}, | |
| 798 | + {0x0005402a, 0x00000000}, | |
| 799 | + {0x0005402b, 0x00000000}, | |
| 800 | + {0x0005402c, 0x00000000}, | |
| 801 | + {0x0005402d, 0x00000000}, | |
| 802 | + {0x0005402e, 0x00000000}, | |
| 803 | + {0x0005402f, 0x00000000}, | |
| 804 | + {0x00054030, 0x00000000}, | |
| 805 | + {0x00054031, 0x00000000}, | |
| 806 | + {0x00054032, 0x00008400}, | |
| 807 | + {0x00054033, 0x00003100}, | |
| 808 | + {0x00054034, 0x00006600}, | |
| 809 | + {0x00054035, 0x0000004d}, | |
| 810 | + {0x00054036, 0x0000004a}, | |
| 811 | + {0x00054037, 0x00001600}, | |
| 812 | + {0x00054038, 0x00008400}, | |
| 813 | + {0x00054039, 0x00003100}, | |
| 814 | + {0x0005403a, 0x00006600}, | |
| 815 | + {0x0005403b, 0x0000004d}, | |
| 816 | + {0x0005403c, 0x0000004a}, | |
| 817 | + {0x0005403d, 0x00002e00}, | |
| 818 | + {0x0005403e, 0x00000000}, | |
| 819 | + {0x0005403f, 0x00000000}, | |
| 820 | + {0x00054040, 0x00000000}, | |
| 821 | + {0x00054041, 0x00000000}, | |
| 822 | + {0x00054042, 0x00000000}, | |
| 823 | + {0x00054043, 0x00000000}, | |
| 824 | + {0x00054044, 0x00000000}, | |
| 825 | + {0x000d0000, 0x00000001}, | |
| 826 | +}; | |
| 827 | + | |
| 828 | + | |
| 829 | +/* P2 message block paremeter for training firmware */ | |
| 830 | +struct dram_cfg_param ddr_fsp2_cfg[] = { | |
| 831 | + {0x000d0000, 0x00000000}, | |
| 832 | + {0x00054000, 0x00000000}, | |
| 833 | + {0x00054001, 0x00000000}, | |
| 834 | + {0x00054002, 0x00000102}, | |
| 835 | + {0x00054003, 0x00000064}, | |
| 836 | + {0x00054004, 0x00000002}, | |
| 837 | + {0x00054005, 0x00000000}, | |
| 838 | + {0x00054006, 0x00000011}, | |
| 839 | + {0x00054007, 0x00000000}, | |
| 840 | + {0x00054008, 0x0000121f}, | |
| 841 | + {0x00054009, 0x000000c8}, | |
| 842 | + {0x0005400a, 0x00000000}, | |
| 843 | + {0x0005400b, 0x00000002}, | |
| 844 | + {0x0005400c, 0x00000000}, | |
| 845 | + {0x0005400d, 0x00000000}, | |
| 846 | + {0x0005400e, 0x00000000}, | |
| 847 | + {0x0005400f, 0x00000100}, | |
| 848 | + {0x00054010, 0x00000000}, | |
| 849 | + {0x00054011, 0x00000000}, | |
| 850 | + {0x00054012, 0x00000310}, | |
| 851 | + {0x00054013, 0x00000000}, | |
| 852 | + {0x00054014, 0x00000000}, | |
| 853 | + {0x00054015, 0x00000000}, | |
| 854 | + {0x00054016, 0x00000000}, | |
| 855 | + {0x00054017, 0x00000000}, | |
| 856 | + {0x00054018, 0x00000000}, | |
| 857 | + {0x00054019, 0x00000084}, | |
| 858 | + {0x0005401a, 0x00000031}, | |
| 859 | + {0x0005401b, 0x00004d66}, | |
| 860 | + {0x0005401c, 0x00004a00}, | |
| 861 | + {0x0005401d, 0x00000000}, | |
| 862 | + {0x0005401e, 0x00000016}, | |
| 863 | + {0x0005401f, 0x00000084}, | |
| 864 | + {0x00054020, 0x00000031}, | |
| 865 | + {0x00054021, 0x00004d66}, | |
| 866 | + {0x00054022, 0x00004a00}, | |
| 867 | + {0x00054023, 0x00000000}, | |
| 868 | + {0x00054024, 0x0000002e}, | |
| 869 | + {0x00054025, 0x00000000}, | |
| 870 | + {0x00054026, 0x00000000}, | |
| 871 | + {0x00054027, 0x00000000}, | |
| 872 | + {0x00054028, 0x00000000}, | |
| 873 | + {0x00054029, 0x00000000}, | |
| 874 | + {0x0005402a, 0x00000000}, | |
| 875 | + {0x0005402b, 0x00000000}, | |
| 876 | + {0x0005402c, 0x00000000}, | |
| 877 | + {0x0005402d, 0x00000000}, | |
| 878 | + {0x0005402e, 0x00000000}, | |
| 879 | + {0x0005402f, 0x00000000}, | |
| 880 | + {0x00054030, 0x00000000}, | |
| 881 | + {0x00054031, 0x00000000}, | |
| 882 | + {0x00054032, 0x00008400}, | |
| 883 | + {0x00054033, 0x00003100}, | |
| 884 | + {0x00054034, 0x00006600}, | |
| 885 | + {0x00054035, 0x0000004d}, | |
| 886 | + {0x00054036, 0x0000004a}, | |
| 887 | + {0x00054037, 0x00001600}, | |
| 888 | + {0x00054038, 0x00008400}, | |
| 889 | + {0x00054039, 0x00003100}, | |
| 890 | + {0x0005403a, 0x00006600}, | |
| 891 | + {0x0005403b, 0x0000004d}, | |
| 892 | + {0x0005403c, 0x0000004a}, | |
| 893 | + {0x0005403d, 0x00002e00}, | |
| 894 | + {0x0005403e, 0x00000000}, | |
| 895 | + {0x0005403f, 0x00000000}, | |
| 896 | + {0x00054040, 0x00000000}, | |
| 897 | + {0x00054041, 0x00000000}, | |
| 898 | + {0x00054042, 0x00000000}, | |
| 899 | + {0x00054043, 0x00000000}, | |
| 900 | + {0x00054044, 0x00000000}, | |
| 901 | + {0x000d0000, 0x00000001}, | |
| 902 | +}; | |
| 903 | + | |
| 904 | +/* P0 2D message block paremeter for training firmware */ | |
| 905 | +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | |
| 906 | + {0x000d0000, 0x00000000}, | |
| 907 | + {0x00054000, 0x00000000}, | |
| 908 | + {0x00054001, 0x00000000}, | |
| 909 | + {0x00054002, 0x00000000}, | |
| 910 | + {0x00054003, 0x00000c80}, | |
| 911 | + {0x00054004, 0x00000002}, | |
| 912 | + {0x00054005, 0x00000000}, | |
| 913 | + {0x00054006, 0x00000011}, | |
| 914 | + {0x00054007, 0x00000000}, | |
| 915 | + {0x00054008, 0x00000061}, | |
| 916 | + {0x00054009, 0x000000c8}, | |
| 917 | + {0x0005400a, 0x00000000}, | |
| 918 | + {0x0005400b, 0x00000002}, | |
| 919 | + {0x0005400c, 0x00000000}, | |
| 920 | + {0x0005400d, 0x00000000}, | |
| 921 | + {0x0005400e, 0x00000000}, | |
| 922 | + {0x0005400f, 0x00000100}, | |
| 923 | + {0x00054010, 0x00001f7f}, | |
| 924 | + {0x00054011, 0x00000000}, | |
| 925 | + {0x00054012, 0x00000310}, | |
| 926 | + {0x00054013, 0x00000000}, | |
| 927 | + {0x00054014, 0x00000000}, | |
| 928 | + {0x00054015, 0x00000000}, | |
| 929 | + {0x00054016, 0x00000000}, | |
| 930 | + {0x00054017, 0x00000000}, | |
| 931 | + {0x00054018, 0x00000000}, | |
| 932 | + {0x00054019, 0x00002dd4}, | |
| 933 | + {0x0005401a, 0x00000031}, | |
| 934 | + {0x0005401b, 0x00004d66}, | |
| 935 | + {0x0005401c, 0x00004a00}, | |
| 936 | + {0x0005401d, 0x00000000}, | |
| 937 | + {0x0005401e, 0x00000016}, | |
| 938 | + {0x0005401f, 0x00002dd4}, | |
| 939 | + {0x00054020, 0x00000031}, | |
| 940 | + {0x00054021, 0x00004d66}, | |
| 941 | + {0x00054022, 0x00004a00}, | |
| 942 | + {0x00054023, 0x00000000}, | |
| 943 | + {0x00054024, 0x0000002e}, | |
| 944 | + {0x00054025, 0x00000000}, | |
| 945 | + {0x00054026, 0x00000000}, | |
| 946 | + {0x00054027, 0x00000000}, | |
| 947 | + {0x00054028, 0x00000000}, | |
| 948 | + {0x00054029, 0x00000000}, | |
| 949 | + {0x0005402a, 0x00000000}, | |
| 950 | + {0x0005402b, 0x00000000}, | |
| 951 | + {0x0005402c, 0x00000000}, | |
| 952 | + {0x0005402d, 0x00000000}, | |
| 953 | + {0x0005402e, 0x00000000}, | |
| 954 | + {0x0005402f, 0x00000000}, | |
| 955 | + {0x00054030, 0x00000000}, | |
| 956 | + {0x00054031, 0x00000000}, | |
| 957 | + {0x00054032, 0x0000d400}, | |
| 958 | + {0x00054033, 0x0000312d}, | |
| 959 | + {0x00054034, 0x00006600}, | |
| 960 | + {0x00054035, 0x0000004d}, | |
| 961 | + {0x00054036, 0x0000004a}, | |
| 962 | + {0x00054037, 0x00001600}, | |
| 963 | + {0x00054038, 0x0000d400}, | |
| 964 | + {0x00054039, 0x0000312d}, | |
| 965 | + {0x0005403a, 0x00006600}, | |
| 966 | + {0x0005403b, 0x0000004d}, | |
| 967 | + {0x0005403c, 0x0000004a}, | |
| 968 | + {0x0005403d, 0x00002e00}, | |
| 969 | + {0x0005403e, 0x00000000}, | |
| 970 | + {0x0005403f, 0x00000000}, | |
| 971 | + {0x00054040, 0x00000000}, | |
| 972 | + {0x00054041, 0x00000000}, | |
| 973 | + {0x00054042, 0x00000000}, | |
| 974 | + {0x00054043, 0x00000000}, | |
| 975 | + {0x00054044, 0x00000000}, | |
| 976 | + {0x000d0000, 0x00000001}, | |
| 977 | +}; | |
| 978 | + | |
| 979 | +/* DRAM PHY init engine image */ | |
| 980 | +struct dram_cfg_param ddr_phy_pie[] = { | |
| 981 | + {0xd0000, 0x0}, | |
| 982 | + {0x90000, 0x10}, | |
| 983 | + {0x90001, 0x400}, | |
| 984 | + {0x90002, 0x10e}, | |
| 985 | + {0x90003, 0x0}, | |
| 986 | + {0x90004, 0x0}, | |
| 987 | + {0x90005, 0x8}, | |
| 988 | + {0x90029, 0xb}, | |
| 989 | + {0x9002a, 0x480}, | |
| 990 | + {0x9002b, 0x109}, | |
| 991 | + {0x9002c, 0x8}, | |
| 992 | + {0x9002d, 0x448}, | |
| 993 | + {0x9002e, 0x139}, | |
| 994 | + {0x9002f, 0x8}, | |
| 995 | + {0x90030, 0x478}, | |
| 996 | + {0x90031, 0x109}, | |
| 997 | + {0x90032, 0x0}, | |
| 998 | + {0x90033, 0xe8}, | |
| 999 | + {0x90034, 0x109}, | |
| 1000 | + {0x90035, 0x2}, | |
| 1001 | + {0x90036, 0x10}, | |
| 1002 | + {0x90037, 0x139}, | |
| 1003 | + {0x90038, 0xb}, | |
| 1004 | + {0x90039, 0x7c0}, | |
| 1005 | + {0x9003a, 0x139}, | |
| 1006 | + {0x9003b, 0x44}, | |
| 1007 | + {0x9003c, 0x633}, | |
| 1008 | + {0x9003d, 0x159}, | |
| 1009 | + {0x9003e, 0x14f}, | |
| 1010 | + {0x9003f, 0x630}, | |
| 1011 | + {0x90040, 0x159}, | |
| 1012 | + {0x90041, 0x47}, | |
| 1013 | + {0x90042, 0x633}, | |
| 1014 | + {0x90043, 0x149}, | |
| 1015 | + {0x90044, 0x4f}, | |
| 1016 | + {0x90045, 0x633}, | |
| 1017 | + {0x90046, 0x179}, | |
| 1018 | + {0x90047, 0x8}, | |
| 1019 | + {0x90048, 0xe0}, | |
| 1020 | + {0x90049, 0x109}, | |
| 1021 | + {0x9004a, 0x0}, | |
| 1022 | + {0x9004b, 0x7c8}, | |
| 1023 | + {0x9004c, 0x109}, | |
| 1024 | + {0x9004d, 0x0}, | |
| 1025 | + {0x9004e, 0x1}, | |
| 1026 | + {0x9004f, 0x8}, | |
| 1027 | + {0x90050, 0x0}, | |
| 1028 | + {0x90051, 0x45a}, | |
| 1029 | + {0x90052, 0x9}, | |
| 1030 | + {0x90053, 0x0}, | |
| 1031 | + {0x90054, 0x448}, | |
| 1032 | + {0x90055, 0x109}, | |
| 1033 | + {0x90056, 0x40}, | |
| 1034 | + {0x90057, 0x633}, | |
| 1035 | + {0x90058, 0x179}, | |
| 1036 | + {0x90059, 0x1}, | |
| 1037 | + {0x9005a, 0x618}, | |
| 1038 | + {0x9005b, 0x109}, | |
| 1039 | + {0x9005c, 0x40c0}, | |
| 1040 | + {0x9005d, 0x633}, | |
| 1041 | + {0x9005e, 0x149}, | |
| 1042 | + {0x9005f, 0x8}, | |
| 1043 | + {0x90060, 0x4}, | |
| 1044 | + {0x90061, 0x48}, | |
| 1045 | + {0x90062, 0x4040}, | |
| 1046 | + {0x90063, 0x633}, | |
| 1047 | + {0x90064, 0x149}, | |
| 1048 | + {0x90065, 0x0}, | |
| 1049 | + {0x90066, 0x4}, | |
| 1050 | + {0x90067, 0x48}, | |
| 1051 | + {0x90068, 0x40}, | |
| 1052 | + {0x90069, 0x633}, | |
| 1053 | + {0x9006a, 0x149}, | |
| 1054 | + {0x9006b, 0x10}, | |
| 1055 | + {0x9006c, 0x4}, | |
| 1056 | + {0x9006d, 0x18}, | |
| 1057 | + {0x9006e, 0x0}, | |
| 1058 | + {0x9006f, 0x4}, | |
| 1059 | + {0x90070, 0x78}, | |
| 1060 | + {0x90071, 0x549}, | |
| 1061 | + {0x90072, 0x633}, | |
| 1062 | + {0x90073, 0x159}, | |
| 1063 | + {0x90074, 0xd49}, | |
| 1064 | + {0x90075, 0x633}, | |
| 1065 | + {0x90076, 0x159}, | |
| 1066 | + {0x90077, 0x94a}, | |
| 1067 | + {0x90078, 0x633}, | |
| 1068 | + {0x90079, 0x159}, | |
| 1069 | + {0x9007a, 0x441}, | |
| 1070 | + {0x9007b, 0x633}, | |
| 1071 | + {0x9007c, 0x149}, | |
| 1072 | + {0x9007d, 0x42}, | |
| 1073 | + {0x9007e, 0x633}, | |
| 1074 | + {0x9007f, 0x149}, | |
| 1075 | + {0x90080, 0x1}, | |
| 1076 | + {0x90081, 0x633}, | |
| 1077 | + {0x90082, 0x149}, | |
| 1078 | + {0x90083, 0x0}, | |
| 1079 | + {0x90084, 0xe0}, | |
| 1080 | + {0x90085, 0x109}, | |
| 1081 | + {0x90086, 0xa}, | |
| 1082 | + {0x90087, 0x10}, | |
| 1083 | + {0x90088, 0x109}, | |
| 1084 | + {0x90089, 0x9}, | |
| 1085 | + {0x9008a, 0x3c0}, | |
| 1086 | + {0x9008b, 0x149}, | |
| 1087 | + {0x9008c, 0x9}, | |
| 1088 | + {0x9008d, 0x3c0}, | |
| 1089 | + {0x9008e, 0x159}, | |
| 1090 | + {0x9008f, 0x18}, | |
| 1091 | + {0x90090, 0x10}, | |
| 1092 | + {0x90091, 0x109}, | |
| 1093 | + {0x90092, 0x0}, | |
| 1094 | + {0x90093, 0x3c0}, | |
| 1095 | + {0x90094, 0x109}, | |
| 1096 | + {0x90095, 0x18}, | |
| 1097 | + {0x90096, 0x4}, | |
| 1098 | + {0x90097, 0x48}, | |
| 1099 | + {0x90098, 0x18}, | |
| 1100 | + {0x90099, 0x4}, | |
| 1101 | + {0x9009a, 0x58}, | |
| 1102 | + {0x9009b, 0xb}, | |
| 1103 | + {0x9009c, 0x10}, | |
| 1104 | + {0x9009d, 0x109}, | |
| 1105 | + {0x9009e, 0x1}, | |
| 1106 | + {0x9009f, 0x10}, | |
| 1107 | + {0x900a0, 0x109}, | |
| 1108 | + {0x900a1, 0x5}, | |
| 1109 | + {0x900a2, 0x7c0}, | |
| 1110 | + {0x900a3, 0x109}, | |
| 1111 | + {0x40000, 0x811}, | |
| 1112 | + {0x40020, 0x880}, | |
| 1113 | + {0x40040, 0x0}, | |
| 1114 | + {0x40060, 0x0}, | |
| 1115 | + {0x40001, 0x4008}, | |
| 1116 | + {0x40021, 0x83}, | |
| 1117 | + {0x40041, 0x4f}, | |
| 1118 | + {0x40061, 0x0}, | |
| 1119 | + {0x40002, 0x4040}, | |
| 1120 | + {0x40022, 0x83}, | |
| 1121 | + {0x40042, 0x51}, | |
| 1122 | + {0x40062, 0x0}, | |
| 1123 | + {0x40003, 0x811}, | |
| 1124 | + {0x40023, 0x880}, | |
| 1125 | + {0x40043, 0x0}, | |
| 1126 | + {0x40063, 0x0}, | |
| 1127 | + {0x40004, 0x720}, | |
| 1128 | + {0x40024, 0xf}, | |
| 1129 | + {0x40044, 0x1740}, | |
| 1130 | + {0x40064, 0x0}, | |
| 1131 | + {0x40005, 0x16}, | |
| 1132 | + {0x40025, 0x83}, | |
| 1133 | + {0x40045, 0x4b}, | |
| 1134 | + {0x40065, 0x0}, | |
| 1135 | + {0x40006, 0x716}, | |
| 1136 | + {0x40026, 0xf}, | |
| 1137 | + {0x40046, 0x2001}, | |
| 1138 | + {0x40066, 0x0}, | |
| 1139 | + {0x40007, 0x716}, | |
| 1140 | + {0x40027, 0xf}, | |
| 1141 | + {0x40047, 0x2800}, | |
| 1142 | + {0x40067, 0x0}, | |
| 1143 | + {0x40008, 0x716}, | |
| 1144 | + {0x40028, 0xf}, | |
| 1145 | + {0x40048, 0xf00}, | |
| 1146 | + {0x40068, 0x0}, | |
| 1147 | + {0x40009, 0x720}, | |
| 1148 | + {0x40029, 0xf}, | |
| 1149 | + {0x40049, 0x1400}, | |
| 1150 | + {0x40069, 0x0}, | |
| 1151 | + {0x4000a, 0xe08}, | |
| 1152 | + {0x4002a, 0xc15}, | |
| 1153 | + {0x4004a, 0x0}, | |
| 1154 | + {0x4006a, 0x0}, | |
| 1155 | + {0x4000b, 0x625}, | |
| 1156 | + {0x4002b, 0x15}, | |
| 1157 | + {0x4004b, 0x0}, | |
| 1158 | + {0x4006b, 0x0}, | |
| 1159 | + {0x4000c, 0x4028}, | |
| 1160 | + {0x4002c, 0x80}, | |
| 1161 | + {0x4004c, 0x0}, | |
| 1162 | + {0x4006c, 0x0}, | |
| 1163 | + {0x4000d, 0xe08}, | |
| 1164 | + {0x4002d, 0xc1a}, | |
| 1165 | + {0x4004d, 0x0}, | |
| 1166 | + {0x4006d, 0x0}, | |
| 1167 | + {0x4000e, 0x625}, | |
| 1168 | + {0x4002e, 0x1a}, | |
| 1169 | + {0x4004e, 0x0}, | |
| 1170 | + {0x4006e, 0x0}, | |
| 1171 | + {0x4000f, 0x4040}, | |
| 1172 | + {0x4002f, 0x80}, | |
| 1173 | + {0x4004f, 0x0}, | |
| 1174 | + {0x4006f, 0x0}, | |
| 1175 | + {0x40010, 0x2604}, | |
| 1176 | + {0x40030, 0x15}, | |
| 1177 | + {0x40050, 0x0}, | |
| 1178 | + {0x40070, 0x0}, | |
| 1179 | + {0x40011, 0x708}, | |
| 1180 | + {0x40031, 0x5}, | |
| 1181 | + {0x40051, 0x0}, | |
| 1182 | + {0x40071, 0x2002}, | |
| 1183 | + {0x40012, 0x8}, | |
| 1184 | + {0x40032, 0x80}, | |
| 1185 | + {0x40052, 0x0}, | |
| 1186 | + {0x40072, 0x0}, | |
| 1187 | + {0x40013, 0x2604}, | |
| 1188 | + {0x40033, 0x1a}, | |
| 1189 | + {0x40053, 0x0}, | |
| 1190 | + {0x40073, 0x0}, | |
| 1191 | + {0x40014, 0x708}, | |
| 1192 | + {0x40034, 0xa}, | |
| 1193 | + {0x40054, 0x0}, | |
| 1194 | + {0x40074, 0x2002}, | |
| 1195 | + {0x40015, 0x4040}, | |
| 1196 | + {0x40035, 0x80}, | |
| 1197 | + {0x40055, 0x0}, | |
| 1198 | + {0x40075, 0x0}, | |
| 1199 | + {0x40016, 0x60a}, | |
| 1200 | + {0x40036, 0x15}, | |
| 1201 | + {0x40056, 0x1200}, | |
| 1202 | + {0x40076, 0x0}, | |
| 1203 | + {0x40017, 0x61a}, | |
| 1204 | + {0x40037, 0x15}, | |
| 1205 | + {0x40057, 0x1300}, | |
| 1206 | + {0x40077, 0x0}, | |
| 1207 | + {0x40018, 0x60a}, | |
| 1208 | + {0x40038, 0x1a}, | |
| 1209 | + {0x40058, 0x1200}, | |
| 1210 | + {0x40078, 0x0}, | |
| 1211 | + {0x40019, 0x642}, | |
| 1212 | + {0x40039, 0x1a}, | |
| 1213 | + {0x40059, 0x1300}, | |
| 1214 | + {0x40079, 0x0}, | |
| 1215 | + {0x4001a, 0x4808}, | |
| 1216 | + {0x4003a, 0x880}, | |
| 1217 | + {0x4005a, 0x0}, | |
| 1218 | + {0x4007a, 0x0}, | |
| 1219 | + {0x900a4, 0x0}, | |
| 1220 | + {0x900a5, 0x790}, | |
| 1221 | + {0x900a6, 0x11a}, | |
| 1222 | + {0x900a7, 0x8}, | |
| 1223 | + {0x900a8, 0x7aa}, | |
| 1224 | + {0x900a9, 0x2a}, | |
| 1225 | + {0x900aa, 0x10}, | |
| 1226 | + {0x900ab, 0x7b2}, | |
| 1227 | + {0x900ac, 0x2a}, | |
| 1228 | + {0x900ad, 0x0}, | |
| 1229 | + {0x900ae, 0x7c8}, | |
| 1230 | + {0x900af, 0x109}, | |
| 1231 | + {0x900b0, 0x10}, | |
| 1232 | + {0x900b1, 0x10}, | |
| 1233 | + {0x900b2, 0x109}, | |
| 1234 | + {0x900b3, 0x10}, | |
| 1235 | + {0x900b4, 0x2a8}, | |
| 1236 | + {0x900b5, 0x129}, | |
| 1237 | + {0x900b6, 0x8}, | |
| 1238 | + {0x900b7, 0x370}, | |
| 1239 | + {0x900b8, 0x129}, | |
| 1240 | + {0x900b9, 0xa}, | |
| 1241 | + {0x900ba, 0x3c8}, | |
| 1242 | + {0x900bb, 0x1a9}, | |
| 1243 | + {0x900bc, 0xc}, | |
| 1244 | + {0x900bd, 0x408}, | |
| 1245 | + {0x900be, 0x199}, | |
| 1246 | + {0x900bf, 0x14}, | |
| 1247 | + {0x900c0, 0x790}, | |
| 1248 | + {0x900c1, 0x11a}, | |
| 1249 | + {0x900c2, 0x8}, | |
| 1250 | + {0x900c3, 0x4}, | |
| 1251 | + {0x900c4, 0x18}, | |
| 1252 | + {0x900c5, 0xe}, | |
| 1253 | + {0x900c6, 0x408}, | |
| 1254 | + {0x900c7, 0x199}, | |
| 1255 | + {0x900c8, 0x8}, | |
| 1256 | + {0x900c9, 0x8568}, | |
| 1257 | + {0x900ca, 0x108}, | |
| 1258 | + {0x900cb, 0x18}, | |
| 1259 | + {0x900cc, 0x790}, | |
| 1260 | + {0x900cd, 0x16a}, | |
| 1261 | + {0x900ce, 0x8}, | |
| 1262 | + {0x900cf, 0x1d8}, | |
| 1263 | + {0x900d0, 0x169}, | |
| 1264 | + {0x900d1, 0x10}, | |
| 1265 | + {0x900d2, 0x8558}, | |
| 1266 | + {0x900d3, 0x168}, | |
| 1267 | + {0x900d4, 0x70}, | |
| 1268 | + {0x900d5, 0x788}, | |
| 1269 | + {0x900d6, 0x16a}, | |
| 1270 | + {0x900d7, 0x1ff8}, | |
| 1271 | + {0x900d8, 0x85a8}, | |
| 1272 | + {0x900d9, 0x1e8}, | |
| 1273 | + {0x900da, 0x50}, | |
| 1274 | + {0x900db, 0x798}, | |
| 1275 | + {0x900dc, 0x16a}, | |
| 1276 | + {0x900dd, 0x60}, | |
| 1277 | + {0x900de, 0x7a0}, | |
| 1278 | + {0x900df, 0x16a}, | |
| 1279 | + {0x900e0, 0x8}, | |
| 1280 | + {0x900e1, 0x8310}, | |
| 1281 | + {0x900e2, 0x168}, | |
| 1282 | + {0x900e3, 0x8}, | |
| 1283 | + {0x900e4, 0xa310}, | |
| 1284 | + {0x900e5, 0x168}, | |
| 1285 | + {0x900e6, 0xa}, | |
| 1286 | + {0x900e7, 0x408}, | |
| 1287 | + {0x900e8, 0x169}, | |
| 1288 | + {0x900e9, 0x6e}, | |
| 1289 | + {0x900ea, 0x0}, | |
| 1290 | + {0x900eb, 0x68}, | |
| 1291 | + {0x900ec, 0x0}, | |
| 1292 | + {0x900ed, 0x408}, | |
| 1293 | + {0x900ee, 0x169}, | |
| 1294 | + {0x900ef, 0x0}, | |
| 1295 | + {0x900f0, 0x8310}, | |
| 1296 | + {0x900f1, 0x168}, | |
| 1297 | + {0x900f2, 0x0}, | |
| 1298 | + {0x900f3, 0xa310}, | |
| 1299 | + {0x900f4, 0x168}, | |
| 1300 | + {0x900f5, 0x1ff8}, | |
| 1301 | + {0x900f6, 0x85a8}, | |
| 1302 | + {0x900f7, 0x1e8}, | |
| 1303 | + {0x900f8, 0x68}, | |
| 1304 | + {0x900f9, 0x798}, | |
| 1305 | + {0x900fa, 0x16a}, | |
| 1306 | + {0x900fb, 0x78}, | |
| 1307 | + {0x900fc, 0x7a0}, | |
| 1308 | + {0x900fd, 0x16a}, | |
| 1309 | + {0x900fe, 0x68}, | |
| 1310 | + {0x900ff, 0x790}, | |
| 1311 | + {0x90100, 0x16a}, | |
| 1312 | + {0x90101, 0x8}, | |
| 1313 | + {0x90102, 0x8b10}, | |
| 1314 | + {0x90103, 0x168}, | |
| 1315 | + {0x90104, 0x8}, | |
| 1316 | + {0x90105, 0xab10}, | |
| 1317 | + {0x90106, 0x168}, | |
| 1318 | + {0x90107, 0xa}, | |
| 1319 | + {0x90108, 0x408}, | |
| 1320 | + {0x90109, 0x169}, | |
| 1321 | + {0x9010a, 0x58}, | |
| 1322 | + {0x9010b, 0x0}, | |
| 1323 | + {0x9010c, 0x68}, | |
| 1324 | + {0x9010d, 0x0}, | |
| 1325 | + {0x9010e, 0x408}, | |
| 1326 | + {0x9010f, 0x169}, | |
| 1327 | + {0x90110, 0x0}, | |
| 1328 | + {0x90111, 0x8b10}, | |
| 1329 | + {0x90112, 0x168}, | |
| 1330 | + {0x90113, 0x1}, | |
| 1331 | + {0x90114, 0xab10}, | |
| 1332 | + {0x90115, 0x168}, | |
| 1333 | + {0x90116, 0x0}, | |
| 1334 | + {0x90117, 0x1d8}, | |
| 1335 | + {0x90118, 0x169}, | |
| 1336 | + {0x90119, 0x80}, | |
| 1337 | + {0x9011a, 0x790}, | |
| 1338 | + {0x9011b, 0x16a}, | |
| 1339 | + {0x9011c, 0x18}, | |
| 1340 | + {0x9011d, 0x7aa}, | |
| 1341 | + {0x9011e, 0x6a}, | |
| 1342 | + {0x9011f, 0xa}, | |
| 1343 | + {0x90120, 0x0}, | |
| 1344 | + {0x90121, 0x1e9}, | |
| 1345 | + {0x90122, 0x8}, | |
| 1346 | + {0x90123, 0x8080}, | |
| 1347 | + {0x90124, 0x108}, | |
| 1348 | + {0x90125, 0xf}, | |
| 1349 | + {0x90126, 0x408}, | |
| 1350 | + {0x90127, 0x169}, | |
| 1351 | + {0x90128, 0xc}, | |
| 1352 | + {0x90129, 0x0}, | |
| 1353 | + {0x9012a, 0x68}, | |
| 1354 | + {0x9012b, 0x9}, | |
| 1355 | + {0x9012c, 0x0}, | |
| 1356 | + {0x9012d, 0x1a9}, | |
| 1357 | + {0x9012e, 0x0}, | |
| 1358 | + {0x9012f, 0x408}, | |
| 1359 | + {0x90130, 0x169}, | |
| 1360 | + {0x90131, 0x0}, | |
| 1361 | + {0x90132, 0x8080}, | |
| 1362 | + {0x90133, 0x108}, | |
| 1363 | + {0x90134, 0x8}, | |
| 1364 | + {0x90135, 0x7aa}, | |
| 1365 | + {0x90136, 0x6a}, | |
| 1366 | + {0x90137, 0x0}, | |
| 1367 | + {0x90138, 0x8568}, | |
| 1368 | + {0x90139, 0x108}, | |
| 1369 | + {0x9013a, 0xb7}, | |
| 1370 | + {0x9013b, 0x790}, | |
| 1371 | + {0x9013c, 0x16a}, | |
| 1372 | + {0x9013d, 0x1f}, | |
| 1373 | + {0x9013e, 0x0}, | |
| 1374 | + {0x9013f, 0x68}, | |
| 1375 | + {0x90140, 0x8}, | |
| 1376 | + {0x90141, 0x8558}, | |
| 1377 | + {0x90142, 0x168}, | |
| 1378 | + {0x90143, 0xf}, | |
| 1379 | + {0x90144, 0x408}, | |
| 1380 | + {0x90145, 0x169}, | |
| 1381 | + {0x90146, 0xd}, | |
| 1382 | + {0x90147, 0x0}, | |
| 1383 | + {0x90148, 0x68}, | |
| 1384 | + {0x90149, 0x0}, | |
| 1385 | + {0x9014a, 0x408}, | |
| 1386 | + {0x9014b, 0x169}, | |
| 1387 | + {0x9014c, 0x0}, | |
| 1388 | + {0x9014d, 0x8558}, | |
| 1389 | + {0x9014e, 0x168}, | |
| 1390 | + {0x9014f, 0x8}, | |
| 1391 | + {0x90150, 0x3c8}, | |
| 1392 | + {0x90151, 0x1a9}, | |
| 1393 | + {0x90152, 0x3}, | |
| 1394 | + {0x90153, 0x370}, | |
| 1395 | + {0x90154, 0x129}, | |
| 1396 | + {0x90155, 0x20}, | |
| 1397 | + {0x90156, 0x2aa}, | |
| 1398 | + {0x90157, 0x9}, | |
| 1399 | + {0x90158, 0x0}, | |
| 1400 | + {0x90159, 0x400}, | |
| 1401 | + {0x9015a, 0x10e}, | |
| 1402 | + {0x9015b, 0x8}, | |
| 1403 | + {0x9015c, 0xe8}, | |
| 1404 | + {0x9015d, 0x109}, | |
| 1405 | + {0x9015e, 0x0}, | |
| 1406 | + {0x9015f, 0x8140}, | |
| 1407 | + {0x90160, 0x10c}, | |
| 1408 | + {0x90161, 0x10}, | |
| 1409 | + {0x90162, 0x8138}, | |
| 1410 | + {0x90163, 0x10c}, | |
| 1411 | + {0x90164, 0x8}, | |
| 1412 | + {0x90165, 0x7c8}, | |
| 1413 | + {0x90166, 0x101}, | |
| 1414 | + {0x90167, 0x8}, | |
| 1415 | + {0x90168, 0x448}, | |
| 1416 | + {0x90169, 0x109}, | |
| 1417 | + {0x9016a, 0xf}, | |
| 1418 | + {0x9016b, 0x7c0}, | |
| 1419 | + {0x9016c, 0x109}, | |
| 1420 | + {0x9016d, 0x0}, | |
| 1421 | + {0x9016e, 0xe8}, | |
| 1422 | + {0x9016f, 0x109}, | |
| 1423 | + {0x90170, 0x47}, | |
| 1424 | + {0x90171, 0x630}, | |
| 1425 | + {0x90172, 0x109}, | |
| 1426 | + {0x90173, 0x8}, | |
| 1427 | + {0x90174, 0x618}, | |
| 1428 | + {0x90175, 0x109}, | |
| 1429 | + {0x90176, 0x8}, | |
| 1430 | + {0x90177, 0xe0}, | |
| 1431 | + {0x90178, 0x109}, | |
| 1432 | + {0x90179, 0x0}, | |
| 1433 | + {0x9017a, 0x7c8}, | |
| 1434 | + {0x9017b, 0x109}, | |
| 1435 | + {0x9017c, 0x8}, | |
| 1436 | + {0x9017d, 0x8140}, | |
| 1437 | + {0x9017e, 0x10c}, | |
| 1438 | + {0x9017f, 0x0}, | |
| 1439 | + {0x90180, 0x1}, | |
| 1440 | + {0x90181, 0x8}, | |
| 1441 | + {0x90182, 0x8}, | |
| 1442 | + {0x90183, 0x4}, | |
| 1443 | + {0x90184, 0x8}, | |
| 1444 | + {0x90185, 0x8}, | |
| 1445 | + {0x90186, 0x7c8}, | |
| 1446 | + {0x90187, 0x101}, | |
| 1447 | + {0x90006, 0x0}, | |
| 1448 | + {0x90007, 0x0}, | |
| 1449 | + {0x90008, 0x8}, | |
| 1450 | + {0x90009, 0x0}, | |
| 1451 | + {0x9000a, 0x0}, | |
| 1452 | + {0x9000b, 0x0}, | |
| 1453 | + {0xd00e7, 0x400}, | |
| 1454 | + {0x90017, 0x0}, | |
| 1455 | + {0x9001f, 0x29}, | |
| 1456 | + {0x90026, 0x6a}, | |
| 1457 | + {0x400d0, 0x0}, | |
| 1458 | + {0x400d1, 0x101}, | |
| 1459 | + {0x400d2, 0x105}, | |
| 1460 | + {0x400d3, 0x107}, | |
| 1461 | + {0x400d4, 0x10f}, | |
| 1462 | + {0x400d5, 0x202}, | |
| 1463 | + {0x400d6, 0x20a}, | |
| 1464 | + {0x400d7, 0x20b}, | |
| 1465 | + {0x2003a, 0x2}, | |
| 1466 | + {0x2000b, 0x64}, | |
| 1467 | + {0x2000c, 0xc8}, | |
| 1468 | + {0x2000d, 0x7d0}, | |
| 1469 | + {0x2000e, 0x2c}, | |
| 1470 | + {0x12000b, 0xc}, | |
| 1471 | + {0x12000c, 0x19}, | |
| 1472 | + {0x12000d, 0xfa}, | |
| 1473 | + {0x12000e, 0x10}, | |
| 1474 | + {0x22000b, 0x3}, | |
| 1475 | + {0x22000c, 0x6}, | |
| 1476 | + {0x22000d, 0x3e}, | |
| 1477 | + {0x22000e, 0x10}, | |
| 1478 | + {0x9000c, 0x0}, | |
| 1479 | + {0x9000d, 0x173}, | |
| 1480 | + {0x9000e, 0x60}, | |
| 1481 | + {0x9000f, 0x6110}, | |
| 1482 | + {0x90010, 0x2152}, | |
| 1483 | + {0x90011, 0xdfbd}, | |
| 1484 | + {0x90012, 0x2060}, | |
| 1485 | + {0x90013, 0x6152}, | |
| 1486 | + {0x20010, 0x5a}, | |
| 1487 | + {0x20011, 0x3}, | |
| 1488 | + {0x40080, 0xe0}, | |
| 1489 | + {0x40081, 0x12}, | |
| 1490 | + {0x40082, 0xe0}, | |
| 1491 | + {0x40083, 0x12}, | |
| 1492 | + {0x40084, 0xe0}, | |
| 1493 | + {0x40085, 0x12}, | |
| 1494 | + {0x140080, 0xe0}, | |
| 1495 | + {0x140081, 0x12}, | |
| 1496 | + {0x140082, 0xe0}, | |
| 1497 | + {0x140083, 0x12}, | |
| 1498 | + {0x140084, 0xe0}, | |
| 1499 | + {0x140085, 0x12}, | |
| 1500 | + {0x240080, 0xe0}, | |
| 1501 | + {0x240081, 0x12}, | |
| 1502 | + {0x240082, 0xe0}, | |
| 1503 | + {0x240083, 0x12}, | |
| 1504 | + {0x240084, 0xe0}, | |
| 1505 | + {0x240085, 0x12}, | |
| 1506 | + {0x400fd, 0xf}, | |
| 1507 | + {0x10011, 0x1}, | |
| 1508 | + {0x10012, 0x1}, | |
| 1509 | + {0x10013, 0x180}, | |
| 1510 | + {0x10018, 0x1}, | |
| 1511 | + {0x10002, 0x6209}, | |
| 1512 | + {0x100b2, 0x1}, | |
| 1513 | + {0x101b4, 0x1}, | |
| 1514 | + {0x102b4, 0x1}, | |
| 1515 | + {0x103b4, 0x1}, | |
| 1516 | + {0x104b4, 0x1}, | |
| 1517 | + {0x105b4, 0x1}, | |
| 1518 | + {0x106b4, 0x1}, | |
| 1519 | + {0x107b4, 0x1}, | |
| 1520 | + {0x108b4, 0x1}, | |
| 1521 | + {0x11011, 0x1}, | |
| 1522 | + {0x11012, 0x1}, | |
| 1523 | + {0x11013, 0x180}, | |
| 1524 | + {0x11018, 0x1}, | |
| 1525 | + {0x11002, 0x6209}, | |
| 1526 | + {0x110b2, 0x1}, | |
| 1527 | + {0x111b4, 0x1}, | |
| 1528 | + {0x112b4, 0x1}, | |
| 1529 | + {0x113b4, 0x1}, | |
| 1530 | + {0x114b4, 0x1}, | |
| 1531 | + {0x115b4, 0x1}, | |
| 1532 | + {0x116b4, 0x1}, | |
| 1533 | + {0x117b4, 0x1}, | |
| 1534 | + {0x118b4, 0x1}, | |
| 1535 | + {0x20089, 0x1}, | |
| 1536 | + {0x20088, 0x19}, | |
| 1537 | + {0xc0080, 0x2}, | |
| 1538 | + {0xd0000, 0x1}, | |
| 1539 | +}; | |
| 1540 | + | |
| 1541 | +struct dram_fsp_msg ddr_dram_fsp_msg[] = { | |
| 1542 | + { | |
| 1543 | + /* P0 3200mts 1D */ | |
| 1544 | + .drate = 3200, | |
| 1545 | + .fw_type = FW_1D_IMAGE, | |
| 1546 | + .fsp_cfg = ddr_fsp0_cfg, | |
| 1547 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | |
| 1548 | + }, | |
| 1549 | + { | |
| 1550 | + /* P1 400mts 1D */ | |
| 1551 | + .drate = 400, | |
| 1552 | + .fw_type = FW_1D_IMAGE, | |
| 1553 | + .fsp_cfg = ddr_fsp1_cfg, | |
| 1554 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | |
| 1555 | + }, | |
| 1556 | + { | |
| 1557 | + /* P2 100mts 1D */ | |
| 1558 | + .drate = 100, | |
| 1559 | + .fw_type = FW_1D_IMAGE, | |
| 1560 | + .fsp_cfg = ddr_fsp2_cfg, | |
| 1561 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), | |
| 1562 | + }, | |
| 1563 | + { | |
| 1564 | + /* P0 3200mts 2D */ | |
| 1565 | + .drate = 3200, | |
| 1566 | + .fw_type = FW_2D_IMAGE, | |
| 1567 | + .fsp_cfg = ddr_fsp0_2d_cfg, | |
| 1568 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | |
| 1569 | + }, | |
| 1570 | +}; | |
| 1571 | + | |
| 1572 | +/* ddr timing config params */ | |
| 1573 | +struct dram_timing_info dram_timing = { | |
| 1574 | + .ddrc_cfg = ddr_ddrc_cfg, | |
| 1575 | + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | |
| 1576 | + .ddrphy_cfg = ddr_ddrphy_cfg, | |
| 1577 | + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | |
| 1578 | + .fsp_msg = ddr_dram_fsp_msg, | |
| 1579 | + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | |
| 1580 | + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | |
| 1581 | + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | |
| 1582 | + .ddrphy_pie = ddr_phy_pie, | |
| 1583 | + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | |
| 1584 | + .fsp_table = { 3200, 400, 100, }, | |
| 1585 | +}; |
board/freescale/imx8mm_ab2/spl.c
| ... | ... | @@ -24,6 +24,8 @@ |
| 24 | 24 | |
| 25 | 25 | #ifdef CONFIG_TARGET_IMX8MM_AB2 |
| 26 | 26 | #include <asm/arch/imx8mm_pins.h> |
| 27 | +#else | |
| 28 | +#include <asm/arch/imx8mn_pins.h> | |
| 27 | 29 | #endif |
| 28 | 30 | |
| 29 | 31 | #ifdef CONFIG_POWER_PCA9450 |
| ... | ... | @@ -36,6 +38,7 @@ |
| 36 | 38 | |
| 37 | 39 | int spl_board_boot_device(enum boot_device boot_dev_spl) |
| 38 | 40 | { |
| 41 | +#ifdef CONFIG_TARGET_IMX8MM_AB2 | |
| 39 | 42 | switch (boot_dev_spl) { |
| 40 | 43 | case SD2_BOOT: |
| 41 | 44 | case MMC2_BOOT: |
| ... | ... | @@ -52,6 +55,9 @@ |
| 52 | 55 | default: |
| 53 | 56 | return BOOT_DEVICE_NONE; |
| 54 | 57 | } |
| 58 | +#else | |
| 59 | + return BOOT_DEVICE_BOOTROM; | |
| 60 | +#endif | |
| 55 | 61 | } |
| 56 | 62 | |
| 57 | 63 | void spl_dram_init(void) |
| ... | ... | @@ -81,6 +87,21 @@ |
| 81 | 87 | }; |
| 82 | 88 | #endif |
| 83 | 89 | |
| 90 | +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) | |
| 91 | +struct i2c_pads_info i2c_pad_info1 = { | |
| 92 | + .scl = { | |
| 93 | + .i2c_mode = IMX8MN_PAD_I2C1_SCL__I2C1_SCL | PC, | |
| 94 | + .gpio_mode = IMX8MN_PAD_I2C1_SCL__GPIO5_IO14 | PC, | |
| 95 | + .gp = IMX_GPIO_NR(5, 14), | |
| 96 | + }, | |
| 97 | + .sda = { | |
| 98 | + .i2c_mode = IMX8MN_PAD_I2C1_SDA__I2C1_SDA | PC, | |
| 99 | + .gpio_mode = IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 | PC, | |
| 100 | + .gp = IMX_GPIO_NR(5, 15), | |
| 101 | + }, | |
| 102 | +}; | |
| 103 | +#endif | |
| 104 | + | |
| 84 | 105 | #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) |
| 85 | 106 | #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) |
| 86 | 107 | |
| ... | ... | @@ -110,6 +131,32 @@ |
| 110 | 131 | }; |
| 111 | 132 | #endif |
| 112 | 133 | |
| 134 | +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) | |
| 135 | +static iomux_v3_cfg_t const usdhc3_pads[] = { | |
| 136 | + IMX8MN_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 137 | + IMX8MN_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 138 | + IMX8MN_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 139 | + IMX8MN_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 140 | + IMX8MN_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 141 | + IMX8MN_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 142 | + IMX8MN_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 143 | + IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 144 | + IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 145 | + IMX8MN_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 146 | +}; | |
| 147 | + | |
| 148 | +static iomux_v3_cfg_t const usdhc2_pads[] = { | |
| 149 | + IMX8MN_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 150 | + IMX8MN_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 151 | + IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 152 | + IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 153 | + IMX8MN_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 154 | + IMX8MN_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
| 155 | + IMX8MN_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), | |
| 156 | + IMX8MN_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), | |
| 157 | +}; | |
| 158 | +#endif | |
| 159 | + | |
| 113 | 160 | static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| 114 | 161 | {USDHC2_BASE_ADDR, 0, 4}, |
| 115 | 162 | {USDHC3_BASE_ADDR, 0, 8}, |
| 116 | 163 | |
| ... | ... | @@ -177,12 +224,13 @@ |
| 177 | 224 | |
| 178 | 225 | #ifdef CONFIG_POWER |
| 179 | 226 | #define I2C_PMIC 0 |
| 227 | + | |
| 228 | +#ifdef CONFIG_POWER_PCA9450 | |
| 180 | 229 | int power_init_board(void) |
| 181 | 230 | { |
| 182 | 231 | struct pmic *p; |
| 183 | 232 | int ret; |
| 184 | 233 | |
| 185 | -#ifdef CONFIG_POWER_PCA9450 | |
| 186 | 234 | ret = power_pca9450b_init(I2C_PMIC); |
| 187 | 235 | if (ret) |
| 188 | 236 | printf("power init failed"); |
| 189 | 237 | |
| ... | ... | @@ -202,14 +250,25 @@ |
| 202 | 250 | pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); |
| 203 | 251 | pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); |
| 204 | 252 | |
| 205 | - /* Kernel uses OD/OD freq for SOC */ | |
| 206 | - /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ | |
| 207 | - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); | |
| 208 | - | |
| 253 | +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) | |
| 254 | + /* set VDD_SNVS_0V8 from default 0.85V */ | |
| 255 | + pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0); | |
| 256 | + /* enable LDO4 to 1.2v */ | |
| 257 | + pmic_reg_write(p, PCA9450_LDO4CTRL, 0x44); | |
| 258 | +#endif | |
| 209 | 259 | /* set WDOG_B_CFG to cold reset */ |
| 210 | 260 | pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); |
| 211 | 261 | |
| 212 | -#else | |
| 262 | + return 0; | |
| 263 | +} | |
| 264 | +#endif /* CONFIG_POWER_PCA9450 */ | |
| 265 | + | |
| 266 | +#ifdef CONFIG_POWER_BD71837 | |
| 267 | +int power_init_board(void) | |
| 268 | +{ | |
| 269 | + struct pmic *p; | |
| 270 | + int ret; | |
| 271 | + | |
| 213 | 272 | ret = power_bd71837_init(I2C_PMIC); |
| 214 | 273 | if (ret) |
| 215 | 274 | printf("power init failed"); |
| 216 | 275 | |
| 217 | 276 | |
| 218 | 277 | |
| 219 | 278 | |
| ... | ... | @@ -220,21 +279,39 @@ |
| 220 | 279 | pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); |
| 221 | 280 | /* unlock the PMIC regs */ |
| 222 | 281 | pmic_reg_write(p, BD71837_REGLOCK, 0x1); |
| 282 | +#ifdef CONFIG_TARGET_IMX8MM_AB2 | |
| 223 | 283 | /* increase VDD_SOC to typical value 0.85v before first DRAM access */ |
| 224 | 284 | pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); |
| 225 | 285 | /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ |
| 226 | 286 | pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); |
| 227 | -#ifndef CONFIG_IMX8M_LPDDR4 | |
| 287 | +#ifdef CONFIG_IMX8M_DDR4 | |
| 228 | 288 | /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ |
| 229 | 289 | pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); |
| 230 | 290 | #endif |
| 291 | +#endif /* CONFIG_TARGET_IMX8MM_AB2 */ | |
| 292 | + | |
| 293 | +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) | |
| 294 | + /* Set VDD_ARM to typical value 0.85v for 1.2Ghz */ | |
| 295 | + pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0xf); | |
| 296 | +#ifdef CONFIG_IMX8M_DDR4 | |
| 297 | + /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */ | |
| 298 | + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0xf); | |
| 299 | +#endif | |
| 300 | + /* Set VDD_SOC 0.85v for suspend */ | |
| 301 | + pmic_reg_write(p, BD71837_BUCK1_VOLT_SUSP, 0xf); | |
| 302 | +#ifdef CONFIG_IMX8M_DDR4 | |
| 303 | + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ | |
| 304 | + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); | |
| 305 | +#endif | |
| 306 | +#endif /* CONFIG_TARGET_IMX8MN_AB2 */ | |
| 307 | + | |
| 231 | 308 | /* lock the PMIC regs */ |
| 232 | 309 | pmic_reg_write(p, BD71837_REGLOCK, 0x11); |
| 233 | -#endif | |
| 234 | 310 | |
| 235 | 311 | return 0; |
| 236 | 312 | } |
| 237 | -#endif | |
| 313 | +#endif /* CONFIG_POWER_BD71837 */ | |
| 314 | +#endif /* CONFIG_POWER */ | |
| 238 | 315 | |
| 239 | 316 | void spl_board_init(void) |
| 240 | 317 | { |
configs/imx8mn_ab2_defconfig
| 1 | +CONFIG_ARM=y | |
| 2 | +CONFIG_SPL_SYS_ICACHE_OFF=y | |
| 3 | +CONFIG_SPL_SYS_DCACHE_OFF=y | |
| 4 | +CONFIG_ARCH_IMX8M=y | |
| 5 | +CONFIG_SYS_TEXT_BASE=0x40200000 | |
| 6 | +CONFIG_SPL_GPIO_SUPPORT=y | |
| 7 | +CONFIG_SPL_LIBCOMMON_SUPPORT=y | |
| 8 | +CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
| 9 | +CONFIG_SYS_MALLOC_F_LEN=0x2000 | |
| 10 | +CONFIG_SYS_I2C_MXC_I2C1=y | |
| 11 | +CONFIG_SYS_I2C_MXC_I2C2=y | |
| 12 | +CONFIG_SYS_I2C_MXC_I2C3=y | |
| 13 | +CONFIG_ENV_SIZE=0x1000 | |
| 14 | +CONFIG_ENV_OFFSET=0x400000 | |
| 15 | +CONFIG_ENV_SECT_SIZE=0x10000 | |
| 16 | +CONFIG_DM_GPIO=y | |
| 17 | +CONFIG_TARGET_IMX8MN_AB2=y | |
| 18 | +CONFIG_ARCH_MISC_INIT=y | |
| 19 | +CONFIG_SPL_SERIAL_SUPPORT=y | |
| 20 | +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | |
| 21 | +CONFIG_SPL=y | |
| 22 | +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | |
| 23 | +CONFIG_CSF_SIZE=0x2000 | |
| 24 | +CONFIG_SPL_TEXT_BASE=0x912000 | |
| 25 | +CONFIG_FIT=y | |
| 26 | +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | |
| 27 | +CONFIG_SPL_LOAD_FIT=y | |
| 28 | +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | |
| 29 | +CONFIG_OF_SYSTEM_SETUP=y | |
| 30 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" | |
| 31 | +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ab2" | |
| 32 | +CONFIG_DEFAULT_FDT_FILE="imx8mn-ab2.dtb" | |
| 33 | +CONFIG_BOARD_LATE_INIT=y | |
| 34 | +CONFIG_BOARD_EARLY_INIT_F=y | |
| 35 | +CONFIG_SPL_BOARD_INIT=y | |
| 36 | +CONFIG_SPL_BOOTROM_SUPPORT=y | |
| 37 | +CONFIG_SPL_SEPARATE_BSS=y | |
| 38 | +CONFIG_SPL_I2C_SUPPORT=y | |
| 39 | +CONFIG_SPL_POWER_SUPPORT=y | |
| 40 | +CONFIG_NR_DRAM_BANKS=2 | |
| 41 | +CONFIG_HUSH_PARSER=y | |
| 42 | +CONFIG_SYS_PROMPT="u-boot=> " | |
| 43 | +# CONFIG_CMD_EXPORTENV is not set | |
| 44 | +# CONFIG_CMD_IMPORTENV is not set | |
| 45 | +CONFIG_CMD_ERASEENV=y | |
| 46 | +# CONFIG_CMD_CRC32 is not set | |
| 47 | +# CONFIG_BOOTM_NETBSD is not set | |
| 48 | +CONFIG_CMD_CLK=y | |
| 49 | +CONFIG_CMD_FUSE=y | |
| 50 | +CONFIG_CMD_GPIO=y | |
| 51 | +CONFIG_CMD_I2C=y | |
| 52 | +CONFIG_CMD_MMC=y | |
| 53 | +CONFIG_CMD_DHCP=y | |
| 54 | +CONFIG_CMD_MII=y | |
| 55 | +CONFIG_CMD_PING=y | |
| 56 | +CONFIG_CMD_CACHE=y | |
| 57 | +CONFIG_CMD_REGULATOR=y | |
| 58 | +CONFIG_CMD_MEMTEST=y | |
| 59 | +CONFIG_CMD_EXT2=y | |
| 60 | +CONFIG_CMD_EXT4=y | |
| 61 | +CONFIG_CMD_EXT4_WRITE=y | |
| 62 | +CONFIG_CMD_FAT=y | |
| 63 | +CONFIG_CMD_SF=y | |
| 64 | +CONFIG_OF_CONTROL=y | |
| 65 | +CONFIG_ENV_IS_IN_MMC=y | |
| 66 | +CONFIG_ENV_IS_IN_SPI_FLASH=y | |
| 67 | +CONFIG_ENV_IS_NOWHERE=y | |
| 68 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| 69 | +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | |
| 70 | +CONFIG_CLK_COMPOSITE_CCF=y | |
| 71 | +CONFIG_CLK_IMX8MN=y | |
| 72 | +CONFIG_MXC_GPIO=y | |
| 73 | + | |
| 74 | +CONFIG_DM_I2C=y | |
| 75 | +CONFIG_SYS_I2C_MXC=y | |
| 76 | +CONFIG_DM_MMC=y | |
| 77 | +CONFIG_MMC_IO_VOLTAGE=y | |
| 78 | +CONFIG_MMC_UHS_SUPPORT=y | |
| 79 | +CONFIG_MMC_HS400_SUPPORT=y | |
| 80 | +CONFIG_MMC_HS400_ES_SUPPORT=y | |
| 81 | +CONFIG_EFI_PARTITION=y | |
| 82 | +CONFIG_SUPPORT_EMMC_BOOT=y | |
| 83 | +CONFIG_FSL_ESDHC_IMX=y | |
| 84 | +CONFIG_DM_SPI_FLASH=y | |
| 85 | +CONFIG_DM_SPI=y | |
| 86 | +CONFIG_FSL_FSPI=y | |
| 87 | +CONFIG_SPI=y | |
| 88 | +CONFIG_SPI_FLASH=y | |
| 89 | +CONFIG_SPI_FLASH_BAR=y | |
| 90 | +CONFIG_SPI_FLASH_STMICRO=y | |
| 91 | +CONFIG_SF_DEFAULT_BUS=0 | |
| 92 | +CONFIG_SF_DEFAULT_CS=0 | |
| 93 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
| 94 | +CONFIG_SF_DEFAULT_MODE=0 | |
| 95 | + | |
| 96 | +CONFIG_PHYLIB=y | |
| 97 | +CONFIG_PHY_REALTEK=y | |
| 98 | +CONFIG_DM_ETH=y | |
| 99 | +CONFIG_PHY_GIGE=y | |
| 100 | +CONFIG_FEC_MXC=y | |
| 101 | +CONFIG_MII=y | |
| 102 | +CONFIG_PINCTRL=y | |
| 103 | +CONFIG_PINCTRL_IMX8M=y | |
| 104 | +CONFIG_DM_REGULATOR=y | |
| 105 | +CONFIG_DM_REGULATOR_FIXED=y | |
| 106 | +CONFIG_DM_REGULATOR_GPIO=y | |
| 107 | +CONFIG_MXC_UART=y | |
| 108 | +CONFIG_SYSRESET=y | |
| 109 | +CONFIG_SYSRESET_PSCI=y | |
| 110 | +CONFIG_DM_THERMAL=y | |
| 111 | +CONFIG_NXP_TMU=y | |
| 112 | + | |
| 113 | +CONFIG_OF_LIBFDT_OVERLAY=y |
configs/imx8mn_ddr4_ab2_defconfig
| 1 | +CONFIG_ARM=y | |
| 2 | +CONFIG_SPL_SYS_ICACHE_OFF=y | |
| 3 | +CONFIG_SPL_SYS_DCACHE_OFF=y | |
| 4 | +CONFIG_ARCH_IMX8M=y | |
| 5 | +CONFIG_SYS_TEXT_BASE=0x40200000 | |
| 6 | +CONFIG_SPL_GPIO_SUPPORT=y | |
| 7 | +CONFIG_SPL_LIBCOMMON_SUPPORT=y | |
| 8 | +CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
| 9 | +CONFIG_SYS_MALLOC_F_LEN=0x2000 | |
| 10 | +CONFIG_SYS_I2C_MXC_I2C1=y | |
| 11 | +CONFIG_SYS_I2C_MXC_I2C2=y | |
| 12 | +CONFIG_SYS_I2C_MXC_I2C3=y | |
| 13 | +CONFIG_ENV_SIZE=0x1000 | |
| 14 | +CONFIG_ENV_OFFSET=0x400000 | |
| 15 | +CONFIG_ENV_SECT_SIZE=0x10000 | |
| 16 | +CONFIG_DM_GPIO=y | |
| 17 | +CONFIG_TARGET_IMX8MN_DDR4_AB2=y | |
| 18 | +CONFIG_ARCH_MISC_INIT=y | |
| 19 | +CONFIG_SPL_SERIAL_SUPPORT=y | |
| 20 | +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | |
| 21 | +CONFIG_SPL=y | |
| 22 | +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | |
| 23 | +CONFIG_CSF_SIZE=0x2000 | |
| 24 | +CONFIG_SPL_TEXT_BASE=0x912000 | |
| 25 | +CONFIG_FIT=y | |
| 26 | +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | |
| 27 | +CONFIG_SPL_LOAD_FIT=y | |
| 28 | +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | |
| 29 | +CONFIG_OF_SYSTEM_SETUP=y | |
| 30 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg" | |
| 31 | +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-ab2" | |
| 32 | +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-ab2.dtb" | |
| 33 | +CONFIG_BOARD_LATE_INIT=y | |
| 34 | +CONFIG_BOARD_EARLY_INIT_F=y | |
| 35 | +CONFIG_SPL_BOARD_INIT=y | |
| 36 | +CONFIG_SPL_BOOTROM_SUPPORT=y | |
| 37 | +CONFIG_SPL_SEPARATE_BSS=y | |
| 38 | +CONFIG_SPL_I2C_SUPPORT=y | |
| 39 | +CONFIG_SPL_POWER_SUPPORT=y | |
| 40 | +CONFIG_NR_DRAM_BANKS=2 | |
| 41 | +CONFIG_HUSH_PARSER=y | |
| 42 | +CONFIG_SYS_PROMPT="u-boot=> " | |
| 43 | +# CONFIG_CMD_EXPORTENV is not set | |
| 44 | +# CONFIG_CMD_IMPORTENV is not set | |
| 45 | +CONFIG_CMD_ERASEENV=y | |
| 46 | +# CONFIG_CMD_CRC32 is not set | |
| 47 | +# CONFIG_BOOTM_NETBSD is not set | |
| 48 | +CONFIG_CMD_CLK=y | |
| 49 | +CONFIG_CMD_FUSE=y | |
| 50 | +CONFIG_CMD_GPIO=y | |
| 51 | +CONFIG_CMD_I2C=y | |
| 52 | +CONFIG_CMD_MMC=y | |
| 53 | +CONFIG_CMD_DHCP=y | |
| 54 | +CONFIG_CMD_MII=y | |
| 55 | +CONFIG_CMD_PING=y | |
| 56 | +CONFIG_CMD_CACHE=y | |
| 57 | +CONFIG_CMD_REGULATOR=y | |
| 58 | +CONFIG_CMD_MEMTEST=y | |
| 59 | +CONFIG_CMD_EXT2=y | |
| 60 | +CONFIG_CMD_EXT4=y | |
| 61 | +CONFIG_CMD_EXT4_WRITE=y | |
| 62 | +CONFIG_CMD_FAT=y | |
| 63 | +CONFIG_CMD_SF=y | |
| 64 | +CONFIG_OF_CONTROL=y | |
| 65 | +CONFIG_ENV_IS_IN_MMC=y | |
| 66 | +CONFIG_ENV_IS_IN_SPI_FLASH=y | |
| 67 | +CONFIG_ENV_IS_NOWHERE=y | |
| 68 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| 69 | +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | |
| 70 | +CONFIG_CLK_COMPOSITE_CCF=y | |
| 71 | +CONFIG_CLK_IMX8MN=y | |
| 72 | +CONFIG_MXC_GPIO=y | |
| 73 | + | |
| 74 | +CONFIG_DM_I2C=y | |
| 75 | +CONFIG_SYS_I2C_MXC=y | |
| 76 | +CONFIG_DM_MMC=y | |
| 77 | +CONFIG_MMC_IO_VOLTAGE=y | |
| 78 | +CONFIG_MMC_UHS_SUPPORT=y | |
| 79 | +CONFIG_MMC_HS400_SUPPORT=y | |
| 80 | +CONFIG_MMC_HS400_ES_SUPPORT=y | |
| 81 | +CONFIG_EFI_PARTITION=y | |
| 82 | +CONFIG_SUPPORT_EMMC_BOOT=y | |
| 83 | +CONFIG_FSL_ESDHC_IMX=y | |
| 84 | +CONFIG_DM_SPI_FLASH=y | |
| 85 | +CONFIG_DM_SPI=y | |
| 86 | +CONFIG_FSL_FSPI=y | |
| 87 | +CONFIG_SPI=y | |
| 88 | +CONFIG_SPI_FLASH=y | |
| 89 | +CONFIG_SPI_FLASH_BAR=y | |
| 90 | +CONFIG_SPI_FLASH_STMICRO=y | |
| 91 | +CONFIG_SF_DEFAULT_BUS=0 | |
| 92 | +CONFIG_SF_DEFAULT_CS=0 | |
| 93 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
| 94 | +CONFIG_SF_DEFAULT_MODE=0 | |
| 95 | + | |
| 96 | +CONFIG_PHYLIB=y | |
| 97 | +CONFIG_PHY_REALTEK=y | |
| 98 | +CONFIG_DM_ETH=y | |
| 99 | +CONFIG_PHY_GIGE=y | |
| 100 | +CONFIG_FEC_MXC=y | |
| 101 | +CONFIG_MII=y | |
| 102 | +CONFIG_PINCTRL=y | |
| 103 | +CONFIG_PINCTRL_IMX8M=y | |
| 104 | +CONFIG_DM_REGULATOR=y | |
| 105 | +CONFIG_DM_REGULATOR_FIXED=y | |
| 106 | +CONFIG_DM_REGULATOR_GPIO=y | |
| 107 | +CONFIG_MXC_UART=y | |
| 108 | +CONFIG_SYSRESET=y | |
| 109 | +CONFIG_SYSRESET_PSCI=y | |
| 110 | +CONFIG_DM_THERMAL=y | |
| 111 | +CONFIG_NXP_TMU=y | |
| 112 | + | |
| 113 | +CONFIG_OF_LIBFDT_OVERLAY=y |
include/configs/imx8mn_ab2.h
| 1 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 2 | +/* | |
| 3 | + * Copyright 2020 NXP | |
| 4 | + */ | |
| 5 | + | |
| 6 | +#ifndef __IMX8MN_AB2_H | |
| 7 | +#define __IMX8MN_AB2_H | |
| 8 | + | |
| 9 | +#include <linux/sizes.h> | |
| 10 | +#include <asm/arch/imx-regs.h> | |
| 11 | + | |
| 12 | +#include "imx_env.h" | |
| 13 | + | |
| 14 | +#define CONFIG_SPL_MAX_SIZE (208 * 1024) | |
| 15 | +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
| 16 | +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR | |
| 17 | +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 | |
| 18 | +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 | |
| 19 | +#define CONFIG_SYS_UBOOT_BASE \ | |
| 20 | + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) | |
| 21 | + | |
| 22 | +#ifdef CONFIG_SPL_BUILD | |
| 23 | +#define CONFIG_SPL_STACK 0x187FF0 | |
| 24 | +#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 | |
| 25 | +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ | |
| 26 | +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 | |
| 27 | +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_64K /* 64 KB */ | |
| 28 | + | |
| 29 | +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ | |
| 30 | +#define CONFIG_MALLOC_F_ADDR 0x184000 | |
| 31 | + | |
| 32 | +/* For RAW image gives a error info not panic */ | |
| 33 | +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE | |
| 34 | + | |
| 35 | +#define CONFIG_POWER | |
| 36 | +#define CONFIG_POWER_I2C | |
| 37 | +#ifdef CONFIG_IMX8M_DDR4 | |
| 38 | +#define CONFIG_POWER_BD71837 | |
| 39 | +#else | |
| 40 | +#define CONFIG_POWER_PCA9450 | |
| 41 | +#endif | |
| 42 | + | |
| 43 | +#define CONFIG_SYS_I2C | |
| 44 | + | |
| 45 | +#if defined(CONFIG_NAND_BOOT) | |
| 46 | +#define CONFIG_SPL_NAND_SUPPORT | |
| 47 | +#define CONFIG_SPL_DMA | |
| 48 | +#define CONFIG_SPL_NAND_MXS | |
| 49 | +#define CONFIG_SPL_NAND_BASE | |
| 50 | +#define CONFIG_SPL_NAND_IDENT | |
| 51 | +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ | |
| 52 | + | |
| 53 | +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ | |
| 54 | +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ | |
| 55 | + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) | |
| 56 | +#endif | |
| 57 | + | |
| 58 | +#endif | |
| 59 | + | |
| 60 | +#define CONFIG_CMD_READ | |
| 61 | +#define CONFIG_SERIAL_TAG | |
| 62 | + | |
| 63 | +#define CONFIG_REMAKE_ELF | |
| 64 | +/* ENET Config */ | |
| 65 | +/* ENET1 */ | |
| 66 | +#if defined(CONFIG_FEC_MXC) | |
| 67 | +#define CONFIG_ETHPRIME "eth0" | |
| 68 | + | |
| 69 | +#define CONFIG_FEC_XCV_TYPE RGMII | |
| 70 | +#define CONFIG_FEC_MXC_PHYADDR 1 | |
| 71 | +#define FEC_QUIRK_ENET_MAC | |
| 72 | + | |
| 73 | +#define IMX_FEC_BASE 0x30BE0000 | |
| 74 | +#endif | |
| 75 | + | |
| 76 | + | |
| 77 | +/* | |
| 78 | + * Another approach is add the clocks for inmates into clks_init_on | |
| 79 | + * in clk-imx8mm.c, then clk_ingore_unused could be removed. | |
| 80 | + */ | |
| 81 | +#define JAILHOUSE_ENV \ | |
| 82 | + "jh_clk= \0 " \ | |
| 83 | + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file imx8mn-ddr4-ab2-root.dtb;" \ | |
| 84 | + "setenv jh_clk clk_ignore_unused; " \ | |
| 85 | + "if run loadimage; then " \ | |
| 86 | + "run mmcboot; " \ | |
| 87 | + "else run jh_netboot; fi; \0" \ | |
| 88 | + "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file imx8mn-ddr4-ab2-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " | |
| 89 | + | |
| 90 | +#define CONFIG_MFG_ENV_SETTINGS \ | |
| 91 | + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ | |
| 92 | + "initrd_addr=0x43800000\0" \ | |
| 93 | + "initrd_high=0xffffffffffffffff\0" \ | |
| 94 | + "emmc_dev=2\0"\ | |
| 95 | + "sd_dev=1\0" \ | |
| 96 | + | |
| 97 | +/* Initial environment variables */ | |
| 98 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 99 | + CONFIG_MFG_ENV_SETTINGS \ | |
| 100 | + JAILHOUSE_ENV \ | |
| 101 | + "script=boot.scr\0" \ | |
| 102 | + "image=Image\0" \ | |
| 103 | + "console=ttymxc1,115200\0" \ | |
| 104 | + "fdt_addr=0x43000000\0" \ | |
| 105 | + "fdt_high=0xffffffffffffffff\0" \ | |
| 106 | + "boot_fit=no\0" \ | |
| 107 | + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ | |
| 108 | + "initrd_addr=0x43800000\0" \ | |
| 109 | + "initrd_high=0xffffffffffffffff\0" \ | |
| 110 | + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ | |
| 111 | + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ | |
| 112 | + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ | |
| 113 | + "mmcautodetect=yes\0" \ | |
| 114 | + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ | |
| 115 | + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
| 116 | + "bootscript=echo Running bootscript from mmc ...; " \ | |
| 117 | + "source\0" \ | |
| 118 | + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ | |
| 119 | + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
| 120 | + "mmcboot=echo Booting from mmc ...; " \ | |
| 121 | + "run mmcargs; " \ | |
| 122 | + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ | |
| 123 | + "bootm ${loadaddr}; " \ | |
| 124 | + "else " \ | |
| 125 | + "if run loadfdt; then " \ | |
| 126 | + "booti ${loadaddr} - ${fdt_addr}; " \ | |
| 127 | + "else " \ | |
| 128 | + "echo WARN: Cannot load the DT; " \ | |
| 129 | + "fi; " \ | |
| 130 | + "fi;\0" \ | |
| 131 | + "netargs=setenv bootargs ${jh_clk} console=${console} " \ | |
| 132 | + "root=/dev/nfs " \ | |
| 133 | + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
| 134 | + "netboot=echo Booting from net ...; " \ | |
| 135 | + "run netargs; " \ | |
| 136 | + "if test ${ip_dyn} = yes; then " \ | |
| 137 | + "setenv get_cmd dhcp; " \ | |
| 138 | + "else " \ | |
| 139 | + "setenv get_cmd tftp; " \ | |
| 140 | + "fi; " \ | |
| 141 | + "${get_cmd} ${loadaddr} ${image}; " \ | |
| 142 | + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ | |
| 143 | + "bootm ${loadaddr}; " \ | |
| 144 | + "else " \ | |
| 145 | + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
| 146 | + "booti ${loadaddr} - ${fdt_addr}; " \ | |
| 147 | + "else " \ | |
| 148 | + "echo WARN: Cannot load the DT; " \ | |
| 149 | + "fi; " \ | |
| 150 | + "fi;\0" | |
| 151 | + | |
| 152 | +#define CONFIG_BOOTCOMMAND \ | |
| 153 | + "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
| 154 | + "if run loadbootscript; then " \ | |
| 155 | + "run bootscript; " \ | |
| 156 | + "else " \ | |
| 157 | + "if run loadimage; then " \ | |
| 158 | + "run mmcboot; " \ | |
| 159 | + "else run netboot; " \ | |
| 160 | + "fi; " \ | |
| 161 | + "fi; " \ | |
| 162 | + "fi;" | |
| 163 | + | |
| 164 | +/* Link Definitions */ | |
| 165 | +#define CONFIG_LOADADDR 0x40480000 | |
| 166 | + | |
| 167 | +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
| 168 | + | |
| 169 | +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 | |
| 170 | +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 | |
| 171 | +#define CONFIG_SYS_INIT_SP_OFFSET \ | |
| 172 | + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 173 | +#define CONFIG_SYS_INIT_SP_ADDR \ | |
| 174 | + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
| 175 | + | |
| 176 | +#define CONFIG_ENV_OVERWRITE | |
| 177 | +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) | |
| 178 | +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
| 179 | +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
| 180 | +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
| 181 | +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
| 182 | +#endif | |
| 183 | +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ | |
| 184 | +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ | |
| 185 | + | |
| 186 | +/* Size of malloc() pool */ | |
| 187 | +#define CONFIG_SYS_MALLOC_LEN SZ_32M | |
| 188 | + | |
| 189 | +#define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
| 190 | +#define PHYS_SDRAM 0x40000000 | |
| 191 | +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ | |
| 192 | + | |
| 193 | +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
| 194 | +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) | |
| 195 | + | |
| 196 | +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR | |
| 197 | + | |
| 198 | +/* Monitor Command Prompt */ | |
| 199 | +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 200 | +#define CONFIG_SYS_CBSIZE 2048 | |
| 201 | +#define CONFIG_SYS_MAXARGS 64 | |
| 202 | +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 203 | +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
| 204 | + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 205 | + | |
| 206 | +#define CONFIG_IMX_BOOTAUX | |
| 207 | + | |
| 208 | +/* USDHC */ | |
| 209 | +#define CONFIG_FSL_USDHC | |
| 210 | + | |
| 211 | +#define CONFIG_SYS_FSL_USDHC_NUM 2 | |
| 212 | +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
| 213 | + | |
| 214 | +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 | |
| 215 | + | |
| 216 | +#ifdef CONFIG_FSL_FSPI | |
| 217 | +#define FSL_FSPI_FLASH_SIZE SZ_32M | |
| 218 | +#define FSL_FSPI_FLASH_NUM 1 | |
| 219 | +#define FSPI0_BASE_ADDR 0x30bb0000 | |
| 220 | +#define FSPI0_AMBA_BASE 0x0 | |
| 221 | +#define CONFIG_FSPI_QUAD_SUPPORT | |
| 222 | + | |
| 223 | +#define CONFIG_SYS_FSL_FSPI_AHB | |
| 224 | +#endif | |
| 225 | + | |
| 226 | +#ifdef CONFIG_NAND_MXS | |
| 227 | +#define CONFIG_CMD_NAND_TRIMFFS | |
| 228 | + | |
| 229 | +/* NAND stuff */ | |
| 230 | +#define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 231 | +#define CONFIG_SYS_NAND_BASE 0x20000000 | |
| 232 | +#define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
| 233 | +#define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 234 | +#define CONFIG_SYS_NAND_USE_FLASH_BBT | |
| 235 | +#endif /* CONFIG_NAND_MXS */ | |
| 236 | + | |
| 237 | +#define CONFIG_SYS_I2C_SPEED 100000 | |
| 238 | + | |
| 239 | +#endif |