make change to hardware revision 00E0

Eric Lee
1 parent afba354e26
Showing 3 changed files with 11 additions and 11 deletions Side-by-side Diff
arch/arm/dts/imx7d-smarcfimx7.dts
arch/arm/dts/imx7s-smarcfimx7.dts
include/configs/smarcfimx7.h
@@ -216,7 +216,7 @@
 				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
 				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy0>;
 	fsl,magic-packet;
 	status = "okay";
  
  
  
@@ -225,14 +225,14 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
  
-		ethphy0: ethernet-phy@6 {
+		ethphy0: ethernet-phy@1 {
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
+			reg = <1>;
 		};
  
-		ethphy1: ethernet-phy@7 {
+		ethphy1: ethernet-phy@2 {
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
+			reg = <2>;
 		};
 	};
 };
@@ -249,7 +249,7 @@
 				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
 				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy1>;
 	fsl,magic-packet;
 	status = "okay";
@@ -190,9 +190,9 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
  
-		ethphy0: ethernet-phy@6 {
+		ethphy0: ethernet-phy@1 {
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
+			reg = <1>;
 		};
 	};
 };
@@ -35,15 +35,15 @@
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_FEC_ENET_DEV		0
  
-#define CONFIG_PHY_ATHEROS
+#define CONFIG_PHY_REALTEK
 /* ENET1 */
 #if (CONFIG_FEC_ENET_DEV == 0)
 #define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR          0x6
+#define CONFIG_FEC_MXC_PHYADDR          0x1
 #define CONFIG_ETHPRIME                 "eth0"
 #elif (CONFIG_FEC_ENET_DEV == 1)
 #define IMX_FEC_BASE			ENET2_IPS_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR          0x7
+#define CONFIG_FEC_MXC_PHYADDR          0x2
 #define CONFIG_ETHPRIME                 "eth1"
 #endif
...	...	@@ -216,7 +216,7 @@
216	216	<&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
217	217	<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
218	218	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
219		- phy-mode = "rgmii";
	219	+ phy-mode = "rgmii-id";
220	220	phy-handle = <&ethphy0>;
221	221	fsl,magic-packet;
222	222	status = "okay";
223	223
224	224
225	225
...	...	@@ -225,14 +225,14 @@
225	225	#address-cells = <1>;
226	226	#size-cells = <0>;
227	227
228		- ethphy0: ethernet-phy@6 {
	228	+ ethphy0: ethernet-phy@1 {
229	229	compatible = "ethernet-phy-ieee802.3-c22";
230		- reg = <0>;
	230	+ reg = <1>;
231	231	};
232	232
233		- ethphy1: ethernet-phy@7 {
	233	+ ethphy1: ethernet-phy@2 {
234	234	compatible = "ethernet-phy-ieee802.3-c22";
235		- reg = <1>;
	235	+ reg = <2>;
236	236	};
237	237	};
238	238	};
...	...	@@ -249,7 +249,7 @@
249	249	<&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
250	250	<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
251	251	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
252		- phy-mode = "rgmii";
	252	+ phy-mode = "rgmii-id";
253	253	phy-handle = <&ethphy1>;
254	254	fsl,magic-packet;
255	255	status = "okay";
...	...	@@ -190,9 +190,9 @@
190	190	#address-cells = <1>;
191	191	#size-cells = <0>;
192	192
193		- ethphy0: ethernet-phy@6 {
	193	+ ethphy0: ethernet-phy@1 {
194	194	compatible = "ethernet-phy-ieee802.3-c22";
195		- reg = <0>;
	195	+ reg = <1>;
196	196	};
197	197	};
198	198	};
...	...	@@ -35,15 +35,15 @@
35	35	#define CONFIG_FEC_XCV_TYPE RGMII
36	36	#define CONFIG_FEC_ENET_DEV 0
37	37
38		-#define CONFIG_PHY_ATHEROS
	38	+#define CONFIG_PHY_REALTEK
39	39	/* ENET1 */
40	40	#if (CONFIG_FEC_ENET_DEV == 0)
41	41	#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
42		-#define CONFIG_FEC_MXC_PHYADDR 0x6
	42	+#define CONFIG_FEC_MXC_PHYADDR 0x1
43	43	#define CONFIG_ETHPRIME "eth0"
44	44	#elif (CONFIG_FEC_ENET_DEV == 1)
45	45	#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR
46		-#define CONFIG_FEC_MXC_PHYADDR 0x7
	46	+#define CONFIG_FEC_MXC_PHYADDR 0x2
47	47	#define CONFIG_ETHPRIME "eth1"
48	48	#endif
49	49