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Commit 97405d843ece2a53e67b801e02ee42005d26e172

Authored by Lokesh Vutla
Committed by Tom Rini
1 parent 7f36c88f64
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: DRA7xx: clocks: Update PLL values 

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>

Showing 7 changed files with 73 additions and 46 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap-common/clocks-common.c
Diff comments   View file @ 97405d8
... ... @@ -50,13 +50,12 @@
50 50  
51 51 const u32 sys_clk_array[8] = {
52 52 12000000, /* 12 MHz */
53   - 13000000, /* 13 MHz */
  53 + 20000000, /* 20 MHz */
54 54 16800000, /* 16.8 MHz */
55 55 19200000, /* 19.2 MHz */
56 56 26000000, /* 26 MHz */
57 57 27000000, /* 27 MHz */
58 58 38400000, /* 38.4 MHz */
59   - 20000000, /* 20 MHz */
60 59 };
61 60  
62 61 static inline u32 __get_sys_clk_index(void)
... ... @@ -75,13 +74,6 @@
75 74 /* SYS_CLKSEL - 1 to match the dpll param array indices */
76 75 ind = (readl((*prcm)->cm_sys_clksel) &
77 76 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
78   - /*
79   - * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
80   - * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
81   - * NUM_SYS_CLK. So considering the last 3 bits as the index
82   - * for the dpll param array.
83   - */
84   - ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
85 77 }
86 78 return ind;
87 79 }
... ... @@ -441,6 +433,12 @@
441 433 params = get_abe_dpll_params(*dplls_data);
442 434 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
443 435 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
  436 +
  437 + if (omap_revision() == DRA752_ES1_0)
  438 + /* Select the sys clk for dpll_abe */
  439 + clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
  440 + CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
  441 + CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
444 442 #else
445 443 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
446 444 /*
arch/arm/cpu/armv7/omap5/hw_data.c
Diff comments   View file @ 97405d8
... ... @@ -100,14 +100,13 @@
100 100 };
101 101  
102 102 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
103   - {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
104   - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
105   - {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
106   - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
107   - {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  103 + {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  104 + {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  105 + {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  106 + {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  107 + {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
108 108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
109   - {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
110   - {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
  109 + {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
111 110 };
112 111  
113 112 static const struct dpll_params
114 113  
... ... @@ -133,15 +132,14 @@
133 132 };
134 133  
135 134 static const struct dpll_params
136   - core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
137   - {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
138   - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
139   - {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
140   - {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
141   - {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
  135 + core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
  136 + {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
  137 + {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
  138 + {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
  139 + {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
  140 + {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
142 141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
143   - {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
144   - {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
  142 + {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
145 143 };
146 144  
147 145 static const struct dpll_params
148 146  
... ... @@ -187,14 +185,13 @@
187 185 };
188 186  
189 187 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
190   - {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
191   - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
192   - {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
193   - {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
194   - {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
  188 + {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
  189 + {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
  190 + {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  191 + {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  192 + {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
195 193 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
196   - {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
197   - {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
  194 + {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
198 195 };
199 196  
200 197 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
... ... @@ -207,6 +204,16 @@
207 204 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
208 205 };
209 206  
  207 +static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
  208 + {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  209 + {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  210 + {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  211 + {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  212 + {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  213 + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  214 + {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  215 +};
  216 +
210 217 /* ABE M & N values with sys_clk as source */
211 218 static const struct dpll_params
212 219 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
213 220  
214 221  
215 222  
216 223  
... ... @@ -224,26 +231,36 @@
224 231 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
225 232 };
226 233  
  234 +/* ABE M & N values with sysclk2(22.5792 MHz) as input */
  235 +static const struct dpll_params
  236 + abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
  237 + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  238 + {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  239 + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  240 + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  241 + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  242 + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  243 + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  244 +};
  245 +
227 246 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
228 247 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
229   - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  248 + {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
230 249 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
231 250 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
232 251 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
233 252 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
234 253 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
235   - {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
236 254 };
237 255  
238   -static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
239   - {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
240   - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
241   - {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
242   - {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
243   - {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  256 +static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
  257 + {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  258 + {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  259 + {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  260 + {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  261 + {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
244 262 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
245   - {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
246   - {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
  263 + {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
247 264 };
248 265  
249 266 struct dplls omap5_dplls_es1 = {
250 267  
251 268  
... ... @@ -276,10 +293,12 @@
276 293  
277 294 struct dplls dra7xx_dplls = {
278 295 .mpu = mpu_dpll_params_1ghz,
279   - .core = core_dpll_params_2128mhz_ddr532_dra7xx,
  296 + .core = core_dpll_params_2128mhz_dra7xx,
280 297 .per = per_dpll_params_768mhz_dra7xx,
  298 + .abe = abe_dpll_params_sysclk2_361267khz,
  299 + .iva = iva_dpll_params_2330mhz_dra7xx,
281 300 .usb = usb_dpll_params_1920mhz,
282   - .ddr = ddr_dpll_params_1066mhz,
  301 + .ddr = ddr_dpll_params_2128mhz,
283 302 };
284 303  
285 304 struct pmic_data palmas = {
arch/arm/cpu/armv7/omap5/prcm-regs.c
Diff comments   View file @ 97405d8
... ... @@ -951,6 +951,7 @@
951 951 /* l4 wkup regs */
952 952 .cm_abe_pll_ref_clksel = 0x4ae0610c,
953 953 .cm_sys_clksel = 0x4ae06110,
  954 + .cm_abe_pll_sys_clksel = 0x4ae06118,
954 955 .cm_wkup_clkstctrl = 0x4ae07800,
955 956 .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
956 957 .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
arch/arm/include/asm/arch-omap4/clock.h
Diff comments   View file @ 97405d8
... ... @@ -76,7 +76,7 @@
76 76 #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
77 77  
78 78 /* CM_SYS_CLKSEL */
79   -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
  79 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
80 80  
81 81 /* CM_CLKSEL_CORE */
82 82 #define CLKSEL_CORE_SHIFT 0
arch/arm/include/asm/arch-omap5/clock.h
Diff comments   View file @ 97405d8
... ... @@ -81,7 +81,7 @@
81 81 #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
82 82  
83 83 /* CM_SYS_CLKSEL */
84   -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
  84 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
85 85  
86 86 /* CM_CLKSEL_CORE */
87 87 #define CLKSEL_CORE_SHIFT 0
... ... @@ -97,6 +97,12 @@
97 97 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
98 98 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
99 99 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
  100 +
  101 +/* CM_CLKSEL_ABE_PLL_SYS */
  102 +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0
  103 +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1
  104 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0
  105 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1
100 106  
101 107 /* CM_BYPCLK_DPLL_IVA */
102 108 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
arch/arm/include/asm/omap_common.h
Diff comments   View file @ 97405d8
... ... @@ -29,7 +29,7 @@
29 29  
30 30 #include <common.h>
31 31  
32   -#define NUM_SYS_CLKS 8
  32 +#define NUM_SYS_CLKS 7
33 33  
34 34 struct prcm_regs {
35 35 /* cm1.ckgen */
... ... @@ -303,6 +303,7 @@
303 303 /* l4 wkup regs */
304 304 u32 cm_abe_pll_ref_clksel;
305 305 u32 cm_sys_clksel;
  306 + u32 cm_abe_pll_sys_clksel;
306 307 u32 cm_wkup_clkstctrl;
307 308 u32 cm_wkup_l4wkup_clkctrl;
308 309 u32 cm_wkup_wdtimer1_clkctrl;
include/configs/dra7xx_evm.h
Diff comments   View file @ 97405d8
... ... @@ -39,5 +39,7 @@
39 39 #define CONFIG_CONS_INDEX 1
40 40 #define CONFIG_SYS_NS16550_COM1 UART1_BASE
41 41 #define CONFIG_BAUDRATE 115200
  42 +
  43 +#define CONFIG_SYS_OMAP_ABE_SYSCK
42 44 #endif /* __CONFIG_DRA7XX_EVM_H */