Eric Lee / smarc-uboot

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Commit f5e0d03970409feb3c77ab0107d5dece6b7d45c9

Authored by Heiko Schocher
1 parent 8d352247ec
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Add support for wrPPMC7xx/74xx boards 

Patch from Richard Danter, 12 Aug 2005

Showing 16 changed files with 1703 additions and 4 deletions Side-by-side Diff

... ... @@ -2,6 +2,9 @@
2 2 Changes since U-Boot 1.1.4:
3 3 ======================================================================
4 4  
  5 +* Add support for wrPPMC7xx/74xx boards
  6 + Patch from Richard Danter, 12 Aug 2005
  7 +
5 8 * Add support for gth2 board
6 9 Patch by Thomas Lange, Aug 11 2005
7 10  
... ... @@ -105,6 +105,10 @@
105 105 E: damm@opensource.se
106 106 D: 8xxrom
107 107  
  108 +N: Richard Danter
  109 +E: richard.danter@windriver.com
  110 +D: Support for Wind River PPMC 7xx/74xx boards
  111 +
108 112 N: George G. Davis
109 113 E: gdavis@mvista.com
110 114 D: Board ports for ADS GraphicsClient+ and Intel Assabet
... ... @@ -142,7 +142,7 @@
142 142 "
143 143  
144 144 LIST_7xx=" \
145   - BAB7xx CPCI750 ELPPC \
  145 + BAB7xx CPCI750 ELPPC ppmc7xx \
146 146 "
147 147  
148 148 LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
... ... @@ -1452,6 +1452,9 @@
1452 1452 ZUMA_config: unconfig
1453 1453 @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
1454 1454  
  1455 +ppmc7xx_config: unconfig
  1456 + @./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
  1457 +
1455 1458 #========================================================================
1456 1459 # ARM
1457 1460 #========================================================================
board/ppmc7xx/Makefile
Diff comments   View file @ f5e0d03
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS := ppmc7xx.o pci.o flash.o
  29 +SOBJS := init.o
  30 +
  31 +$(LIB): .depend $(OBJS) $(SOBJS)
  32 + $(AR) crv $@ $(OBJS) $(SOBJS)
  33 +
  34 +clean:
  35 + rm -f $(SOBJS) $(OBJS)
  36 +
  37 +distclean: clean
  38 + rm -f $(LIB) core *.bak .depend
  39 +
  40 +#########################################################################
  41 +
  42 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  43 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  44 +
  45 +-include .depend
  46 +
  47 +#########################################################################
board/ppmc7xx/config.mk
Diff comments   View file @ f5e0d03
  1 +#
  2 +# (C) Copyright 2005
  3 +# Richard Danter, Wind River Systems
  4 +#
  5 +# (C) Copyright 2000
  6 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7 +#
  8 +# See file CREDITS for list of people who contributed to this
  9 +# project.
  10 +#
  11 +# This program is free software; you can redistribute it and/or
  12 +# modify it under the terms of the GNU General Public License as
  13 +# published by the Free Software Foundation; either version 2 of
  14 +# the License, or (at your option) any later version.
  15 +#
  16 +# This program is distributed in the hope that it will be useful,
  17 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 +# GNU General Public License for more details.
  20 +#
  21 +# You should have received a copy of the GNU General Public License
  22 +# along with this program; if not, write to the Free Software
  23 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 +# MA 02111-1307 USA
  25 +#
  26 +
  27 +#
  28 +#
  29 +#
  30 +
  31 +TEXT_BASE = 0xFFF00000
  32 +TEXT_END = 0xFFF40000
  33 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
board/ppmc7xx/flash.c
Diff comments   View file @ f5e0d03
  1 +/*
  2 + * flash.c
  3 + * -------
  4 + *
  5 + * Flash programming routines for the Wind River PPMC 74xx/7xx
  6 + * based on flash.c from the TQM8260 board.
  7 + *
  8 + * By Richard Danter (richard.danter@windriver.com)
  9 + * Copyright (C) 2005 Wind River Systems
  10 + */
  11 +
  12 +#include <common.h>
  13 +#include <asm/processor.h>
  14 +#include <74xx_7xx.h>
  15 +
  16 +#define DWORD unsigned long long
  17 +
  18 +/* Local function prototypes */
  19 +static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
  20 +static void write_via_fpu (volatile DWORD* addr, DWORD* data);
  21 +
  22 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  23 +
  24 +/*-----------------------------------------------------------------------
  25 + */
  26 +void flash_reset (void)
  27 +{
  28 + unsigned long msr;
  29 + DWORD cmd_reset = 0x00F000F000F000F0LL;
  30 +
  31 + if (flash_info[0].flash_id != FLASH_UNKNOWN) {
  32 + msr = get_msr ();
  33 + set_msr (msr | MSR_FP);
  34 +
  35 + write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
  36 +
  37 + set_msr (msr);
  38 + }
  39 +}
  40 +
  41 +/*-----------------------------------------------------------------------
  42 + */
  43 +ulong flash_get_size (ulong baseaddr, flash_info_t * info)
  44 +{
  45 + int i;
  46 + unsigned long msr;
  47 + DWORD flashtest;
  48 + DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
  49 + 0x0090009000900090LL };
  50 +
  51 + /* Enable FPU */
  52 + msr = get_msr ();
  53 + set_msr (msr | MSR_FP);
  54 +
  55 + /* Write auto-select command sequence */
  56 + write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
  57 + write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
  58 + write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
  59 +
  60 + /* Restore FPU */
  61 + set_msr (msr);
  62 +
  63 + /* Read manufacturer ID */
  64 + flashtest = *(volatile DWORD*)baseaddr;
  65 + switch ((int)flashtest) {
  66 + case AMD_MANUFACT:
  67 + info->flash_id = FLASH_MAN_AMD;
  68 + break;
  69 + case FUJ_MANUFACT:
  70 + info->flash_id = FLASH_MAN_FUJ;
  71 + break;
  72 + default:
  73 + /* No, faulty or unknown flash */
  74 + info->flash_id = FLASH_UNKNOWN;
  75 + info->sector_count = 0;
  76 + info->size = 0;
  77 + return (0);
  78 + }
  79 +
  80 + /* Read device ID */
  81 + flashtest = *(volatile DWORD*)(baseaddr + 8);
  82 + switch ((long)flashtest) {
  83 + case AMD_ID_LV800T:
  84 + info->flash_id += FLASH_AM800T;
  85 + info->sector_count = 19;
  86 + info->size = 0x00400000;
  87 + break;
  88 + case AMD_ID_LV800B:
  89 + info->flash_id += FLASH_AM800B;
  90 + info->sector_count = 19;
  91 + info->size = 0x00400000;
  92 + break;
  93 + case AMD_ID_LV160T:
  94 + info->flash_id += FLASH_AM160T;
  95 + info->sector_count = 35;
  96 + info->size = 0x00800000;
  97 + break;
  98 + case AMD_ID_LV160B:
  99 + info->flash_id += FLASH_AM160B;
  100 + info->sector_count = 35;
  101 + info->size = 0x00800000;
  102 + break;
  103 + case AMD_ID_DL322T:
  104 + info->flash_id += FLASH_AMDL322T;
  105 + info->sector_count = 71;
  106 + info->size = 0x01000000;
  107 + break;
  108 + case AMD_ID_DL322B:
  109 + info->flash_id += FLASH_AMDL322B;
  110 + info->sector_count = 71;
  111 + info->size = 0x01000000;
  112 + break;
  113 + case AMD_ID_DL323T:
  114 + info->flash_id += FLASH_AMDL323T;
  115 + info->sector_count = 71;
  116 + info->size = 0x01000000;
  117 + break;
  118 + case AMD_ID_DL323B:
  119 + info->flash_id += FLASH_AMDL323B;
  120 + info->sector_count = 71;
  121 + info->size = 0x01000000;
  122 + break;
  123 + case AMD_ID_LV640U:
  124 + info->flash_id += FLASH_AM640U;
  125 + info->sector_count = 128;
  126 + info->size = 0x02000000;
  127 + break;
  128 + default:
  129 + /* Unknown flash type */
  130 + info->flash_id = FLASH_UNKNOWN;
  131 + return (0);
  132 + }
  133 +
  134 + if ((long)flashtest == AMD_ID_LV640U) {
  135 + /* set up sector start adress table (uniform sector type) */
  136 + for (i = 0; i < info->sector_count; i++)
  137 + info->start[i] = baseaddr + (i * 0x00040000);
  138 + } else if (info->flash_id & FLASH_BTYPE) {
  139 + /* set up sector start adress table (bottom sector type) */
  140 + info->start[0] = baseaddr + 0x00000000;
  141 + info->start[1] = baseaddr + 0x00010000;
  142 + info->start[2] = baseaddr + 0x00018000;
  143 + info->start[3] = baseaddr + 0x00020000;
  144 + for (i = 4; i < info->sector_count; i++) {
  145 + info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
  146 + }
  147 + } else {
  148 + /* set up sector start adress table (top sector type) */
  149 + i = info->sector_count - 1;
  150 + info->start[i--] = baseaddr + info->size - 0x00010000;
  151 + info->start[i--] = baseaddr + info->size - 0x00018000;
  152 + info->start[i--] = baseaddr + info->size - 0x00020000;
  153 + for (; i >= 0; i--) {
  154 + info->start[i] = baseaddr + i * 0x00040000;
  155 + }
  156 + }
  157 +
  158 + /* check for protected sectors */
  159 + for (i = 0; i < info->sector_count; i++) {
  160 + /* read sector protection at sector address, (A7 .. A0) = 0x02 */
  161 + if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
  162 + info->protect[i] = 1; /* D0 = 1 if protected */
  163 + } else {
  164 + info->protect[i] = 0;
  165 + }
  166 + }
  167 +
  168 + flash_reset ();
  169 + return (info->size);
  170 +}
  171 +
  172 +/*-----------------------------------------------------------------------
  173 + */
  174 +unsigned long flash_init (void)
  175 +{
  176 + unsigned long size_b0 = 0;
  177 + int i;
  178 +
  179 + /* Init: no FLASHes known */
  180 + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
  181 + flash_info[i].flash_id = FLASH_UNKNOWN;
  182 + }
  183 +
  184 + /* Static FLASH Bank configuration here (only one bank) */
  185 + size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
  186 + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
  187 + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
  188 + size_b0, size_b0 >> 20);
  189 + }
  190 +
  191 + /*
  192 + * protect monitor and environment sectors
  193 + */
  194 +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
  195 + flash_protect (FLAG_PROTECT_SET,
  196 + CFG_MONITOR_BASE,
  197 + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
  198 +#endif
  199 +
  200 +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
  201 +# ifndef CFG_ENV_SIZE
  202 +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
  203 +# endif
  204 + flash_protect (FLAG_PROTECT_SET,
  205 + CFG_ENV_ADDR,
  206 + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
  207 +#endif
  208 +
  209 + return (size_b0);
  210 +}
  211 +
  212 +/*-----------------------------------------------------------------------
  213 + */
  214 +void flash_print_info (flash_info_t * info)
  215 +{
  216 + int i;
  217 +
  218 + if (info->flash_id == FLASH_UNKNOWN) {
  219 + printf ("missing or unknown FLASH type\n");
  220 + return;
  221 + }
  222 +
  223 + switch (info->flash_id & FLASH_VENDMASK) {
  224 + case FLASH_MAN_AMD:
  225 + printf ("AMD ");
  226 + break;
  227 + case FLASH_MAN_FUJ:
  228 + printf ("FUJITSU ");
  229 + break;
  230 + default:
  231 + printf ("Unknown Vendor ");
  232 + break;
  233 + }
  234 +
  235 + switch (info->flash_id & FLASH_TYPEMASK) {
  236 + case FLASH_AM800T:
  237 + printf ("29LV800T (8 M, top sector)\n");
  238 + break;
  239 + case FLASH_AM800B:
  240 + printf ("29LV800T (8 M, bottom sector)\n");
  241 + break;
  242 + case FLASH_AM160T:
  243 + printf ("29LV160T (16 M, top sector)\n");
  244 + break;
  245 + case FLASH_AM160B:
  246 + printf ("29LV160B (16 M, bottom sector)\n");
  247 + break;
  248 + case FLASH_AMDL322T:
  249 + printf ("29DL322T (32 M, top sector)\n");
  250 + break;
  251 + case FLASH_AMDL322B:
  252 + printf ("29DL322B (32 M, bottom sector)\n");
  253 + break;
  254 + case FLASH_AMDL323T:
  255 + printf ("29DL323T (32 M, top sector)\n");
  256 + break;
  257 + case FLASH_AMDL323B:
  258 + printf ("29DL323B (32 M, bottom sector)\n");
  259 + break;
  260 + case FLASH_AM640U:
  261 + printf ("29LV640D (64 M, uniform sector)\n");
  262 + break;
  263 + default:
  264 + printf ("Unknown Chip Type\n");
  265 + break;
  266 + }
  267 +
  268 + printf (" Size: %ld MB in %d Sectors\n",
  269 + info->size >> 20, info->sector_count);
  270 +
  271 + printf (" Sector Start Addresses:");
  272 + for (i = 0; i < info->sector_count; ++i) {
  273 + if ((i % 5) == 0)
  274 + printf ("\n ");
  275 + printf (" %08lX%s",
  276 + info->start[i],
  277 + info->protect[i] ? " (RO)" : " "
  278 + );
  279 + }
  280 + printf ("\n");
  281 + return;
  282 +}
  283 +
  284 +/*-----------------------------------------------------------------------
  285 + */
  286 +int flash_erase (flash_info_t * info, int s_first, int s_last)
  287 +{
  288 + int flag, prot, sect, l_sect;
  289 + ulong start, now, last;
  290 + unsigned long msr;
  291 + DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
  292 + 0x0080008000800080LL, 0x00AA00AA00AA00AALL,
  293 + 0x0055005500550055LL, 0x0030003000300030LL };
  294 +
  295 + if ((s_first < 0) || (s_first > s_last)) {
  296 + if (info->flash_id == FLASH_UNKNOWN) {
  297 + printf ("- missing\n");
  298 + } else {
  299 + printf ("- no sectors to erase\n");
  300 + }
  301 + return 1;
  302 + }
  303 +
  304 + prot = 0;
  305 + for (sect = s_first; sect <= s_last; sect++) {
  306 + if (info->protect[sect])
  307 + prot++;
  308 + }
  309 +
  310 + if (prot) {
  311 + printf ("- Warning: %d protected sectors will not be erased!\n",
  312 + prot);
  313 + } else {
  314 + printf ("\n");
  315 + }
  316 +
  317 + l_sect = -1;
  318 +
  319 + /* Enable FPU */
  320 + msr = get_msr();
  321 + set_msr ( msr | MSR_FP );
  322 +
  323 + /* Disable interrupts which might cause a timeout here */
  324 + flag = disable_interrupts ();
  325 +
  326 + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
  327 + write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
  328 + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
  329 + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
  330 + write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
  331 + udelay (1000);
  332 +
  333 + /* Start erase on unprotected sectors */
  334 + for (sect = s_first; sect <= s_last; sect++) {
  335 + if (info->protect[sect] == 0) { /* not protected */
  336 + write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
  337 + l_sect = sect;
  338 + }
  339 + }
  340 +
  341 + /* re-enable interrupts if necessary */
  342 + if (flag)
  343 + enable_interrupts ();
  344 +
  345 + /* Restore FPU */
  346 + set_msr (msr);
  347 +
  348 + /* wait at least 80us - let's wait 1 ms */
  349 + udelay (1000);
  350 +
  351 + /*
  352 + * We wait for the last triggered sector
  353 + */
  354 + if (l_sect < 0)
  355 + goto DONE;
  356 +
  357 + start = get_timer (0);
  358 + last = start;
  359 + while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
  360 + != 0x0080008000800080LL )
  361 + {
  362 + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
  363 + printf ("Timeout\n");
  364 + return 1;
  365 + }
  366 + /* show that we're waiting */
  367 + if ((now - last) > 1000) { /* every second */
  368 + serial_putc ('.');
  369 + last = now;
  370 + }
  371 + }
  372 +
  373 + DONE:
  374 + /* reset to read mode */
  375 + flash_reset ();
  376 +
  377 + printf (" done\n");
  378 + return 0;
  379 +}
  380 +
  381 +
  382 +/*-----------------------------------------------------------------------
  383 + * Copy memory to flash, returns:
  384 + * 0 - OK
  385 + * 1 - write timeout
  386 + * 2 - Flash not erased
  387 + */
  388 +
  389 +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  390 +{
  391 + ulong dp;
  392 + static unsigned char bb[8];
  393 + int i, l, rc, cc = cnt;
  394 +
  395 + dp = (addr & ~7); /* get lower dword aligned address */
  396 +
  397 + /*
  398 + * handle unaligned start bytes
  399 + */
  400 + if ((l = addr - dp) != 0) {
  401 + for (i = 0; i < 8; i++)
  402 + bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
  403 + if ((rc = write_dword (info, dp, bb)) != 0) {
  404 + return (rc);
  405 + }
  406 + dp += 8;
  407 + cc -= 8 - l;
  408 + }
  409 +
  410 + /*
  411 + * handle word aligned part
  412 + */
  413 + while (cc >= 8) {
  414 + if ((rc = write_dword (info, dp, src)) != 0) {
  415 + return (rc);
  416 + }
  417 + dp += 8;
  418 + src += 8;
  419 + cc -= 8;
  420 + }
  421 +
  422 + if (cc <= 0) {
  423 + return (0);
  424 + }
  425 +
  426 + /*
  427 + * handle unaligned tail bytes
  428 + */
  429 + for (i = 0; i < 8; i++) {
  430 + bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
  431 + }
  432 + return (write_dword (info, dp, bb));
  433 +}
  434 +
  435 +/*-----------------------------------------------------------------------
  436 + * Write a dword to Flash, returns:
  437 + * 0 - OK
  438 + * 1 - write timeout
  439 + * 2 - Flash not erased
  440 + */
  441 +static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
  442 +{
  443 + ulong start;
  444 + unsigned long msr;
  445 + int flag, i;
  446 + DWORD data;
  447 + DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
  448 + 0x00A000A000A000A0LL };
  449 +
  450 + for (data = 0, i = 0; i < 8; i++)
  451 + data = (data << 8) + *pdata++;
  452 +
  453 + /* Check if Flash is (sufficiently) erased */
  454 + if ((*(DWORD*)dest & data) != data) {
  455 + return (2);
  456 + }
  457 +
  458 + /* Enable FPU */
  459 + msr = get_msr();
  460 + set_msr( msr | MSR_FP );
  461 +
  462 + /* Disable interrupts which might cause a timeout here */
  463 + flag = disable_interrupts ();
  464 +
  465 + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
  466 + write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
  467 + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
  468 + write_via_fpu ((DWORD*)dest, &data );
  469 +
  470 + /* re-enable interrupts if necessary */
  471 + if (flag)
  472 + enable_interrupts ();
  473 +
  474 + /* Restore FPU */
  475 + set_msr(msr);
  476 +
  477 + /* data polling for D7 */
  478 + start = get_timer (0);
  479 + while (*(volatile DWORD*)dest != data ) {
  480 + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
  481 + return (1);
  482 + }
  483 + }
  484 + return (0);
  485 +}
  486 +
  487 +/*-----------------------------------------------------------------------
  488 + */
  489 +static void write_via_fpu (volatile DWORD* addr, DWORD* data)
  490 +{
  491 + __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
  492 + __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
  493 + __asm__ __volatile__ ("eieio");
  494 +}
board/ppmc7xx/init.S
Diff comments   View file @ f5e0d03
  1 +/*
  2 + * init.S
  3 + * ------
  4 + *
  5 + * Wind River PPMC 7xx/74xx init code.
  6 + *
  7 + * By Richard Danter (richard.danter@windriver.com)
  8 + * Copyright (C) 2005 Wind River Systems
  9 + *
  10 + * NOTE: The following code was generated automatically by Workbench
  11 + * from the ppmc7400_107.reg register file.
  12 + */
  13 +
  14 +#include <ppc_asm.tmpl>
  15 +
  16 +
  17 +.globl board_asm_init
  18 +board_asm_init:
  19 +
  20 + lis r4,0xFEC0
  21 + ori r4,r4,0x0000
  22 + lis r5,0xFEE0
  23 + ori r5,r5,0x0000
  24 + lis r3,0x8000 # ADDR_00
  25 + ori r3,r3,0x0000
  26 + stwbrx r3,0,r4
  27 + li r3,0x1057 # VENDOR
  28 + li r8, 0x0
  29 + sthbrx r3,r8,r5
  30 + lis r3,0x8000 # ADDR_02
  31 + ori r3,r3,0x0002
  32 + stwbrx r3,0,r4
  33 + li r3,0x0004 # ID
  34 + li r8, 0x2
  35 + sthbrx r3,r8,r5
  36 + lis r3,0x8000 # ADDR_04
  37 + ori r3,r3,0x0004
  38 + stwbrx r3,0,r4
  39 + li r3,0x0006 # PCICMD
  40 + li r8, 0x0
  41 + sthbrx r3,r8,r5
  42 + lis r3,0x8000 # ADDR_06
  43 + ori r3,r3,0x0006
  44 + stwbrx r3,0,r4
  45 + li r3,0x00A0 # PCISTAT
  46 + li r8, 0x2
  47 + sthbrx r3,r8,r5
  48 + lis r3,0x8000 # ADDR_08
  49 + ori r3,r3,0x0008
  50 + stwbrx r3,0,r4
  51 + li r3,0x10 # REVID
  52 + stb r3,0x0(r5)
  53 + lis r3,0x8000 # ADDR_09
  54 + ori r3,r3,0x0009
  55 + stwbrx r3,0,r4
  56 + li r3,0x00 # PROGIR
  57 + stb r3,0x1(r5)
  58 + lis r3,0x8000 # ADDR_0A
  59 + ori r3,r3,0x000A
  60 + stwbrx r3,0,r4
  61 + li r3,0x00 # SUBCCODE
  62 + stb r3,0x2(r5)
  63 + lis r3,0x8000 # ADDR_0B
  64 + ori r3,r3,0x000B
  65 + stwbrx r3,0,r4
  66 + li r3,0x06 # PBCCR
  67 + stb r3,0x3(r5)
  68 + lis r3,0x8000 # ADDR_0C
  69 + ori r3,r3,0x000C
  70 + stwbrx r3,0,r4
  71 + li r3,0x08 # PCLSR
  72 + stb r3,0x0(r5)
  73 + lis r3,0x8000 # ADDR_0D
  74 + ori r3,r3,0x000D
  75 + stwbrx r3,0,r4
  76 + li r3,0x00 # PLTR
  77 + stb r3,0x1(r5)
  78 + lis r3,0x8000 # ADDR_0E
  79 + ori r3,r3,0x000E
  80 + stwbrx r3,0,r4
  81 + li r3,0x00 # HEADTYPE
  82 + stb r3,0x2(r5)
  83 + lis r3,0x8000 # ADDR_0F
  84 + ori r3,r3,0x000F
  85 + stwbrx r3,0,r4
  86 + li r3,0x00 # BISTCTRL
  87 + stb r3,0x3(r5)
  88 + lis r3,0x8000 # ADDR_10
  89 + ori r3,r3,0x0010
  90 + stwbrx r3,0,r4
  91 + lis r3,0x0000 # LMBAR
  92 + ori r3,r3,0x0008
  93 + li r8, 0x0
  94 + stwbrx r3,r8,r5
  95 + lis r3,0x8000 # ADDR_14
  96 + ori r3,r3,0x0014
  97 + stwbrx r3,0,r4
  98 + lis r3,0xF000 # PCSRBAR
  99 + ori r3,r3,0x0000
  100 + li r8, 0x0
  101 + stwbrx r3,r8,r5
  102 + lis r3,0x8000 # ADDR_3C
  103 + ori r3,r3,0x003C
  104 + stwbrx r3,0,r4
  105 + li r3,0x00 # ILR
  106 + stb r3,0x0(r5)
  107 + lis r3,0x8000 # ADDR_3D
  108 + ori r3,r3,0x003D
  109 + stwbrx r3,0,r4
  110 + li r3,0x01 # INTPIN
  111 + stb r3,0x1(r5)
  112 + lis r3,0x8000 # ADDR_3E
  113 + ori r3,r3,0x003E
  114 + stwbrx r3,0,r4
  115 + li r3,0x00 # MIN_GNT
  116 + stb r3,0x2(r5)
  117 + lis r3,0x8000 # ADDR_3F
  118 + ori r3,r3,0x003F
  119 + stwbrx r3,0,r4
  120 + li r3,0x00 # MAX_LAT
  121 + stb r3,0x3(r5)
  122 + lis r3,0x8000 # ADDR_40
  123 + ori r3,r3,0x0040
  124 + stwbrx r3,0,r4
  125 + li r3,0x00 # BUSNB
  126 + stb r3,0x0(r5)
  127 + lis r3,0x8000 # ADDR_41
  128 + ori r3,r3,0x0041
  129 + stwbrx r3,0,r4
  130 + li r3,0x00 # SBUSNB
  131 + stb r3,0x1(r5)
  132 + lis r3,0x8000 # ADDR_46
  133 + ori r3,r3,0x0046
  134 + stwbrx r3,0,r4
  135 +# li r3,0xE080 # PCIARB
  136 + li r3,-0x1F80 # PCIARB
  137 + li r8, 0x2
  138 + sthbrx r3,r8,r5
  139 + lis r3,0x8000 # ADDR_70
  140 + ori r3,r3,0x0070
  141 + stwbrx r3,0,r4
  142 + li r3,0x0000 # PMCR1
  143 + li r8, 0x0
  144 + sthbrx r3,r8,r5
  145 + lis r3,0x8000 # ADDR_72
  146 + ori r3,r3,0x0072
  147 + stwbrx r3,0,r4
  148 + li r3,0xC0 # PMCR2
  149 + stb r3,0x2(r5)
  150 + lis r3,0x8000 # ADDR_73
  151 + ori r3,r3,0x0073
  152 + stwbrx r3,0,r4
  153 + li r3,0xEF # ODCR
  154 + stb r3,0x3(r5)
  155 + lis r3,0x8000 # ADDR_74
  156 + ori r3,r3,0x0074
  157 + stwbrx r3,0,r4
  158 + li r3,0x7D00 # CLKDCR
  159 + li r8, 0x0
  160 + sthbrx r3,r8,r5
  161 + lis r3,0x8000 # ADDR_76
  162 + ori r3,r3,0x0076
  163 + stwbrx r3,0,r4
  164 + li r3,0x00 # MDCR
  165 + stb r3,0x2(r5)
  166 + lis r6,0xFCE0
  167 + ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
  168 + lis r3,0x8000 # ADDR_78
  169 + ori r3,r3,0x0078
  170 + stwbrx r3,0,r4
  171 + lis r3,0xFCE0 # EUMBBAR
  172 + ori r3,r3,0x0000
  173 + li r8, 0x0
  174 + stwbrx r3,r8,r5
  175 + lis r3,0x8000 # ADDR_80
  176 + ori r3,r3,0x0080
  177 + stwbrx r3,0,r4
  178 + lis r3,0xFFFF # MSADDR1
  179 + ori r3,r3,0x4000
  180 + li r8, 0x0
  181 + stwbrx r3,r8,r5
  182 + lis r3,0x8000 # ADDR_84
  183 + ori r3,r3,0x0084
  184 + stwbrx r3,0,r4
  185 + lis r3,0xFFFF # MSADDR2
  186 + ori r3,r3,0xFFFF
  187 + li r8, 0x0
  188 + stwbrx r3,r8,r5
  189 + lis r3,0x8000 # ADDR_88
  190 + ori r3,r3,0x0088
  191 + stwbrx r3,0,r4
  192 + lis r3,0x0303 # EMSADDR1
  193 + ori r3,r3,0x0000
  194 + li r8, 0x0
  195 + stwbrx r3,r8,r5
  196 + lis r3,0x8000 # ADDR_8C
  197 + ori r3,r3,0x008C
  198 + stwbrx r3,0,r4
  199 + lis r3,0x0303 # EMSADDR2
  200 + ori r3,r3,0x0303
  201 + li r8, 0x0
  202 + stwbrx r3,r8,r5
  203 + lis r3,0x8000 # ADDR_90
  204 + ori r3,r3,0x0090
  205 + stwbrx r3,0,r4
  206 + lis r3,0xFFFF # EMEADDR1
  207 + ori r3,r3,0x7F3F
  208 + li r8, 0x0
  209 + stwbrx r3,r8,r5
  210 + lis r3,0x8000 # ADDR_94
  211 + ori r3,r3,0x0094
  212 + stwbrx r3,0,r4
  213 + lis r3,0xFFFF # EMEADDR2
  214 + ori r3,r3,0xFFFF
  215 + li r8, 0x0
  216 + stwbrx r3,r8,r5
  217 + lis r3,0x8000 # ADDR_98
  218 + ori r3,r3,0x0098
  219 + stwbrx r3,0,r4
  220 + lis r3,0x0303 # EXTEMEM1
  221 + ori r3,r3,0x0000
  222 + li r8, 0x0
  223 + stwbrx r3,r8,r5
  224 + lis r3,0x8000 # ADDR_9C
  225 + ori r3,r3,0x009C
  226 + stwbrx r3,0,r4
  227 + lis r3,0x0303 # EXTEMEM2
  228 + ori r3,r3,0x0303
  229 + li r8, 0x0
  230 + stwbrx r3,r8,r5
  231 + lis r3,0x8000 # ADDR_A0
  232 + ori r3,r3,0x00A0
  233 + stwbrx r3,0,r4
  234 + li r3,0x03 # MEMBNKEN
  235 + stb r3,0x0(r5)
  236 + lis r3,0x8000 # ADDR_A3
  237 + ori r3,r3,0x00A3
  238 + stwbrx r3,0,r4
  239 + li r3,0x00 # MEMPMODE
  240 + stb r3,0x3(r5)
  241 + lis r3,0x8000 # ADDR_B8
  242 + ori r3,r3,0x00B8
  243 + stwbrx r3,0,r4
  244 + li r3,0x00 # ECCCNT
  245 + stb r3,0x0(r5)
  246 + lis r3,0x8000 # ADDR_B9
  247 + ori r3,r3,0x00B9
  248 + stwbrx r3,0,r4
  249 + li r3,0x00 # ECCTRG
  250 + stb r3,0x1(r5)
  251 + lis r3,0x8000 # ADDR_C0
  252 + ori r3,r3,0x00C0
  253 + stwbrx r3,0,r4
  254 + li r3,0xFF # ERRENR1
  255 + stb r3,0x0(r5)
  256 + lis r3,0x8000 # ADDR_C1
  257 + ori r3,r3,0x00C1
  258 + stwbrx r3,0,r4
  259 + li r3,0x00 # ERRDR1
  260 + stb r3,0x1(r5)
  261 + lis r3,0x8000 # ADDR_C3
  262 + ori r3,r3,0x00C3
  263 + stwbrx r3,0,r4
  264 + li r3,0x50 # IPBESR
  265 + stb r3,0x3(r5)
  266 + lis r3,0x8000 # ADDR_C4
  267 + ori r3,r3,0x00C4
  268 + stwbrx r3,0,r4
  269 + li r3,0xBF # ERRENR2
  270 + stb r3,0x0(r5)
  271 + lis r3,0x8000 # ADDR_C5
  272 + ori r3,r3,0x00C5
  273 + stwbrx r3,0,r4
  274 + li r3,0x00 # ERRDR2
  275 + stb r3,0x1(r5)
  276 + lis r3,0x8000 # ADDR_C7
  277 + ori r3,r3,0x00C7
  278 + stwbrx r3,0,r4
  279 + li r3,0x00 # PCIBESR
  280 + stb r3,0x3(r5)
  281 + lis r3,0x8000 # ADDR_C8
  282 + ori r3,r3,0x00C8
  283 + stwbrx r3,0,r4
  284 + lis r3,0x0000 # BERRADDR
  285 + ori r3,r3,0xE0FE
  286 + li r8, 0x0
  287 + stwbrx r3,r8,r5
  288 + lis r3,0x8000 # ADDR_E0
  289 + ori r3,r3,0x00E0
  290 + stwbrx r3,0,r4
  291 + li r3,0xC0 # AMBOR
  292 + stb r3,0x0(r5)
  293 + lis r3,0x8000 # ADDR_F4
  294 + ori r3,r3,0x00F4
  295 + stwbrx r3,0,r4
  296 + lis r3,0x0000 # MCCR2
  297 + ori r3,r3,0x020C
  298 + li r8, 0x0
  299 + stwbrx r3,r8,r5
  300 + lis r3,0x8000 # ADDR_F8
  301 + ori r3,r3,0x00F8
  302 + stwbrx r3,0,r4
  303 + lis r3,0x0230 # MCCR3
  304 + ori r3,r3,0x0000
  305 + li r8, 0x0
  306 + stwbrx r3,r8,r5
  307 + lis r3,0x8000 # ADDR_FC
  308 + ori r3,r3,0x00FC
  309 + stwbrx r3,0,r4
  310 + lis r3,0x2532 # MCCR4
  311 + ori r3,r3,0x2220
  312 + li r8, 0x0
  313 + stwbrx r3,r8,r5
  314 + lis r3,0x8000 # ADDR_F0
  315 + ori r3,r3,0x00F0
  316 + stwbrx r3,0,r4
  317 + lis r3,0xFFC8 # MCCR1
  318 + ori r3,r3,0x0000
  319 + li r8, 0x0
  320 + stwbrx r3,r8,r5
  321 + lis r3,0x8000 # ADDR_A8
  322 + ori r3,r3,0x00A8
  323 + stwbrx r3,0,r4
  324 + lis r3,0xFF14 # PICR1
  325 + ori r3,r3,0x1CC8
  326 + li r8, 0x0
  327 + stwbrx r3,r8,r5
  328 + lis r3,0x8000 # ADDR_AC
  329 + ori r3,r3,0x00AC
  330 + stwbrx r3,0,r4
  331 + lis r3,0x0000 # PICR2
  332 + ori r3,r3,0x0000
  333 + li r8, 0x0
  334 + stwbrx r3,r8,r5
  335 +
  336 + blr
  1 +/*
  2 + * (C) Copyright 2002 ELTEC Elektronik AG
  3 + * Frank Gottschling <fgottschling@eltec.de>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * PCI initialisation for the MPC10x.
  26 + */
  27 +
  28 +#include <common.h>
  29 +#include <pci.h>
  30 +#include <mpc106.h>
  31 +
  32 +#ifdef CONFIG_PCI
  33 +
  34 +struct pci_controller local_hose;
  35 +
  36 +void pci_init_board(void)
  37 +{
  38 + struct pci_controller* hose = (struct pci_controller *)&local_hose;
  39 + u16 reg16;
  40 +
  41 + hose->first_busno = 0;
  42 + hose->last_busno = 0xff;
  43 +
  44 + pci_set_region(hose->regions + 0,
  45 + CFG_PCI_MEMORY_BUS,
  46 + CFG_PCI_MEMORY_PHYS,
  47 + CFG_PCI_MEMORY_SIZE,
  48 + PCI_REGION_MEM | PCI_REGION_MEMORY);
  49 +
  50 + /* PCI memory space */
  51 + pci_set_region(hose->regions + 1,
  52 + CFG_PCI_MEM_BUS,
  53 + CFG_PCI_MEM_PHYS,
  54 + CFG_PCI_MEM_SIZE,
  55 + PCI_REGION_MEM);
  56 +
  57 + /* ISA/PCI memory space */
  58 + pci_set_region(hose->regions + 2,
  59 + CFG_ISA_MEM_BUS,
  60 + CFG_ISA_MEM_PHYS,
  61 + CFG_ISA_MEM_SIZE,
  62 + PCI_REGION_MEM);
  63 +
  64 + /* PCI I/O space */
  65 + pci_set_region(hose->regions + 3,
  66 + CFG_PCI_IO_BUS,
  67 + CFG_PCI_IO_PHYS,
  68 + CFG_PCI_IO_SIZE,
  69 + PCI_REGION_IO);
  70 +
  71 + /* ISA/PCI I/O space */
  72 + pci_set_region(hose->regions + 4,
  73 + CFG_ISA_IO_BUS,
  74 + CFG_ISA_IO_PHYS,
  75 + CFG_ISA_IO_SIZE,
  76 + PCI_REGION_IO);
  77 +
  78 + hose->region_count = 5;
  79 +
  80 + pci_setup_indirect(hose,
  81 + MPC106_REG_ADDR,
  82 + MPC106_REG_DATA);
  83 +
  84 + pci_register_hose(hose);
  85 +
  86 + hose->last_busno = pci_hose_scan(hose);
  87 +
  88 + /* Initialises the MPC10x PCI Configuration regs. */
  89 + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
  90 + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  91 + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
  92 +
  93 + /* Clear non-reserved bits in status register */
  94 + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
  95 +}
  96 +
  97 +#endif /* CONFIG_PCI */
board/ppmc7xx/ppmc7xx.c
Diff comments   View file @ f5e0d03
  1 +/*
  2 + * ppmc7xx.c
  3 + * ---------
  4 + *
  5 + * Main board-specific routines for Wind River PPMC 7xx/74xx board.
  6 + *
  7 + * By Richard Danter (richard.danter@windriver.com)
  8 + * Copyright (C) 2005 Wind River Systems
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <command.h>
  13 +
  14 +
  15 +/* Define some MPC107 (memory controller) registers */
  16 +#define MPC107_EUMB_GCR 0xfce41020
  17 +#define MPC107_EUMB_IACKR 0xfce600a0
  18 +
  19 +
  20 +/* Function prototypes */
  21 +extern void unlock_ram_in_cache( void );
  22 +extern void _start_warm(void);
  23 +
  24 +
  25 +/*
  26 + * initdram()
  27 + *
  28 + * This function normally initialises the (S)DRAM of the system. For this board
  29 + * the SDRAM was already initialised by board_asm_init (see init.S) so we just
  30 + * return the size of RAM.
  31 + */
  32 +long initdram( int board_type )
  33 +{
  34 + return CFG_SDRAM_SIZE;
  35 +}
  36 +
  37 +
  38 +/*
  39 + * after_reloc()
  40 + *
  41 + * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
  42 + * us an opportunity to do some additional setup before the rest of the system
  43 + * is initialised. We don't need to do anything, so we just call board_init_r()
  44 + * which should never return.
  45 + */
  46 +void after_reloc( ulong dest_addr, gd_t* gd )
  47 +{
  48 + /* Jump to the main U-Boot board init code */
  49 + board_init_r( gd, dest_addr );
  50 +}
  51 +
  52 +
  53 +/*
  54 + * checkboard()
  55 + *
  56 + * We could do some board level checks here, such as working out what version
  57 + * it is, but for this board we simply display it's name (on the console).
  58 + */
  59 +int checkboard( void )
  60 +{
  61 + puts( "Board: Wind River PPMC 7xx/74xx\n" );
  62 + return 0;
  63 +}
  64 +
  65 +
  66 +/*
  67 + * misc_init_r
  68 + *
  69 + * Used for other setup which needs to be done late in the bring-up phase.
  70 + */
  71 +int misc_init_r( void )
  72 +{
  73 + /* Reset the EPIC and clear pending interrupts */
  74 + out32r(MPC107_EUMB_GCR, 0xa0000000);
  75 + while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
  76 + out32r( MPC107_EUMB_GCR, 0x20000000 );
  77 + while( in32r( MPC107_EUMB_IACKR ) != 0xff );
  78 +
  79 + /* Enable the I-Cache */
  80 + icache_enable();
  81 +
  82 + return 0;
  83 +}
  84 +
  85 +
  86 +/*
  87 + * do_reset()
  88 + *
  89 + * Shell command to reset the board.
  90 + */
  91 +void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
  92 +{
  93 + printf( "Resetting...\n" );
  94 +
  95 + /* Disabe and invalidate cache */
  96 + icache_disable();
  97 + dcache_disable();
  98 +
  99 + /* Jump to warm start (in RAM) */
  100 + _start_warm();
  101 +
  102 + /* Should never get here */
  103 + while(1);
  104 +}
board/ppmc7xx/u-boot.lds
Diff comments   View file @ f5e0d03
  1 +/*
  2 + * (C) Copyright 2001
  3 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
  26 + */
  27 +
  28 +OUTPUT_ARCH(powerpc)
  29 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  30 +/* Do we need any of these for elf?
  31 + __DYNAMIC = 0; */
  32 +SECTIONS
  33 +{
  34 + /* Read-only sections, merged into text segment: */
  35 + . = + SIZEOF_HEADERS;
  36 + .interp : { *(.interp) }
  37 + .hash : { *(.hash) }
  38 + .dynsym : { *(.dynsym) }
  39 + .dynstr : { *(.dynstr) }
  40 + .rel.text : { *(.rel.text) }
  41 + .rela.text : { *(.rela.text) }
  42 + .rel.data : { *(.rel.data) }
  43 + .rela.data : { *(.rela.data) }
  44 + .rel.rodata : { *(.rel.rodata) }
  45 + .rela.rodata : { *(.rela.rodata) }
  46 + .rel.got : { *(.rel.got) }
  47 + .rela.got : { *(.rela.got) }
  48 + .rel.ctors : { *(.rel.ctors) }
  49 + .rela.ctors : { *(.rela.ctors) }
  50 + .rel.dtors : { *(.rel.dtors) }
  51 + .rela.dtors : { *(.rela.dtors) }
  52 + .rel.bss : { *(.rel.bss) }
  53 + .rela.bss : { *(.rela.bss) }
  54 + .rel.plt : { *(.rel.plt) }
  55 + .rela.plt : { *(.rela.plt) }
  56 + .init : { *(.init) }
  57 + .plt : { *(.plt) }
  58 + .text :
  59 + {
  60 + cpu/74xx_7xx/start.o (.text)
  61 +
  62 +/* store the environment in a seperate sector in the boot flash */
  63 +/* . = env_offset; */
  64 +/* common/environment.o(.text) */
  65 +
  66 + *(.text)
  67 + *(.fixup)
  68 + *(.got1)
  69 + }
  70 + _etext = .;
  71 + PROVIDE (etext = .);
  72 + .rodata :
  73 + {
  74 + *(.rodata)
  75 + *(.rodata1)
  76 + *(.rodata.str1.4)
  77 + }
  78 + .fini : { *(.fini) } =0
  79 + .ctors : { *(.ctors) }
  80 + .dtors : { *(.dtors) }
  81 +
  82 + /* Read-write section, merged into data segment: */
  83 + . = (. + 0x00FF) & 0xFFFFFF00;
  84 + _erotext = .;
  85 + PROVIDE (erotext = .);
  86 + .reloc :
  87 + {
  88 + *(.got)
  89 + _GOT2_TABLE_ = .;
  90 + *(.got2)
  91 + _FIXUP_TABLE_ = .;
  92 + *(.fixup)
  93 + }
  94 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
  95 + __fixup_entries = (. - _FIXUP_TABLE_)>>2;
  96 +
  97 + .data :
  98 + {
  99 + *(.data)
  100 + *(.data1)
  101 + *(.sdata)
  102 + *(.sdata2)
  103 + *(.dynamic)
  104 + CONSTRUCTORS
  105 + }
  106 + _edata = .;
  107 + PROVIDE (edata = .);
  108 +
  109 + __u_boot_cmd_start = .;
  110 + .u_boot_cmd : { *(.u_boot_cmd) }
  111 + __u_boot_cmd_end = .;
  112 +
  113 +
  114 + __start___ex_table = .;
  115 + __ex_table : { *(__ex_table) }
  116 + __stop___ex_table = .;
  117 +
  118 + . = ALIGN(256);
  119 + __init_begin = .;
  120 + .text.init : { *(.text.init) }
  121 + .data.init : { *(.data.init) }
  122 + . = ALIGN(256);
  123 + __init_end = .;
  124 +
  125 + __bss_start = .;
  126 + .bss :
  127 + {
  128 + *(.sbss) *(.scommon)
  129 + *(.dynbss)
  130 + *(.bss)
  131 + *(COMMON)
  132 + }
  133 + _end = . ;
  134 + PROVIDE (end = .);
  135 +}
... ... @@ -215,7 +215,8 @@
215 215  
216 216 #if !defined(CONFIG_PCIPPC2) && \
217 217 !defined(CONFIG_BAB7xx) && \
218   - !defined(CONFIG_ELPPC)
  218 + !defined(CONFIG_ELPPC) && \
  219 + !defined(CONFIG_PPMC7XX)
219 220 /* no generic way to do board reset. simply call soft_reset. */
220 221 void
221 222 do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
cpu/74xx_7xx/start.S
Diff comments   View file @ f5e0d03
... ... @@ -756,7 +756,8 @@
756 756 #if defined(CONFIG_AMIGAONEG3SE) || \
757 757 defined(CONFIG_DB64360) || \
758 758 defined(CONFIG_DB64460) || \
759   - defined(CONFIG_CPCI750)
  759 + defined(CONFIG_CPCI750) || \
  760 + defined(CONFIG_PPMC7XX)
760 761 mr r4, r9 /* Use RAM copy of the global data */
761 762 #endif
762 763 bl after_reloc
... ... @@ -163,7 +163,7 @@
163 163 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
164 164 #endif
165 165 for (bdf = PCI_BDF(bus,0,0);
166   -#ifdef CONFIG_ELPPC
  166 +#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
167 167 bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
168 168 #else
169 169 bdf < PCI_BDF(bus+1,0,0);
include/configs/ppmc7xx.h
Diff comments   View file @ f5e0d03
  1 +/*
  2 + * ppmc7xx.h
  3 + * ---------
  4 + *
  5 + * Wind River PPMC 7xx/74xx board configuration file.
  6 + *
  7 + * By Richard Danter (richard.danter@windriver.com)
  8 + * Copyright (C) 2005 Wind River Systems
  9 + */
  10 +
  11 +
  12 +#ifndef __CONFIG_H
  13 +#define __CONFIG_H
  14 +
  15 +#define CONFIG_PPMC7XX
  16 +
  17 +
  18 +/*===================================================================
  19 + *
  20 + * User configurable settings - Modify to your preference
  21 + *
  22 + *===================================================================
  23 + */
  24 +
  25 +/*
  26 + * Debug
  27 + *
  28 + * DEBUG - Define this is you want extra debug info
  29 + * GTREGREAD - Required to build with debug
  30 + * do_bdinfo - Required to build with debug
  31 + */
  32 +
  33 +#undef DEBUG
  34 +#define GTREGREAD(x) 0xFFFFFFFF
  35 +#define do_bdinfo(a,b,c,d)
  36 +
  37 +
  38 +/*
  39 + * CPU type
  40 + *
  41 + * CONFIG_7xx - We have a 750 or 755 CPU
  42 + * CONFIG_74xx - We have a 7400 CPU
  43 + * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
  44 + * CONFIG_BUS_CLK - System bus clock in Hz
  45 + */
  46 +
  47 +#define CONFIG_7xx
  48 +#undef CONFIG_74xx
  49 +#undef CONFIG_ALTIVEC
  50 +#define CONFIG_BUS_CLK 66000000
  51 +
  52 +
  53 +/*
  54 + * Monitor configuration
  55 + *
  56 + * CONFIG_COMMANDS - List of command sets to include in shell
  57 + *
  58 + * The following command sets have been tested and known to work:
  59 + *
  60 + * CFG_CMD_CACHE - Cache control commands
  61 + * CFG_CMD_MEMORY - Memory display, change and test commands
  62 + * CFG_CMD_FLASH - Erase and program flash
  63 + * CFG_CMD_ENV - Environment commands
  64 + * CFG_CMD_RUN - Run commands stored in env vars
  65 + * CFG_CMD_ELF - Load ELF files
  66 + * CFG_CMD_NET - Networking/file download commands
  67 + * CFG_CMD_PING - ICMP Echo Request command
  68 + * CFG_CMD_PCI - PCI Bus scanning command
  69 + */
  70 +
  71 +#define CONFIG_COMMANDS ( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) | \
  72 + CFG_CMD_FLASH | \
  73 + CFG_CMD_ENV | \
  74 + CFG_CMD_RUN | \
  75 + CFG_CMD_ELF | \
  76 + CFG_CMD_NET | \
  77 + CFG_CMD_PING | \
  78 + CFG_CMD_PCI)
  79 +
  80 +
  81 +/*
  82 + * Serial configuration
  83 + *
  84 + * CONFIG_CONS_INDEX - Serial console port number (COM1)
  85 + * CONFIG_BAUDRATE - Serial speed
  86 + */
  87 +
  88 +#define CONFIG_CONS_INDEX 1
  89 +#define CONFIG_BAUDRATE 9600
  90 +
  91 +
  92 +/*
  93 + * PCI config
  94 + *
  95 + * CONFIG_PCI - Enable PCI bus
  96 + * CONFIG_PCI_PNP - Enable Plug & Play support
  97 + * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
  98 + */
  99 +
  100 +#define CONFIG_PCI
  101 +#define CONFIG_PCI_PNP
  102 +#undef CONFIG_PCI_SCAN_SHOW
  103 +
  104 +
  105 +/*
  106 + * Network config
  107 + *
  108 + * CONFIG_NET_MULTI - Support for multiple network interfaces
  109 + * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
  110 + * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
  111 + */
  112 +
  113 +#define CONFIG_NET_MULTI
  114 +#define CONFIG_EEPRO100
  115 +#define CONFIG_EEPRO100_SROM_WRITE
  116 +
  117 +
  118 +/*
  119 + * Enable extra init functions
  120 + *
  121 + * CONFIG_MISC_INIT_F - Call pre-relocation init functions
  122 + * CONFIG_MISC_INIT_R - Call post relocation init functions
  123 + */
  124 +
  125 +#undef CONFIG_MISC_INIT_F
  126 +#define CONFIG_MISC_INIT_R
  127 +
  128 +
  129 +/*
  130 + * Boot config
  131 + *
  132 + * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
  133 + * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
  134 + */
  135 +
  136 +#define CONFIG_BOOTCOMMAND \
  137 + "bootp;" \
  138 + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
  139 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
  140 + "bootm"
  141 +#define CONFIG_BOOTDELAY 5
  142 +
  143 +
  144 +/*===================================================================
  145 + *
  146 + * Board configuration settings - You should not need to modify these
  147 + *
  148 + *===================================================================
  149 + */
  150 +
  151 +
  152 +#include <cmd_confdefs.h>
  153 +
  154 +
  155 +/*
  156 + * Memory map
  157 + *
  158 + * This board runs in a standard CHRP (Map-B) configuration.
  159 + *
  160 + * Type Start End Size Width Chip Sel
  161 + * ----------- ----------- ----------- ------- ------- --------
  162 + * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
  163 + * User LED's 0x78000000 RCS3
  164 + * UART 0x7C000000 RCS2
  165 + * Mailbox 0xFF000000 RCS1
  166 + * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
  167 + *
  168 + * Flash sectors are laid out as follows.
  169 + *
  170 + * Sector Start End Size Comments
  171 + * ------- ----------- ----------- ------- -----------
  172 + * 0 0xFFC00000 0xFFC3FFFF 256KB
  173 + * 1 0xFFC40000 0xFFC7FFFF 256KB
  174 + * 2 0xFFC80000 0xFFCBFFFF 256KB
  175 + * 3 0xFFCC0000 0xFFCFFFFF 256KB
  176 + * 4 0xFFD00000 0xFFD3FFFF 256KB
  177 + * 5 0xFFD40000 0xFFD7FFFF 256KB
  178 + * 6 0xFFD80000 0xFFDBFFFF 256KB
  179 + * 7 0xFFDC0000 0xFFDFFFFF 256KB
  180 + * 8 0xFFE00000 0xFFE3FFFF 256KB
  181 + * 9 0xFFE40000 0xFFE7FFFF 256KB
  182 + * 10 0xFFE80000 0xFFEBFFFF 256KB
  183 + * 11 0xFFEC0000 0xFFEFFFFF 256KB
  184 + * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
  185 + * 13 0xFFF40000 0xFFF7FFFF 256KB
  186 + * 14 0xFFF80000 0xFFFBFFFF 256KB
  187 + * 15 0xFFFC0000 0xFFFDFFFF 128KB
  188 + * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
  189 + * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
  190 + * 18 0xFFFF0000 0xFFFFFFFF 64KB
  191 + */
  192 +
  193 +
  194 +/*
  195 + * SDRAM config - see memory map details above.
  196 + *
  197 + * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
  198 + * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
  199 + */
  200 +
  201 +#define CFG_SDRAM_BASE 0x00000000
  202 +#define CFG_SDRAM_SIZE 0x04000000
  203 +
  204 +
  205 +/*
  206 + * Flash config - see memory map details above.
  207 + *
  208 + * CFG_FLASH_BASE - Start address of flash memory
  209 + * CFG_FLASH_SIZE - Total size of contiguous flash mem
  210 + * CFG_FLASH_ERASE_TOUT - Erase timeout in ms
  211 + * CFG_FLASH_WRITE_TOUT - Write timeout in ms
  212 + * CFG_MAX_FLASH_BANKS - Number of banks of flash on board
  213 + * CFG_MAX_FLASH_SECT - Number of sectors in a bank
  214 + */
  215 +
  216 +#define CFG_FLASH_BASE 0xFFC00000
  217 +#define CFG_FLASH_SIZE 0x00400000
  218 +#define CFG_FLASH_ERASE_TOUT 250000
  219 +#define CFG_FLASH_WRITE_TOUT 5000
  220 +#define CFG_MAX_FLASH_BANKS 1
  221 +#define CFG_MAX_FLASH_SECT 19
  222 +
  223 +
  224 +/*
  225 + * Monitor config - see memory map details above
  226 + *
  227 + * CFG_MONITOR_BASE - Base address of monitor code
  228 + * CFG_MALLOC_LEN - Size of malloc pool (128KB)
  229 + */
  230 +
  231 +#define CFG_MONITOR_BASE TEXT_BASE
  232 +#define CFG_MALLOC_LEN 0x20000
  233 +
  234 +
  235 +/*
  236 + * Command shell settings
  237 + *
  238 + * CFG_BARGSIZE - Boot Argument buffer size
  239 + * CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
  240 + * CFG_CBSIZE - Console Buffer (input) size
  241 + * CFG_LOAD_ADDR - Default load address
  242 + * CFG_LONGHELP - Provide more detailed help
  243 + * CFG_MAXARGS - Number of args accepted by monitor commands
  244 + * CFG_MEMTEST_START - Start address of test to run on RAM
  245 + * CFG_MEMTEST_END - End address of RAM test
  246 + * CFG_PBSIZE - Print Buffer (output) size
  247 + * CFG_PROMPT - Prompt string
  248 + */
  249 +
  250 +#define CFG_BARGSIZE 1024
  251 +#define CFG_BOOTMAPSZ 0x800000
  252 +#define CFG_CBSIZE 1024
  253 +#define CFG_LOAD_ADDR 0x100000
  254 +#define CFG_LONGHELP
  255 +#define CFG_MAXARGS 16
  256 +#define CFG_MEMTEST_START 0x00040000
  257 +#define CFG_MEMTEST_END 0x00040100
  258 +#define CFG_PBSIZE 1024
  259 +#define CFG_PROMPT "=> "
  260 +
  261 +
  262 +/*
  263 + * Environment config - see memory map details above
  264 + *
  265 + * CFG_ENV_IS_IN_FLASH - The env variables are stored in flash
  266 + * CFG_ENV_ADDR - Address of the sector containing env vars
  267 + * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
  268 + * CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
  269 + */
  270 +
  271 +#define CFG_ENV_IS_IN_FLASH 1
  272 +#define CFG_ENV_ADDR 0xFFFE0000
  273 +#define CFG_ENV_SIZE 0x1000
  274 +#define CFG_ENV_ADDR_REDUND 0xFFFE8000
  275 +#define CFG_ENV_SIZE_REDUND 0x1000
  276 +#define CFG_ENV_SECT_SIZE 0x8000
  277 +
  278 +
  279 +/*
  280 + * Initial RAM config
  281 + *
  282 + * Since the main system RAM is initialised very early, we place the INIT_RAM
  283 + * in the main system RAM just above the exception vectors. The contents are
  284 + * copied to top of RAM by the init code.
  285 + *
  286 + * CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
  287 + * CFG_INIT_RAM_END - Size of Init RAM
  288 + * CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
  289 + * CFG_GBL_DATA_OFFSET - Start of global data, top of stack
  290 + */
  291 +
  292 +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
  293 +#define CFG_INIT_RAM_END 0x4000
  294 +#define CFG_GBL_DATA_SIZE 128
  295 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  296 +
  297 +
  298 +/*
  299 + * Initial BAT config
  300 + *
  301 + * BAT0 - System SDRAM
  302 + * BAT1 - LED's and Serial Port
  303 + * BAT2 - PCI Memory
  304 + * BAT3 - PCI I/O including Flash Memory
  305 + */
  306 +
  307 +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  308 +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
  309 +#define CFG_DBAT0L CFG_IBAT0L
  310 +#define CFG_DBAT0U CFG_IBAT0U
  311 +
  312 +#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  313 +#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  314 +#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  315 +#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  316 +
  317 +#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  318 +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  319 +#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  320 +#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  321 +
  322 +#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  323 +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  324 +#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  325 +#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  326 +
  327 +
  328 +/*
  329 + * Cache config
  330 + *
  331 + * CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
  332 + * CFG_L2 - L2 cache enabled if defined
  333 + * L2_INIT - L2 cache init flags
  334 + * L2_ENABLE - L2 cache enable flags
  335 + */
  336 +
  337 +#define CFG_CACHELINE_SIZE 32
  338 +#undef CFG_L2
  339 +#define L2_INIT 0
  340 +#define L2_ENABLE 0
  341 +
  342 +
  343 +/*
  344 + * Clocks config
  345 + *
  346 + * CFG_BUS_HZ - Bus clock frequency in Hz
  347 + * CFG_BUS_CLK - As above (?)
  348 + * CFG_HZ - Decrementer freq in Hz
  349 + */
  350 +
  351 +#define CFG_BUS_HZ CONFIG_BUS_CLK
  352 +#define CFG_BUS_CLK CONFIG_BUS_CLK
  353 +#define CFG_HZ 1000
  354 +
  355 +
  356 +/*
  357 + * Serial port config
  358 + *
  359 + * CFG_BAUDRATE_TABLE - List of valid baud rates
  360 + * CFG_NS16550 - Include the NS16550 driver
  361 + * CFG_NS16550_SERIAL - Include the serial (wrapper) driver
  362 + * CFG_NS16550_CLK - Frequency of reference clock
  363 + * CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
  364 + * CFG_NS16550_COM1 - Base address of 1st serial port
  365 + */
  366 +
  367 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  368 +#define CFG_NS16550
  369 +#define CFG_NS16550_SERIAL
  370 +#define CFG_NS16550_CLK 3686400
  371 +#define CFG_NS16550_REG_SIZE -8
  372 +#define CFG_NS16550_COM1 0x7C000000
  373 +
  374 +
  375 +/*
  376 + * PCI Config - Address Map B (CHRP)
  377 + */
  378 +
  379 +#define CFG_PCI_MEMORY_BUS 0x00000000
  380 +#define CFG_PCI_MEMORY_PHYS 0x00000000
  381 +#define CFG_PCI_MEMORY_SIZE 0x40000000
  382 +#define CFG_PCI_MEM_BUS 0x80000000
  383 +#define CFG_PCI_MEM_PHYS 0x80000000
  384 +#define CFG_PCI_MEM_SIZE 0x7D000000
  385 +#define CFG_ISA_MEM_BUS 0x00000000
  386 +#define CFG_ISA_MEM_PHYS 0xFD000000
  387 +#define CFG_ISA_MEM_SIZE 0x01000000
  388 +#define CFG_PCI_IO_BUS 0x00800000
  389 +#define CFG_PCI_IO_PHYS 0xFE800000
  390 +#define CFG_PCI_IO_SIZE 0x00400000
  391 +#define CFG_ISA_IO_BUS 0x00000000
  392 +#define CFG_ISA_IO_PHYS 0xFE000000
  393 +#define CFG_ISA_IO_SIZE 0x00800000
  394 +#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
  395 +#define CFG_ISA_IO CFG_ISA_IO_PHYS
  396 +#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
  397 +
  398 +
  399 +/*
  400 + * Extra init functions
  401 + *
  402 + * CFG_BOARD_ASM_INIT - Call assembly init code
  403 + */
  404 +
  405 +#define CFG_BOARD_ASM_INIT
  406 +
  407 +
  408 +/*
  409 + * Boot flags
  410 + *
  411 + * BOOTFLAG_COLD - Indicates a power-on boot
  412 + * BOOTFLAG_WARM - Indicates a software reset
  413 + */
  414 +
  415 +#define BOOTFLAG_COLD 0x01
  416 +#define BOOTFLAG_WARM 0x02
  417 +
  418 +
  419 +#endif /* __CONFIG_H */
... ... @@ -7,6 +7,9 @@
7 7 * added prototypes for ns16550.c
8 8 * reduced no of com ports to 2
9 9 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
  10 + *
  11 + * added support for port on 64-bit bus
  12 + * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
10 13 */
11 14  
12 15 #if (CFG_NS16550_REG_SIZE == 1)
... ... @@ -81,6 +84,25 @@
81 84 unsigned char osc_12m_sel;
82 85 int pad10:24;
83 86 #endif
  87 +} __attribute__ ((packed));
  88 +#elif (CFG_NS16550_REG_SIZE == -8)
  89 +struct NS16550 {
  90 + unsigned char rbr; /* 0 */
  91 + unsigned char pad0[7];
  92 + unsigned char ier; /* 1 */
  93 + unsigned char pad1[7];
  94 + unsigned char fcr; /* 2 */
  95 + unsigned char pad2[7];
  96 + unsigned char lcr; /* 3 */
  97 + unsigned char pad3[7];
  98 + unsigned char mcr; /* 4 */
  99 + unsigned char pad4[7];
  100 + unsigned char lsr; /* 5 */
  101 + unsigned char pad5[7];
  102 + unsigned char msr; /* 6 */
  103 + unsigned char pad6[7];
  104 + unsigned char scr; /* 7 */
  105 + unsigned char pad7[7];
84 106 } __attribute__ ((packed));
85 107 #else
86 108 #error "Please define NS16550 registers size."