04 Apr, 2020
2 commits
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USB 3 host controller may be described in ACPI to allow users alter
the properties or other features. Describe it for Intel Tangier SoC.Signed-off-by: Andy Shevchenko
Reviewed-by: Bin Meng -
There is established way to provide I²C timings, or actually counters,
to the OS via ACPI. Fill them for Intel Merrifield platform.Signed-off-by: Andy Shevchenko
Reviewed-by: Simon Glass
05 Mar, 2020
1 commit
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The function cpu_x86_get_count() is also useful for other modules.
Make it non-static and add a prototype + description.Signed-off-by: Wolfgang Wallner
Reviewed-by: Bin Meng
19 Feb, 2020
3 commits
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The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.Factor them out to , and make all drivers to
include instead of .If we need to differentiate them for some architectures, we can
move the generic definitions to .Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.Signed-off-by: Masahiro Yamada
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dma_unmap_single() takes the dma address, not virtual address.
Signed-off-by: Masahiro Yamada
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Make dma_map_single() return the dma address, and remove the
pointless volatile.Signed-off-by: Masahiro Yamada
04 Feb, 2020
3 commits
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The code in this file is not specific to Apollo Lake. According to
coreboot sources (where this code comes from), it is common to at least:
* Apollo Lake
* Cannon Lake
* Ice Lake
* SkylakeSigned-off-by: Wolfgang Wallner
Reviewed-by: Simon Glass
Reviewed-by: Bin Meng -
ITSS stands for "Interrupt Timer Subsystem", so add that term to the
description of the relevant files.Signed-off-by: Wolfgang Wallner
Reviewed-by: Simon Glass
Reviewed-by: Bin Meng -
Since mid 2016, coreboot has additional fields in the serial struct that
it passes down to U-Boot. Add these so we are in sync.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
26 Jan, 2020
1 commit
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Subsystems such as USB expect dma_map_single() and dma_unmap_single() to
do dcache flush/invalidate operations as required. For example, see
see drivers/usb/gadget/udc/udc-core.c::usb_gadget_map_request().
Currently drivers do this locally, (see drivers/usb/dwc3/ep0.c,
drivers/mtd/nand/raw/denali.c etc..)
Update arch specific dma_map_single() and dma_unmap_single() APIs to do
cache flush/invalidate operations, so that drivers need not implement
them locally.Signed-off-by: Vignesh Raghavendra
Reviewed-by: Masahiro Yamada
Reviewed-by: Rick Chen
15 Dec, 2019
25 commits
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These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add some fixed IO and mmap addresses for use in the device tree and with
some early-init code.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.As well as a pinctrl driver this provides a GPIO driver based on the same
code.Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This subsystem is present on various Intel SoCs.
Add very basic support for taking an lpss device out of reset.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
common API file.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
FSP-S is used by the notify call after it has been used for silicon init.
To avoid having to load it again, add a field to store the location.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.Support for the FSP_S binary is also included.
Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI
reads.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This function is only used within the implementation so make it static.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add support for a second cache type, for Apollo Lake.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
With Apollo Lake we need to support a normal cache, which almost never
changes and a much smaller 'variable' cache which changes every time.Update the code to add a cache type, use an array for the caches and use a
for loop to iterate over the caches.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.Add a new mrc_cache member instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollo Lake's 24-byte variable-data record.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff800000.However some recent Intel CPUs do not use a simple 1:1 memory map. Instead
the map starts at a different address and not all of the SPI flash is
accessible through the map. This 'Fast SPI' feature requires that U-Boot
check the location of the map. It is also possible (optionally) to read
from the SPI flash using a driver.Add support for booting from Fast SPI. The memory-mapped version is used
by both TPL and SPL on Apollo Lake.In respect of a SPI flash driver, the actual SPI driver is ich.c - this
just adds a few helper functions and definitions.This is used by Apollo Lake.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Drivers are not allowed to use static data since they may be used in SPL
where BSS is not available.It is possible that driver model may provide support for numbering devices
in the future. But for now, move this to global_data.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
03 Nov, 2019
3 commits
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For TPL we only need to set up the features and identify the CPU to a
basic level. Add a function to handle that.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
The x86 power unit handles power management. Support initing this device
which is modelled as a new type of system controller since there are no
operations needed.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.Update the code to use a separate flag instead.
Signed-off-by: Simon Glass
Tested-by: Aiden Park
Reviewed-by: Aiden Park
Reviewed-by: Bin Meng
08 Oct, 2019
2 commits
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Normally U-Boot handles MTRRs through an add/commit process which
overwrites all MTRRs. But in very early boot it is not desirable to clear
the existing MTRRs since they may be in use and it can cause a hang.Add a new mtrr_set_next_var() function which sets up the next available
MTRR to the required region.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
[bmeng: pass 'type' to set_var_mtrr() in mtrr_set_next_var()]
Signed-off-by: Bin Meng -
Add a few more CPU functions that are common on Intel CPUs. Also add
attribution for the code source.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
[bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist();
fix 2 typos in cpu_get_burst_mode_state() comments]
Signed-off-by: Bin Meng