27 Apr, 2020
8 commits
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USB OH clock is default enabled by SCFW because it shared
between two USB controller.Signed-off-by: Frank Li
(cherry picked from commit 7a8ec829d4410c51550ad7a589645595042ba541) -
Add clocks required for new i.MX8DXL SoC. Since most of clocks are
same as iMX8QXP, share the same driver but with iMX8DXL new clocks added.Signed-off-by: Fugang Duan
Signed-off-by: Teo Hall
(cherry picked from commit f9c23b2df504c5db5f8f4567ee4c92f2439308fc)
Signed-off-by: Ye Li -
Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocksSigned-off-by: Ye Li
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Add PCIE relevant clocks to clk-imx8 driver, so PCIE IMX driver can
set the clocks through DTBSigned-off-by: Ye Li
(cherry picked from commit cf86e72f32fdd25903b6afb5a803d6e9ccf7d15b) -
Add USB relevant clocks to support usb clock settings for both
DM USB host and gadget driversSigned-off-by: Ye Li
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Add the SATA clocks to clk-imx8, so we can use clk uclass interfaces
to access the clocks in AHCI driver.Signed-off-by: Ye Li
(cherry picked from commit 87adf3f28ffc639240561d90c1d3c51ec29aae80) -
Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocksSigned-off-by: Ye Li
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Add flexspi relevant clocks, and fix set parent clock, so we can
assign clocks through DTBSigned-off-by: Ye Li
23 Apr, 2020
1 commit
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Update imx8 clock driver to support LPCG and full clocks tree for some
modules aligned with kernel.We classify the clock into serveral types: slice, fixed, lpcg, gpr and mux.
Generally slice and fixed clocks are the sources. lpcg, gpr and mux are
the downstream of those sources and are used for gating, muxing or dividing
functions.This patch replaces the functions defined in imx8qm and imx8qxp with the clock
tables of different clock types. clk-imx8 use unified functions to process these
clock tables.Note: since the clock depends on the power domain of its resource, must power
on the resource firstly, then we can get the clock. Otherwise, we can't access lpcg.
Thus, the clock dump only works for the slice clock.Signed-off-by: Ye Li
06 Apr, 2020
1 commit
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This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().Signed-off-by: Chee Hong Ang
Reviewed-by: Ley Foon Tan
02 Apr, 2020
1 commit
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During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Tested-by: Peter Robinson
30 Mar, 2020
1 commit
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The fdtdec_get_addr() does not take into account values set in #address-cells
and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit
systems. This is true for most DTs, however there are exceptions. Switch to
fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells
values into consideration, otherwise the reset controller node register
offset is incorrectly parsed.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
05 Mar, 2020
1 commit
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If all branches of a switch statement have a return instruction, all
subsequent lines are unreachable.Identified with cppcheck.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Lukasz Majewski
Reviewed-by: Simon Glass
28 Feb, 2020
1 commit
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The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling versal_pm_clock_get_name() in versal_get_clock_info() function.Signed-off-by: Rajan Vaja
Signed-off-by: Michal Simek
14 Feb, 2020
2 commits
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- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme -
Solve type issue in stm32mp1_lse_enable and stm32mp1_clktree.
This patch solves the warnings when compiling with W=1
on stm32mp1 board:clk_stm32mp1.c: In function ‘stm32mp1_lse_enable’:
clk_stm32mp1.c:1238:15: warning: comparison of integer expressions
of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
[-Wsign-compare]
clk_stm32mp1.c:1239:13: warning: comparison of integer expressions
of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
[-Wsign-compare]clk_stm32mp1.c: In function ‘stm32mp1_clktree’:
clk_stm32mp1.c:1814:17: warning: comparison of integer expressions
of different signedness: ‘int’ and ‘unsigned int’
[-Wsign-compare]Signed-off-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
13 Feb, 2020
2 commits
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HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin -
Pll bypass has priority over enable/disable.
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin
11 Feb, 2020
1 commit
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sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
07 Feb, 2020
1 commit
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So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.This driver can be expanded later as needed.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
06 Feb, 2020
3 commits
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
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At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin -
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().Signed-off-by: Simon Glass
30 Jan, 2020
1 commit
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Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.The rest of rockchip cru files will add it in future.
Reviewed-by: Kever Yang
Signed-off-by: Jagan Teki
27 Jan, 2020
3 commits
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Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.Signed-off-by: Giulio Benetti
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Guard 'mfd==0' to prevent 'divide by zero' issue in
clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd
should never be 0 at all.Signed-off-by: Giulio Benetti
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Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.Signed-off-by: Giulio Benetti
26 Jan, 2020
4 commits
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dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE.
Signed-off-by: Sean Anderson
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clk_get_by_name() requires clk_get_by_id() that is not available if
CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else
condition of #if CONFIG_IS_ENABLED(OF_PLATDATA).Signed-off-by: Giulio Benetti
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It will ease debug when uclass_get_device_by_name failed with
more error info printed out.Signed-off-by: Peng Fan
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mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.This commit change the return type of mtk_clk_find_parent_rate to
ulong.Signed-off-by: Fabien Parent
21 Jan, 2020
1 commit
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K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodesK3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA supportDRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/tiAM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
20 Jan, 2020
1 commit
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Add slack to the clock frequency parameters passed to firmware within
clk_set_rate. min-freq is changed to 0 and max-rate is changed to
ULONG_MAX. This fixes certain issues with pll clock rounding when the
firmware is not able to set the frequency exactly to the target, the
current implementation fails if the available frequency is even 1Hz off
the target. With the change, the firmware still tries its best to set
the frequency as close as possible to the target.Reported-by: Vishal Mahaveer
Signed-off-by: Lokesh Vutla
Signed-off-by: Tero Kristo
Signed-off-by: Lokesh Vutla
18 Jan, 2020
2 commits
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This function related to timer and most of the timer functions are in
time.h, so move this function there.Signed-off-by: Simon Glass
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These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.Signed-off-by: Simon Glass
16 Jan, 2020
5 commits
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This patch fix clock-rate overflow problem in mediatek
clock driver common part.Signed-off-by: Sam Shih
Reviewed-by: Ryder Lee -
This patch add clock driver for MediaTek MT7622 SoC.
Signed-off-by: Ryder Lee
Signed-off-by: Sam Shih -
This is used to avoid clk_enable() return -ENOSYS.
Signed-off-by: Chunfeng Yun
Reviewed-by: Simon Glass
Reviewed-by: Ryder Lee -
Sometimes we may need get (optional) clock without a device,
that means use ofnode.
e.g. when the phy node has subnode, and there is no device created
for subnode, in this case, we need these new APIs to get subnode's
clock.Signed-off-by: Chunfeng Yun
Reviewed-by: Simon Glass
Reviewed-by: Ryder Lee -
Add valid check for clk->dev, it's useful when get optional
clock even when the clk point is valid, but its dev will be
NULL.Signed-off-by: Chunfeng Yun
Reviewed-by: Simon Glass
Reviewed-by: Ryder Lee
